Specifications

The Patent Office Journal 17/12/2010
4447
(12) PATENT APPLICATION PUBLICATION (21) Application No.3542/CHE/2010 A
(19) INDIA
(22) Date of filing of Application :24/11/2010 (43) Publication Date : 17/12/2010
(54) Title of the invention : SECURE LOW POWER FPGA & ASIC IMPLEMENTATION OF MEDIA SECURITY PROCESSOR
USING COMBINED WATERMARKING AND CRYPTOGRAPHY
(51) International classification
:G06T
1/00
(31) Priority Document No :NA
(32) Priority Date :NA
(33) Name of priority country :NA
(86) International Application No
Filing Date
:NA
:NA
(87) International Publication No : NA
(61) Patent of Addition to Application Number
Filing Date
:NA
:NA
(62) Divisional to Application Number
Filing Date
:NA
:NA
(71)Name of Applicant :
1)P KARTHIGAIKUMAR
Address of Applicant :8, ARUMUGA UDAYAR STREET,
TELUNGUPALAYAM, PERUR MAIN ROAD, COIMBATORE
- 641 039 Tamil Nadu India
2)DR. K BASKARAN
(72)Name of Inventor :
1)P KARTHIGAIKUMAR
2)DR. K BASKARAN
(57) Abstract :
A combined hardware based watermarking and cryptography system that includes a transmitter that receives an input, the input being
any of an image or an audio signal, the transmitter including an invisible watermarking unit that embeds secret information over the
input and a boundary of the image is flipped that acts as a watermark, an encryption block that encrypts a watermarked image or audio
signal received from the invisible watermarking unit, a receiver that receives an output from the transmitter, the receiver including a
decryption block that decrypts the output received from the transmitter to obtain the signal from the encrypted data, and a
watermarking extraction block that extracts the watermarked image or audio signal from the signal obtained from the decryption
block.
No. of Pages : 19 No. of Claims : 10