Product data

MFRC631 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 4 February 2014
227433 14 of 120
NXP Semiconductors
MFRC631
High performance ISO/IEC 14443 A/B reader solution
8.4 Host interfaces
8.4.1 Host interface configuration
The MFRC631 supports direct interfacing of various hosts as the SPI, I
2
C, I
2
CL and serial
UART interface type. The MFRC631 resets its interface and checks the current host
interface type automatically having performed a power-up or resuming from power down.
The MFRC631 identifies the host interface by the means of the logic levels on the control
pins after the Cold Reset Phase. This is done by a combination of fixed pin
connections.The following table shows the possible configurations defined by
IFSEL1,IFSEL0:
8.4.2 SPI interface
8.4.2.1 General
The MFRC631 acts as a slave during the SPI communication. The SPI clock SCK has to
be generated by the master. Data communication from the master to the slave uses the
Line MOSI. Line MISO is used to send data back from the MFRC631 to the master.
A serial peripheral interface (SPI compatible) is supported to enable high speed
communication to a host. The implemented SPI compatible interface is according to a
standard SPI interface. The SPI compatible interface can handle data speed of up to 10
Mbit/s. In the communication with a host MFRC631 acts as a slave receiving data from the
external host for register settings and to send and receive data relevant for the
communication on the RF interface.
On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI line
shall be stable on rising edge of the clock line (SCK) and is allowed to change on falling
edge. The same is valid for the MISO line. Data is provided by the MFRC631 on the falling
edge and is stable on the rising edge.The polarity of the clock is low at SPI idle.
Table 7. Connection scheme for detecting the different interface types
Pin Pin Symbol UART SPI I
2
C I
2
C-L
28 IF0 RX MOSI ADR1 ADR1
29 IF1 - SCK SCL SCL
30 IF2 TX MISO ADR2 SDA
31 IF3 1 NSS SDA ADR2
26 IFSEL0 0 0 1 1
27 IFSEL1 0 1 0 1
Fig 9. Connection to host with SPI
001aal998
READER IC
IF1
SCK
IF0
MOSI
IF2
MISO
IF3
NSS