Product data

MFRC631 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 4 February 2014
227433 21 of 120
NXP Semiconductors
MFRC631
High performance ISO/IEC 14443 A/B reader solution
8.4.4.5 I
2
C Acknowledge
An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer, or a
repeated START (Sr) condition to start a new transfer.
A master-receiver shall indicate the end of data to the slave- transmitter by not generating
an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter
shall release the data line to allow the master to generate a STOP (P) or repeated START
(Sr) condition.
8.4.4.6 I
2
C 7-bit addressing
During the I
2
C-bus addressing procedure, the first byte after the START condition is used
to determine which slave will be selected by the master.
Fig 16. Acknowledge on the I
2
C- bus
Fig 17. Data transfer on the I
2
C- bus
001aam302
clock pulse for
acknowledgement
1
SCL FROM
MASTER
DATA OUTPUT
BY RECEIVERER
DATA OUTPUT
BY TRANSMITTER
289
acknowledge
START
condition
S
not acknowledge
001aam303
MSB acknowledgement
signal from slave
acknowledgement
signal from receiver
clock line held low while
interrupts are serviced
byte complete,
interrupt within slave
1
2789 12 9
ACK ACK
3 - 8
Sr
or
P
P
Sr
S
or
Sr