Product data

MFRC631 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 4 February 2014
227433 23 of 120
NXP Semiconductors
MFRC631
High performance ISO/IEC 14443 A/B reader solution
In order to support a fast FIFO data transfer, the address pointer is not incremented
automatically in case the address is pointing to the FIFO.
The read/write bit shall be set to logic 1.
8.4.4.9 I
2
CL-bus interface
The MFRC631 provides an interface option according to of a logical handling of an I
2
C
interface. This logical interface fulfills the I
2
C specification, but the rise/fall timings will not
be according the I
2
C standard. Standard I/O pads are used for communication and the
communication speed is limited to 5 MBaud. The protocol itself is equivalent to the fast
mode protocol of I
2
C. The address is 01010xxb, where the last two bits of the address can
be defined by the application. The definition of this bits can be done by two options. With a
pin, where the higher bit is fixed to 0 or the configuration can be defined via EEPROM.
Refer to the EEPROM configuration in Section 8.7
.
Fig 19. Register read and write access
001aam305
Ack
0
(W)
Ack 0SA
I2C slave address
A7-A0
CLRC663 register
address A6-A0
Ack
DATA
[7..0]
SO
SO
[0..n]
Ack
0
(W)
Ack
Optional, if the previous access was on the same register address
Read Cycle
Write Cycle
0SA
I2C slave address
A7-A0
CLRC663 register
address A6-A0
1
(R)
AckSA
sent by master
sent by slave
I2C slave address
A7-A0
Ack
DATA
[7..0]
SO
[0..n]
0..n
Nack
DATA
[7..0]
Table 17. Timing parameter I
2
CL
Parameter Min Max Unit
f
SCL
05MHz
t
HD;STA
80 - ns
t
LOW
100 - ns
t
HIGH
100 - ns
t
SU;SDA
80 - ns
t
HD;DAT
050ns
t
SU;DAT
020ns
t
SU;STO
80 - ns
t
BUF
200 - ns