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Product data sheet

COMPANY PUBLIC

Rev. 3.3 — 4 February 2014

227433 56 of 120

NXP Semiconductors

MFRC631

High performance ISO/IEC 14443 A/B reader solution

9. MFRC631 registers

9.1 Register bit behavior

Depending on the functionality of a register, the access conditions to the register can vary.

In principle, bits with same behavior are grouped in common registers. The access

conditions are described in Table 39

Table 39. Behavior of register bits and their designation

Abbreviation Behavior Description

r/w read and write These bits can be written and read via the host interface. Since

they are used only for control purposes, the content is not

influenced by the state machines but can be read by internal state

machines.

dy dynamic These bits can be written and read via the host interface. They

can also be written automatically by internal state machines, for

example Command register changes its value automatically after

the execution of the command.

r read only These register bits indicates hold values which are determined by

internal states only.

w write only Reading these register bits always returns zero.

RFU - These bits are reserved for future use and must not be changed.

In case of a required write access, it is recommended to write a

logic 0.

Table 40. MFRC631 registers overview

Address Register name Function

00h Command Starts and stops command execution

01h HostCtrl Host control register

02h FIFOControl Control register of the FIFO

03h WaterLevel Level of the FIFO underflow and overflow warning

04h FIFOLength Length of the FIFO

05h FIFOData Data In/Out exchange register of FIFO buffer

06h IRQ0 Interrupt register 0

07h IRQ1 Interrupt register 1

08h IRQ0En Interrupt enable register 0

09h IRQ1En Interrupt enable register 1

0Ah Error Error bits showing the error status of the last command execution

0Bh Status Contains status of the communication

0Ch RxBitCtrl Control register for anticollision adjustments for bit oriented protocols