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MFRC631 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 4 February 2014
227433 88 of 120
NXP Semiconductors
MFRC631
High performance ISO/IEC 14443 A/B reader solution
9.10.5 TxWaitLo
9.11 FrameCon
Table 143. TxWaitLo register (address 32h)
Bit 7 6 5 4 3 2 1 0
Symbol TxWaitLo
Access
rights
r/w
Table 144. TxWaitLo bits
Bit Symbol Description
7 to 0 TxWaitLo Defines the minimum time between receive and send or between two
send data streams
Note: TxWait is a 11bit register (additional 3 bits are in the TxWaitCtrl
register)!
See also TxWaitEtu and TxWaitStart.
Table 145. FrameCon register (address 33h)
Bit 7 6 5 4 3 2 1 0
Symbol TxParityEn RxParityEn - - StopSym StartSym
Access
rights
r/w r/w RFU RFU r/w r/w
Table 146. FrameCon bits
Bit Symbol Description
7 TxParityEn If set, a parity bit is calculated and appended to each byte
transmitted.
6 RxParityEn If set, the parity calculation is enabled. The parity is not transferred to
the FIFO.
5 to 4 - RFU
3 to 2 StopSym Defines which symbol is sent as stop-symbol:
• 0h: No symbol is sent
• 1h: Symbol0 is sent
• 2h symbol1 is sent
• 3h Symbol2 is sent
1 to 0 StartSym Defines which symbol is sent as start-symbol:
• 0h: No Symbol is sent
• 1h: Symbol0 is sent
• 2h: Symbol1 is sent
• 3h: Symbol2 is sent