Product data

MFRC631 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 4 February 2014
227433 90 of 120
NXP Semiconductors
MFRC631
High performance ISO/IEC 14443 A/B reader solution
9.12.3 RxWait
Selects internal receiver settings.
9.12.4 RxThreshold
Selects minimum threshold level for the bit decoder.
4 EGT_Check If set to 1, the EGT is checked and if it is too long
a protocol error is set. (This is only valid for ISO/IEC14443 Type B).
3 EMD_Sup Enables the EMD suppression according ISO/IEC14443. If an error
occurs within the first three bytes, these three bytes are assumed to be
EMD, ignored and the FIFO is reset. A collision is treated as an error
as well If a valid SOF was received, the EMD_Sup is set and a frame
of less than 3 bytes had been received. RX_IRq is not set in this EMD
error cases. If RxForceCRCWrite is set, the FIFO should not be read
out before three bytes are written into.
2 to 0 Baudrate Defines the baud rate of the receiving signal.
4h: 106 kBd
5h: 212 kBd
6h: 424 kBd
7h: 847 kBd
all remaining values are RFU
Table 150. RxCtrl bits
Bit Symbol Description
Table 151. RxWait register (address 36h)
Bit 7 6 5 4 3 2 1 0
Symbol RxWaitEtu RxWait
Access
rights
r/w r/w
Table 152. RxWait bits
Bit Symbol Description
7 RXWaitEtu If set to 0, the RxWait time is RxWait  16/13.56 MHz.
If set to 1, the RxWait time is RxWait  (0.5/DBFreq).
6 to 0 RxWait Defines the time after sending, where every input is ignored.
Table 153. RxThreshold register (address 37h)
Bit 7 6 5 4 3 2 1 0
Symbol MinLevel MinLevelP
Access
rights
r/w r/w
Table 154. RxThreshold bits
Bit Symbol Description
7 to 4 MinLevel Defines the MinLevel of the reception.
Note: The MinLevel should be higher than the noise level in the system.
3 to 0 MinLevelP Defines the MinLevel of the phase shift detector unit.