Information

ManualsBrandsMIKROELEKTRONIKA ManualsMikroElektronika Development KitsPCB design board

This is information on a product in full production.

November 2013 DocID15818 Rev 11 1/178

STM32F205xx

STM32F207xx

ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, USB

OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

Datasheet - production data

Features

• Core: ARM 32-bit Cortex™-M3 CPU (120 MHz

max) with Adaptive real-time accelerator (ART

Accelerator™ allowing 0-wait state execution

performance from Flash memory, MPU,

150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)

• Memories

– Up to 1 Mbyte of Flash memory

– 512 bytes of OTP memory

– Up to 128 + 4 Kbytes of SRAM

– Flexible static memory controller that

supports Compact Flash, SRAM, PSRAM,

NOR and NAND memories

– LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– From 1.8 to 3.6 V application supply+I/Os

– POR, PDR, PVD and BOR

– 4 to 26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC, 20 × 32 bit backup

registers, and optional 4 KB backup SRAM

• 3 × 12-bit, 0.5 µs ADCs with up to 24 channels

and up to 6 MSPS in triple interleaved mode

• 2 × 12-bit D/A converters

• General-purpose DMA: 16-stream controller

with centralized FIFOs and burst support

• Up to 17 timers

– Up to twelve 16-bit and two 32-bit timers,

up to 120 MHz, each with up to 4

IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

• Debug mode: Serial wire debug (SWD), JTAG,

and Cortex-M3 Embedded Trace Macrocell™

• Up to 140 I/O ports with interrupt capability:

– Up to 136 fast I/Os up to 60 MHz

– Up to 138 5 V-tolerant I/Os

• Up to 15 communication interfaces

– Up to 3 × I

C interfaces (SMBus/PMBus)

– Up to 4 USARTs and 2 UARTs (7.5 Mbit/s,

ISO 7816 interface, LIN, IrDA, modem ctrl)

– Up to 3 SPIs (30 Mbit/s), 2 with muxed I

to achieve audio class accuracy via audio

PLL or external PLL

– 2 × CAN interfaces (2.0B Active)

– SDIO interface

• Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY

– USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated

DMA, on-chip full-speed PHY and ULPI

– 10/100 Ethernet MAC with dedicated DMA:

supports IEEE 1588v2 hardware, MII/RMII

• 8- to 14-bit parallel camera interface

(48 Mbyte/s max.)

–

• CRC calculation unit

• 96-bit unique ID

Table 1. Device summary

Reference Part number

STM32F205xx

STM32F205RB, STM32F205RC, STM32F205RE,

STM32F205RF, STM32F205RG, STM32F205VB,

STM32F205VC, STM32F205VE, STM32F205VF STM32F205VG,

STM32F205ZC, STM32F205ZE, STM32F205ZF, STM32F205ZG

STM32F207xx

STM32F207IC, STM32F207IE, STM32F207IF, STM32F207IG,

STM32F207ZC, STM32F207ZE, STM32F207ZF, STM32F207ZG,

STM32F207VC, STM32F207VE, STM32F207VF, STM32F207VG

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP144 (20 × 20 mm)

LQFP176 (24 × 24 mm)

UFBGA176

(10 × 10 mm)

WLCSP64+2

(0.400 mm pitch)

&"'!

www.st.com

Summary of content (178 pages)

PAGE 1
STM32F205xx STM32F207xx ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features &"'! • Core: ARM 32-bit Cortex™-M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator™ allowing 0-wait state execution performance from Flash memory, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.
PAGE 2
Contents STM32F20xxx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 3 2/178 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.
PAGE 3
STM32F20xxx Contents 3.20.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.20.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.
PAGE 4
Contents STM32F20xxx 6.1.7 7 8 4/178 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . .
PAGE 5
STM32F20xxx 9 Contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
List of tables STM32F20xxx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
PAGE 7
STM32F20xxx Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95.
PAGE 8
List of figures STM32F20xxx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37.
PAGE 9
STM32F20xxx Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82.
PAGE 10
Introduction 1 STM32F20xxx Introduction This datasheet provides the description of the STM32F205xx and STM32F207xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F205xx and STM32F207xx datasheet should be read in conjunction with the STM32F20x/STM32F21x reference manual. They will be referred to as STM32F20x devices throughout the document.
PAGE 11
STM32F20xxx 2 Description Description The STM32F20x family is based on the high-performance ARM® Cortex™-M3 32-bit RISC core operating at a frequency of up to 120 MHz. The family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.
PAGE 12
Peripherals Flash memory in Kbytes System (SRAM1+SRAM2) SRAM in Kbytes Backup FSMC memory controller STM32F205Rx 128 256 64 (48+16) 96 (80+16) 512 128 256 64 (48+16) 96 (80+16) 512 STM32F205Zx 768 1024 128 (112+16) 4 4 256 512 96 (80+16) 768 128 (112+16) 1024 4 Yes(1) No General-purpose 10 Advanced-control 2 Basic 2 IWDG Yes WWDG Yes DocID15818 Rev 11 Yes Random number generator Yes 2 3 (2)(2) SPI/(I S) 2 I C 3 USART UART 4 2 USB OTG FS Yes USB OTG HS Yes CAN
PAGE 13
Peripherals STM32F205Rx STM32F205Vx STM32F20xxx Table 2. STM32F205xx features and peripheral counts (continued) STM32F205Zx Ambient temperatures: –40 to +85 °C /–40 to +105 °C Operating temperatures Junction temperature: –40 to + 125 °C Package LQFP64 LQFP64 LQFP64 LQFP6 WLCSP64 WLCSP6 4 +2 4+2 LQFP100 LQFP144 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.
PAGE 14
Peripherals STM32F207Vx STM32F207Zx 2 SPI/(I S) Comm. interfaces 3 (2) I2C 3 USART UART 4 2 USB OTG FS Yes USB OTG HS Yes CAN 2 Camera interface GPIOs Yes 82 114 SDIO 12-bit ADC Number of channels 140 Yes 3 16 24 24 DocID15818 Rev 11 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 120 MHz 1.8 V to 3.6 V(3) Operating voltage Ambient temperatures: –40 to +85 °C/–40 to +105 °C Operating temperatures Package STM32F207Ix (2) Description 14/178 Table 3.
PAGE 15
STM32F20xxx 2.1 Description Full compatibility throughout the family The STM32F205xx and STM32F207xx constitute the STM32F20x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle. The STM32F205xx and STM32F207xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible.
PAGE 16
Description STM32F20xxx Figure 2. Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package 75 73 76 VSS 51 50 49 VSS VSS 99 (RFU) 100 19 26 20 1 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F2xx configuration 25 VSS VDD V SS Two 0 Ω resistors connected to: VDD VSS - VSS for the STM32F10xx - VDD, VSS, or NC for the STM32F2xx VSS for STM32F10xx VDD for STM32F2xx ai15961c Figure 3.
PAGE 17
STM32F20xxx Description Figure 4. STM32F20x block diagram DP, DM ULPI: CK, D(7:0), DIR, STP, NXT SCL/SDA, INTN, ID, VBUS, SOF Ethernet MAC DMA/ FIFO 10/100 PHY MII or RMII as AF MDIO as AF DMA/ FIFO USB OTG HS 8 Streams DMA2 FIFO Flash 1 Mbyte RNG SRAM 112 KB SRAM 16 KB AHB2 120 MHz VDD12 FIFO RC HS GPIO PORT A RC LS PB[15:0] GPIO PORT B Power managmt Voltage regulator 3.3 V to 1.
PAGE 18
Functional overview STM32F20xxx 3 Functional overview 3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
PAGE 19
STM32F20xxx 3.4 Functional overview Embedded Flash memory The STM32F20x devices embed a 128-bit wide Flash memory of 128 Kbytes, 256 Kbytes, 512 Kbytes, 768 Kbytes or 1 Mbytes available for storing programs and data. The devices also feature 512 bytes of OTP memory that can be used to store critical user data such as Ethernet MAC addresses or cryptographic keys. 3.
PAGE 20
Functional overview STM32F20xxx Figure 5. Multi-AHB matrix S1 S2 S3 S4 S5 S6 USB_HS_M MAC USB OTG Ethernet HS ETHERNET_M DMA_P2 GP DMA2 DMA_MEM2 DMA_MEM1 DMA_P1 S-bus GP DMA1 S7 M0 ICODE M1 DCODE ART ACCEL. S0 D-bus I-bus ARM Cortex-M3 Flash memory M2 SRAM 112 Kbyte M3 SRAM 16 Kbyte AHB1 periph AHB2 periph M4 M5 M6 APB1 APB2 FSMC Static MemCtl Bus matrix-S ai15963c 3.
PAGE 21
STM32F20xxx Functional overview The DMA can be used with the main peripherals: 3.9 • SPI and I2S • I2C • USART and UART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC. Flexible static memory controller (FSMC) The FSMC is embedded in all STM32F20x devices. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash.
PAGE 22
Functional overview 3.11 STM32F20xxx External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period.
PAGE 23
STM32F20xxx Functional overview in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). • VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 19: Power supply scheme for more details. 3.
PAGE 24
Functional overview STM32F20xxx There are three power modes configured by software when the regulator is ON: • MR is used in the nominal regulation mode • LPR is used in Stop modes The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption.
PAGE 25
STM32F20xxx Functional overview Figure 6. Regulator OFF/internal reset ON Power-down reset risen before VCAP_1/VCAP_2 stabilization External VCAP_1/2 power supply supervisor Application reset signal (optional) Ext. reset controller active when VCAP_1/2 < 1.08 V VDD (1.8 to 3.6 V) PA0 VDD NRST REGOFF 1.2 V VCAP_1 IRROFF VCAP_2 ai18476b The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.
PAGE 26
Functional overview STM32F20xxx Figure 7. Regulator OFF/internal reset OFF VDD 1.2 V External VDD/VCAP_1/2 power supply supervisor Ext. reset controller active when VDD<1.7V and VCAP_1/2 < 1.08 V PA0 VDD NRST REGOFF IRROFF 1.2 V VCAP_1 VCAP_2 ai18477b The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains (see Figure 8). • PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.
PAGE 27
STM32F20xxx Functional overview Figure 8. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization VDD PDR=1.8 V 1.2 V 1.08 V VCAP_1 /V CAP_2 time PA0 tied to NRST NRST time 1. This figure is valid both whatever the internal reset mode (ON or OFF). Figure 9. Startup in regulator OFF: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization VDD PDR=1.8 V 1.2 V 1.
PAGE 28
Functional overview 3.16.3 STM32F20xxx Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON/internal Regulator Regulator OFF/internal reset ON OFF/internal reset ON reset OFF LQFP64 LQFP100 LQFP144 LQFP176 WLCSP 64+2 UFBGA176 3.
PAGE 29
STM32F20xxx Functional overview The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.18: Low-power modes). Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or the VBAT pin. 3.
PAGE 30
Functional overview 3.20 STM32F20xxx Timers and watchdogs The STM32F20x devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 5 compares the features of the advanced-control, general-purpose and basic timers. Table 5.
PAGE 31
STM32F20xxx Functional overview If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The TIM1 and TIM8 counters can be frozen in debug mode. Many of the advanced-control timer features are shared with those of the standard TIMx timers which have the same architecture.
PAGE 32
Functional overview 3.20.4 STM32F20xxx Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.
PAGE 33
STM32F20xxx Functional overview Table 6. USART feature comparison USART Standard Modem SPI LIN irDA name features (RTS/CTS) master Max. baud rate Max. baud rate Smartcard in Mbit/s in Mbit/s (ISO 7816) (oversampling (oversampling by 16) by 8) APB mapping USART1 X X X X X X 1.87 7.5 APB2 (max. 60 MHz) USART2 X X X X X X 1.87 3.75 APB1 (max. 30 MHz) USART3 X X X X X X 1.87 3.75 APB1 (max. 30 MHz) UART4 X - X - X - 1.87 3.75 APB1 (max.
PAGE 34
Functional overview STM32F20xxx The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 3.
PAGE 35
STM32F20xxx Functional overview CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared with any other peripheral. 3.28 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume.
PAGE 36
Functional overview 3.30 STM32F20xxx Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
PAGE 37
STM32F20xxx 3.34 Functional overview ADCs (analog-to-digital converters) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller.
PAGE 38
Functional overview 3.37 STM32F20xxx Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.
PAGE 39
STM32F20xxx Pinouts and pin description VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 10.
PAGE 40
Pinouts and pin description STM32F20xxx 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD RFU PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 12.
PAGE 41
STM32F20xxx Pinouts and pin description RFU PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD Figure 13.
PAGE 42
Pinouts and pin description STM32F20xxx PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS PI3 PI2 V DD 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PI7 PI6 PI5 PI4 Figure 14.
PAGE 43
STM32F20xxx Pinouts and pin description Figure 15.
PAGE 44
Pinouts and pin description STM32F20xxx Table 8.
PAGE 45
STM32F20xxx Pinouts and pin description Table 8.
PAGE 46
Pinouts and pin description STM32F20xxx Table 8.
PAGE 47
STM32F20xxx Pinouts and pin description Table 8.
PAGE 48
Pinouts and pin description STM32F20xxx Table 8.
PAGE 49
STM32F20xxx Pinouts and pin description Table 8.
PAGE 50
Pinouts and pin description STM32F20xxx Table 8.
PAGE 51
STM32F20xxx Pinouts and pin description Table 8.
PAGE 52
Pinouts and pin description STM32F20xxx Table 8.
PAGE 53
STM32F20xxx Pinouts and pin description Table 8.
PAGE 54
Pinouts and pin description STM32F20xxx Table 8.
PAGE 55
STM32F20xxx Pinouts and pin description Table 8.
PAGE 56
Pinouts and pin description STM32F20xxx Table 9.
PAGE 57
STM32F20xxx Pinouts and pin description Table 9.
PAGE 58
AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT UART4_RX ETH_MII _RX_CLK ETH_RMII _REF_CLK EVENTOUT ETH_MDIO EVENTOUT Port SYS PA0-WKUP TIM1/2 TIM3/4/5 TIM8/9/10/11 TIM2_CH1_ETR TIM 5_CH1 TIM8_ETR PA1 TIM2_CH2 TIM5_CH2 PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 I2C1/I2C2/I2C3 TIM2_CH1_ETR PA6 TIM1_BKIN PA7 PA8 TIM1_CH1N USART2_RX TIM3_CH2 TIM8_CH1N SPI1_SCK TIM8_BKIN SPI1_MISO TIM8_CH1N S
PAGE 59
AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 Port SYS I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI TIM1/2 TIM3/4/5 TIM8/9/10/11 PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_D1 ETH _MII_RXD2 PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_D2 ETH _MII_RXD3 AF014 EVENTOUT EVENTOUT PB2 Port B EVENTOUT PB3 JTDO/ TRACESWO PB4 JTRST TIM2_CH2 TIM3_CH1 SPI1_SCK SPI3_SCK I2S3_S
PAGE 60
AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 PC1 PC2 OTG_HS_ULPI_ DIR OTG_HS_ULPI_ NXT SPI2_MISO PC3 SPI2_MOSI PC4 PC5 PC6 TIM3_CH1 TIM8_CH1 PC7 TIM3_CH2 TIM8_CH2 PC8 TIM3_CH3 TIM8_CH3 TIM3_CH4 TIM8_CH4 PC9 MCO2 I2S2_MCK USART6_TX I2S3_MCK I2C3_SDA I2S2_CKIN DocID15818 Rev 11 SPI3_SCK I2S3_SCK PC11 PC12 PC14OSC32_IN PC15OSC32_
PAGE 61
AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 PD0 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI CAN1_RX PD1 FSMC_D2 CAN1_TX PD2 TIM3_ETR AF014 EVENTOUT FSMC_D3 UART5_RX SDIO_CMD AF15 EVENTOUT DCMI_D11 EVENTOUT PD3 USART2_CTS FSMC_CLK EVENTOUT PD4 USART2_RTS FSMC_NOE EVENTOUT PD5 USART2_TX FSMC_NWE EVENTOUT PD6 USART2_RX F
PAGE 62
AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PF0 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI I2C2_SDA AF014 FSMC_A0 AF15 EVENTOUT PF1 I2C2_SCL FSMC_A1 EVENTOUT PF2 I2C2_SMBA FSMC_A2 EVENTOUT PF3 FSMC_A3 EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11_CH1 FSMC_NREG EVENTOU
PAGE 63
AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1/2/3 UART4/5/ USART6 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 AF9 AF10 CAN1/CAN2/ OTG_FS/ OTG_HS TIM12/13/14 AF11 AF12 AF13 ETH FSMC/SDIO/ OTG_HS DCMI AF014 PH0 OSC_IN PH1 OSC_OUT Port H AF15 EVENTOUT EVENTOUT PH2 ETH _MII_CRS EVENTOUT PH3 ETH _MII_COL EVENTOUT PH4 I2C2_SCL PH5 I2C2_SDA PH6 I2C2_SMBA PH7 I2C3_SCL PH8 I2C3_SDA PH9 I2C3_SMBA OTG_HS_ULPI_N XT EVENTOUT EVENTOUT TIM12_CH1
PAGE 64
Memory mapping 5 STM32F20xxx Memory mapping The memory map is shown in Figure 16.
PAGE 65
STM32F20xxx Memory mapping Figure 16.
PAGE 66
Electrical characteristics STM32F20xxx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 67
STM32F20xxx 6.1.6 Electrical characteristics Power supply scheme Figure 19. Power supply scheme VBAT OUT GP I/Os IN 2 × 2.2 μF IO Logic Kernel logic (CPU, digital & RAM) VCAP_1 VCAP_2 VDD 1/2/...14/15 15 × 100 nF + 1 × 4.7 μF Level shifter 1.8-3.6 V VDD Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Power switch Voltage regulator VSS 1/2/...14/15 Flash memory REGOFF IRROFF VDD VDDA VREF 100 nF + 1 μF 100 nF + 1 μF VREF+ VREF- ADC Analog RCs, PLL, ...
PAGE 68
Electrical characteristics 6.1.7 STM32F20xxx Current consumption measurement Figure 20. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied.
PAGE 69
STM32F20xxx Electrical characteristics Table 12. Current characteristics Symbol Ratings Max.
PAGE 70
Electrical characteristics STM32F20xxx Table 14. General operating conditions(1) (continued) Symbol VBAT VIN VCAP1 VCAP2 PD Parameter Min Max 1.65 3.6 FT and TTa I/O TBD TBD BOOT0 TBD TBD 1.1 1.
PAGE 71
STM32F20xxx Electrical characteristics Table 15. Limitations depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency (fFlashmax) VDD =1.8 to 2.1 V(2) Conversion time up to 1 Msps 16 MHz with no Flash memory wait state VDD = 2.1 to 2.4 V Conversion time up to 1 Msps 18 MHz with no Flash memory wait state Conversion time up to 2 Msps 24 MHz with no Flash memory wait state VDD = 2.4 to 2.7 V VDD = 2.7 to 3.
PAGE 72
Electrical characteristics STM32F20xxx Figure 21. Number of wait states versus fCPU and VDD range Wait states vs Fcpu and VDD range 8 7 Number of Wait states 6 5 1.8 to 2.1V 2.1 to 2.4V 4 2.4 to 2.7V 2.7 to 3.6V 3 2 1 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 0 Fcpu (MHz) ai18748b 1. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range and IRROFF is set to VDD. 6.3.
PAGE 73
STM32F20xxx Electrical characteristics 1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. 6.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA. Table 17. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD 6.3.
PAGE 74
Electrical characteristics 6.3.5 STM32F20xxx Embedded reset and power control block characteristics The parameters given in Table 19 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 19. Embedded reset and power control block characteristics Symbol VPVD 74/178 Parameter Conditions Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.04 2.
PAGE 75
STM32F20xxx Electrical characteristics Table 19. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit VBOR2 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 V Rising edge 2.53 2.59 2.63 V VBOR3 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 V Rising edge 2.85 2.92 2.97 - 100 - mV 0.5 1.5 3.0 ms - 160 200 mA - - 5.
PAGE 76
Electrical characteristics STM32F20xxx Typical and maximum current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog inputs by firmware. • All peripherals are disabled except if it is explicitly mentioned. • The Flash memory access time is adjusted to fHCLK frequency (0 wait state from 0 to 30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz and 3 wait states from 90 to 120 MHz).
PAGE 77
STM32F20xxx Electrical characteristics Table 21.
PAGE 78
Electrical characteristics STM32F20xxx Figure 23. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals ON 60 50 105°C IDD(RUN) (mA) 40 85°C 70°C 30 55°C 30°C 0°C 20 -45°C 10 0 0 20 40 60 80 100 120 CPU frequnecy (MHz) MS19014V1 Figure 24.
PAGE 79
STM32F20xxx Electrical characteristics Figure 25. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON 80.0 70.0 IDD(RUN) (mA) 60.0 105 50.0 85 40.0 30°C -45°C 30.0 20.0 10.0 0.0 0 20 40 60 CPU frequnecy (MHz) 80 100 120 MS19016V1 Figure 26. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals OFF 45.0 35.0 30.0 105 25.
PAGE 80
Electrical characteristics STM32F20xxx Table 22. Typical and maximum current consumption in Sleep mode Max(1) Typ Symbol Parameter Conditions External clock(2), all peripherals enabled(3) IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK TA = 25 °C TA = 85 °C TA = 105 °C 120 MHz 38 51 61 90 MHz 30 43 53 60 MHz 20 33 43 30 MHz 11 25 35 25 MHz 8 21 31 16 MHz 6 19 29 8 MHz 3.6 17.0 27.0 4 MHz 2.4 15.4 25.3 2 MHz 1.9 14.9 24.
PAGE 81
STM32F20xxx Electrical characteristics Figure 27. Typical current consumption vs temperature in Sleep mode, peripherals ON 50 45 IDD(SLEEP) (mA) 40 105°C 35 85°C 30 70°C 55°C 25 30°C 20 0°C -45°C 15 10 5 0 0 20 40 60 CPU Frequency (MHz) 80 100 120 MS19018V1 Figure 28.
PAGE 82
Electrical characteristics STM32F20xxx Table 23. Typical and maximum current consumptions in Stop mode(1) Typ Symbol Parameter Conditions Supply current in Stop mode with main regulator in Run mode IDD_STOP Max TA = 25 °C TA = 25 °C TA = 85 °C Unit TA = 105 °C Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.55 1.2 11.00 20.
PAGE 83
STM32F20xxx Electrical characteristics Table 24. Typical and maximum current consumptions in Standby mode Symbol Parameter Conditions Backup SRAM ON, low-speed oscillator and RTC ON Supply current Backup SRAM OFF, lowspeed oscillator and RTC ON IDD_STBY in Standby mode Backup SRAM ON, RTC OFF Backup SRAM OFF, RTC OFF Typ Max(1) TA = 25 °C TA = 85 °C TA = 105 °C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V 3.0 3.4 4.0 15.1 25.8 2.4 2.7 3.3 12.4 20.5 2.4 2.6 3.0 12.5 24.8 1.7 1.9 2.2 9.
PAGE 84
Electrical characteristics STM32F20xxx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 26. The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog inputs by firmware.
PAGE 85
STM32F20xxx Electrical characteristics Table 26. Peripheral current consumption (continued) Peripheral(1) APB1 Typical consumption at 25 °C TIM2 0.61 TIM3 0.49 TIM4 0.54 TIM5 0.62 TIM6 0.20 TIM7 0.20 TIM12 0.36 TIM13 0.28 TIM14 0.25 USART2 0.25 USART3 0.25 UART4 0.25 UART5 0.26 I2C1 0.25 I2C2 0.25 I2C3 0.25 SPI2 0.20/0.10 SPI3 0.18/0.09 CAN1 0.31 CAN2 Unit mA 0.30 (2) 1.11 DAC channel 1(3) 1.11 PWR 0.15 WWDG 0.
PAGE 86
Electrical characteristics STM32F20xxx Table 26. Peripheral current consumption (continued) Peripheral(1) APB2 Typical consumption at 25 °C SDIO 0.69 TIM1 1.06 TIM8 1.03 TIM9 0.58 TIM10 0.37 TIM11 0.39 (4) ADC1 2.13 ADC2(4) 2.04 (4) ADC3 2.12 SPI1 1.20 USART1 0.38 USART6 0.37 Unit mA 1. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 2. EN1 bit is set in DAC_CR register. 3. EN2 bit is set in DAC_CR register. 4.
PAGE 87
STM32F20xxx 6.3.8 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 28 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 28.
PAGE 88
Electrical characteristics STM32F20xxx Figure 30. High-speed external clock source AC timing diagram VHSEH 90 % 10 % VHSEL tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext OSC_IN IL STM32F ai17528 Figure 31.
PAGE 89
STM32F20xxx Electrical characteristics Table 30. HSE 4-26 MHz oscillator characteristics(1) (2) Symbol fOSC_IN RF IDD gm tSU(HSE(3) Parameter Conditions Min Typ Max Unit Oscillator frequency 4 - 26 MHz Feedback resistor - 200 - kΩ VDD=3.3 V, ESR= 30 Ω, CL=5 pF@25 MHz - 449 - VDD=3.3 V, ESR= 30 Ω, CL=10 pF@25 MHz - 532 - Startup 5 - - mA/V VDD is stabilized - 2 - ms HSE current consumption Oscillator transconductance Startup time µA 1.
PAGE 90
Electrical characteristics STM32F20xxx Table 31. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - 18.4 - MΩ IDD LSE current consumption - - 1 µA gm Oscillator Transconductance 2.8 - - µA/V - 2 - s tSU(LSE)(2) startup time VDD is stabilized 1. Guaranteed by design, not tested in production. 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.
PAGE 91
STM32F20xxx Electrical characteristics 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. Figure 34. ACCHSI versus temperature max avg 6 min 4 Normalized deviation (%) 2 0 -2 -4 -6 -8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 Temperature (°C) MS19012V2 Low-speed internal (LSI) RC oscillator Table 33.
PAGE 92
Electrical characteristics STM32F20xxx Figure 35. ACCLSI versus temperature 50 max 40 avg min Normalized deviati on (%) 30 20 10 0 -10 -20 -30 -40 -45 -35 -25 -15 -5 5 15 25 35 45 Temperat ure (°C) 55 65 75 85 95 105 MS19013V1 6.3.10 PLL characteristics The parameters given in Table 34 and Table 35 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. Table 34.
PAGE 93
STM32F20xxx Electrical characteristics Table 34.
PAGE 94
Electrical characteristics STM32F20xxx Table 35. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max RMS - 90 - peak to peak - ±280 - ps Average frequency of 12.288 MHz N=432, R=5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.
PAGE 95
STM32F20xxx 6.3.11 Electrical characteristics PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 42: EMI characteristics). It is available only on the main PLL. Table 36. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % - 215 - MODEPER * INCSTEP - −1 1.
PAGE 96
Electrical characteristics STM32F20xxx Figure 36 and Figure 37 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 36. PLL output clock waveforms in center spread mode Frequency (PLL_OUT) md F0 md tmode 2xtmode Time ai17291 Figure 37. PLL output clock waveforms in down spread mode Frequency (PLL_OUT) F0 2xmd tmode 2xtmode Time ai17292 6.3.
PAGE 97
STM32F20xxx Electrical characteristics Table 37. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode VDD = 1.8 V - 5 - Write / Erase 16-bit mode VDD = 2.1 V - 8 - Write / Erase 32-bit mode VDD = 3.3 V - 12 - Unit mA Table 38.
PAGE 98
Electrical characteristics STM32F20xxx Table 39. Flash memory programming with VPP Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Min(1) Typ Max(1) Unit - 16 100(2) µs - 230 - - 490 - - 875 - - 6.9 - s 2.7 - 3.6 V TA = 0 to +40 °C VDD = 3.3 V VPP = 8.
PAGE 99
STM32F20xxx Electrical characteristics The test results are given in Table 41. They are based on the EMS levels and classes defined in application note AN1709. Table 41. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.
PAGE 100
Electrical characteristics STM32F20xxx Electromagnetic Interference (EMI)g The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC® code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 42. EMI characteristics Symbol Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 25/120 MHz VDD = 3.
PAGE 101
STM32F20xxx Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 44. Electrical sensitivities Symbol LU 6.3.
PAGE 102
Electrical characteristics 6.3.16 STM32F20xxx I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the conditions summarized in Table 14: General operating conditions. All I/Os are CMOS and TTL compliant except for BOOT0 and BOOT1. Table 46. I/O static characteristics(1) Symbol VIL Parameter Low level input voltage Conditions Min Typ Max TTa, FT and NRST I/Os - - 0.35VDD–0.
PAGE 103
STM32F20xxx Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
PAGE 104
Electrical characteristics STM32F20xxx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 38 and Table 48, respectively. Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 48.
PAGE 105
STM32F20xxx Electrical characteristics Table 48. I/O AC characteristics(1) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(2) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD > 2.70 V - - 100(3) CL = 30 pF, VDD > 1.8 V - - 50(3) CL = 10 pF, VDD > 2.70 V - - 180(3) CL = 10 pF, VDD > 1.8 V - - 100(3) CL = 30 pF, VDD > 2.
PAGE 106
Electrical characteristics 6.3.17 STM32F20xxx NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 49). Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 49.
PAGE 107
STM32F20xxx 6.3.18 Electrical characteristics TIM timer characteristics The parameters given in Table 50 and Table 51 are guaranteed by design. Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. Characteristics of TIMx connected to the APB1 domain(1) Symbol tres(TIM) Parameter Min Max Unit 1 - tTIMxCLK 16.7 - ns 1 - tTIMxCLK 33.
PAGE 108
Electrical characteristics STM32F20xxx Table 51.
PAGE 109
STM32F20xxx Electrical characteristics Table 52. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time - 3450(3) - 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.
PAGE 110
Electrical characteristics STM32F20xxx Figure 40. I2C bus AC waveforms and measurement circuit V DD_I2C V DD_I2C RP RP STM32Fxx RS SDA I²C bus RS SCL S T AR T REPEATED S T AR T S T AR T tsu(STA) SD A tf(SDA) tr(SDA) th(STA) tsu(SDA) th(SDA) tw(SCLL) tw(STO:STA) S TOP SCL tr(SCL) tw(SCLH) tf(SCL) tsu(STO) ai14979c 1. RS= series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 53. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.
PAGE 111
STM32F20xxx Electrical characteristics I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 54 for SPI or in Table 55 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14. Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 54.
PAGE 112
Electrical characteristics STM32F20xxx Figure 41. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 42.
PAGE 113
STM32F20xxx Electrical characteristics Figure 43.
PAGE 114
Electrical characteristics STM32F20xxx Table 55. I2S characteristics Symbol Min Max 1.23 1.24 Slave 0 64FS(1) I2S clock rise and fall time capacitive load CL = 50 pF - (2) tv(WS) (3) WS valid time Master 0.
PAGE 115
STM32F20xxx Electrical characteristics Figure 44. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 45.
PAGE 116
Electrical characteristics STM32F20xxx USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Speed). This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 56. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design, not tested in production. Table 57. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage Min.
PAGE 117
STM32F20xxx Electrical characteristics Figure 46. USB OTG FS timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines VCRS VS S tr tf ai14137 Table 58. USB OTG FS electrical characteristics(1) Driver characteristics Symbol tr tf trfm VCRS Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Rise/ fall time matching Output signal crossover voltage 1.
PAGE 118
Electrical characteristics STM32F20xxx Figure 47. ULPI timing diagram Clock Control In (ULPI_DIR, ULPI_NXT) tSC tHC tSD tHD data In (8-bit) tDC tDC Control out (ULPI_STP) tDD data out (8-bit) ai17361c Table 61. ULPI timing Value(1) Symbol Parameter Unit Min. Max. Control in (ULPI_DIR) setup time - 2.0 Control in (ULPI_NXT) setup time - 1.5 tHC Control in (ULPI_DIR, ULPI_NXT) hold time 0 - tSD Data in setup time - 2.
PAGE 119
STM32F20xxx Electrical characteristics Figure 48. Ethernet SMI timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) ai15666d Table 63. Dynamics characteristics: Ethernet MAC signals for SMI Symbol Rating Min Typ Max Unit tMDC MDC cycle time (2.
PAGE 120
Electrical characteristics STM32F20xxx Table 65 gives the list of Ethernet MAC signals for MII and Figure 49 shows the corresponding timing diagram. Figure 50. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668 Table 65. Dynamics characteristics: Ethernet MAC signals for MII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 7.
PAGE 121
STM32F20xxx 6.3.20 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 66 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14. Table 66. ADC characteristics Symbol Parameter VDDA Power supply VREF+ Positive reference voltage fADC fTRIG(3) VAIN RAIN(3) ADC clock frequency External trigger frequency Conditions Typ Max Unit - 3.6 V 1.
PAGE 122
Electrical characteristics STM32F20xxx Table 66. ADC characteristics (continued) Symbol fS(3) Parameter Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps Sampling rate (fADC = 30 MHz) IVREF+(3) ADC VREF DC current consumption in conversion mode - 300 500 µA IVDDA(3) ADC VDDA DC current consumption in conversion mode - 1.6 1.8 mA 1.
PAGE 123
STM32F20xxx Electrical characteristics being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.16 does not affect the ADC accuracy. Figure 51.
PAGE 124
Electrical characteristics STM32F20xxx pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced.
PAGE 125
STM32F20xxx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 53 or Figure 54, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 53. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F V REF+ (See note 1) 1 µF // 10 nF V DDA 1 µF // 10 nF V SSA/V REF(See note 1) ai17535 1.
PAGE 126
Electrical characteristics 6.3.21 STM32F20xxx DAC electrical characteristics Table 68. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 1.8(1) - 3.6 V VREF+ Reference supply voltage 1.8(1) - 3.6 V VSSA Ground 0 - 0 V RLOAD(2) Resistive load with buffer ON 5 - - kΩ RO(2) Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.
PAGE 127
STM32F20xxx Electrical characteristics Table 68. DAC characteristics (continued) Symbol INL(4) Offset(4) Gain error(4) Parameter Min Typ Max Unit - - ±1 LSB Given for the DAC in 10-bit configuration. - - ±4 LSB Given for the DAC in 12-bit configuration. - - ±10 mV - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - ±0.
PAGE 128
Electrical characteristics STM32F20xxx Figure 55. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD DAC_OUTx 12-bit digital to analog converter C LOAD ai17157V2 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.22 Temperature sensor characteristics Table 69.
PAGE 129
STM32F20xxx 6.3.24 Electrical characteristics Embedded reference voltage The parameters given in Table 71 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 71. Embedded internal reference voltage Symbol VREFINT Parameter Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.18 1.21 1.
PAGE 130
Electrical characteristics STM32F20xxx Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FSMC_NOE FSMC_NWE tv(A_NE) FSMC_A[25:0] t h(A_NOE) Address tv(BL_NE) t h(BL_NOE) FSMC_NBL[1:0] t h(Data_NE) t su(Data_NOE) th(Data_NOE) t su(Data_NE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14991c 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 72.
PAGE 131
STM32F20xxx Electrical characteristics 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] th(A_NWE) Address tv(BL_NE) FSMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 73.
PAGE 132
Electrical characteristics STM32F20xxx 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 58. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] t h(A_NOE) Address tv(BL_NE) th(BL_NOE) FSMC_NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NOE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14892b Table 74.
PAGE 133
STM32F20xxx Electrical characteristics Table 74. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued) Symbol Parameter Min Max Unit THCLK+ 3 - ns Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time th(Data_NE) 1. CL = 30 pF. 2. Based on characterization, not tested in production.
PAGE 134
Electrical characteristics STM32F20xxx Figure 59. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B Table 75.
PAGE 135
STM32F20xxx Electrical characteristics Synchronous waveforms and timings Figure 60 through Figure 63 represent synchronous waveforms and Table 77 through Table 79 provide the corresponding timings.
PAGE 136
Electrical characteristics STM32F20xxx Table 76. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max Unit 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1.5 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 2.
PAGE 137
STM32F20xxx Electrical characteristics Figure 61.
PAGE 138
Electrical characteristics STM32F20xxx 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 62.
PAGE 139
STM32F20xxx Electrical characteristics 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 63.
PAGE 140
Electrical characteristics STM32F20xxx Table 79. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued) Symbol td(CLKL-Data) Parameter Min Max Unit - 2 ns 2 - ns FSMC_D[15:0] valid data after FSMC_CLK low td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1. CL = 30 pF. 2. Based on characterization, not tested in production.
PAGE 141
STM32F20xxx Electrical characteristics Figure 64. PC Card/CompactFlash controller waveforms for common memory read access FSMC_NCE4_2(1) FSMC_NCE4_1 th(NCEx-AI) tv(NCEx-A) FSMC_A[10:0] th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) td(NREG-NCEx) td(NIORD-NCEx) FSMC_NREG FSMC_NIOWR FSMC_NIORD FSMC_NWE td(NCE4_1-NOE) FSMC_NOE tw(NOE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14895b 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 65.
PAGE 142
Electrical characteristics STM32F20xxx Figure 66. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded).
PAGE 143
STM32F20xxx Electrical characteristics Figure 67. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 68.
PAGE 144
Electrical characteristics STM32F20xxx Figure 69. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NCE4_1 FSMC_NCE4_2 tv(NCEx-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD td(NCE4_1-NIOWR) tw(NIOWR) FSMC_NIOWR ATTxHIZ =1 tv(NIOWR-D) th(NIOWR-D) FSMC_D[15:0] ai14900c Table 80.
PAGE 145
STM32F20xxx Electrical characteristics Table 81. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8THCLK - 0.5 - ns - 5THCLK- 1 ns 8THCLK- 3 - ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK+ 1.
PAGE 146
Electrical characteristics STM32F20xxx Figure 70. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE td(ALE-NOE) th(NOE-ALE) FSMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14901c Figure 71.
PAGE 147
STM32F20xxx Electrical characteristics Figure 72. NAND controller waveforms for common memory read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) th(NOE-ALE) FSMC_NWE tw(NOE) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14912c Figure 73. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FSMC_NWE FSMC_NOE td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14913c Table 82.
PAGE 148
Electrical characteristics STM32F20xxx Table 83.
PAGE 149
STM32F20xxx Electrical characteristics Figure 75. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Table 85. SD / MMC characteristics Symbol Parameter Conditions Min Max Unit fPP Clock frequency in data transfer mode CL ≤ 30 pF 0 48 MHz - SDIO_CK/fPCLK2 frequency ratio - - 8/3 - tW(CKL) Clock low time, fPP = 16 MHz CL ≤ 30 pF 32 tW(CKH) Clock high time, fPP = 16 MHz CL ≤ 30 pF 31 tr Clock rise time CL ≤ 30 pF 3.
PAGE 150
Package characteristics STM32F20xxx 7 Package characteristics 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
PAGE 151
STM32F20xxx Package characteristics Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE A1 ccc C K L D L1 D1 D3 33 48 32 49 64 PIN 1 IDENTIFICATION E E1 E3 b 17 16 1 e 5W_ME_V2 1. Drawing is not to scale. Table 87. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.
PAGE 152
Package characteristics STM32F20xxx Table 87. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.000 10.200 0.3937 0.3937 0.4016 E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1.
PAGE 153
STM32F20xxx Package characteristics Figure 78. WLCSP64+2 - 0.400 mm pitch wafer level chip size package outline A1 ball location D e1 e e Detail A e1 E G A2 F A Side view Wafer back side Bump side Detail A rotated by 90 °C A1 eee b Seating plane A0FX_ME 1. Drawing is not to scale. Table 88. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0.520 0.570 0.600 0.0205 0.0224 0.0236 A1 0.170 0.190 0.
PAGE 154
Package characteristics STM32F20xxx Table 88. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data (continued) millimeters inches Symbol 154/178 Min Typ Max Min Typ Max G - 0.386 - - 0.0152 - eee - - 0.050 - - 0.
PAGE 155
STM32F20xxx Package characteristics Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE L D A1 K ccc C L1 D1 D3 51 75 50 100 26 PIN 1 1 IDENTIFICATION E E3 E1 b 76 25 e 1L_ME_V4 1. Drawing is not to scale. Table 89. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data Symbol A inches(1) millimeters Min Typ Max Min Typ Max - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.
PAGE 156
Package characteristics STM32F20xxx Table 89. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80.
PAGE 157
STM32F20xxx Package characteristics Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline c A1 A2 A SEATING PLANE C 0.25 mm ccc C A1 GAUGE PLANE D K L D1 L1 D3 108 73 109 E E3 E1 b 72 37 144 1 PIN 1 IDENTIFICATION 36 e 1A_ME_V3 1. Drawing is not to scale. Table 90. LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.
PAGE 158
Package characteristics STM32F20xxx Table 90. LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1.
PAGE 159
STM32F20xxx Package characteristics Figure 83. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline A2 A1 c A C Seating plane 0.25 mm gauge plane k A1 L HD PIN 1 IDENTIFICATION L1 D ZE E HE e ZD b 1T_ME_V2 1. Drawing is not to scale. Table 91. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.
PAGE 160
Package characteristics STM32F20xxx Table 91. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Max HE 25.900 26.100 1.0197 1.0276 L(2) 0.450 0.750 0.0177 0.0295 L1 1.000 0.0394 ZD 1.250 0.0492 ZE 1.250 0.0492 k ccc 0° 7° 0° 0.080 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
PAGE 161
STM32F20xxx Package characteristics Figure 84. LQFP176 recommended footprint 1.2 1 176 133 132 0.5 21.8 26.7 0.3 44 45 89 88 1.2 21.8 26.7 1T_FP_V1 1. Dimensions are expressed in millimeters.
PAGE 162
Package characteristics STM32F20xxx Figure 85. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline C Seating plane A2 ddd A1 b C A A A1 ball A1 ball identifier index area e E F A F D e B R 15 BOTTOM VIEW 1 TOP VIEW Øb (176 + 25 balls) Ø eee M C A B Ø fff M C A0E7_ME_V5 1. Drawing is not to scale. Table 92. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.
PAGE 163
STM32F20xxx 7.2 Package characteristics Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
PAGE 164
Part numbering 8 STM32F20xxx Part numbering Table 94.
PAGE 165
STM32F20xxx 9 Revision history Revision history Table 95. Document revision history Date Revision 05-Jun-2009 1 Initial release. 2 Document status promoted from Target specification to Preliminary data. In Table 8: STM32F20x pin and ball definitions: – Note 4 updated – VDD_SA and VDD_3 pins inverted (Figure 12: STM32F20x LQFP100 pinout, Figure 13: STM32F20x LQFP144 pinout and Figure 14: STM32F20x LQFP176 pinout corrected accordingly). Section 7.
PAGE 166
Revision history STM32F20xxx Table 95. Document revision history (continued) Date 13-Jul-2010 166/178 Revision Changes Added USB OTG_FS features in Section 3.28: Universal serial bus onthe-go full-speed (OTG_FS). Updated VCAP_1 and VCAP_2 capacitor value to 2.2 µF in Figure 19: Power supply scheme. Removed DAC, modified ADC limitations, and updated I/O compensation for 1.8 to 2.1 V range in Table 15: Limitations depending on the operating power supply range.
PAGE 167
STM32F20xxx Revision history Table 95. Document revision history (continued) Date 25-Nov-2010 Revision Changes 5 Update I/Os in Section : Features. Added WLCSP64+2 package. Added note 1 related to LQFP176 on cover page. Added trademark for ART accelerator. Updated Section 3.2: Adaptive real-time memory accelerator (ART Accelerator™). Updated Figure 5: Multi-AHB matrix. Added case of BOR inactivation using IRROFF on WLCSP devices in Section 3.15: Power supply supervisor. Reworked Section 3.
PAGE 168
Revision history STM32F20xxx Table 95. Document revision history (continued) Date 22-Apr-2011 168/178 Revision Changes 6 Changed datasheet status to “Full Datasheet”. Introduced concept of SRAM1 and SRAM2. LQFP176 package now in production and offered only for 256 Kbyte and 1 Mbyte devices. Availability of WLCSP64+2 package limited to 512 Kbyte and 1 Mbyte devices.
PAGE 169
STM32F20xxx Revision history Table 95. Document revision history (continued) Date 22-Apr-2011 Revision Changes Updated Typical and maximum current consumption conditions, as well as Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM.
PAGE 170
Revision history STM32F20xxx Table 95. Document revision history (continued) Date 22-Apr-2011 170/178 Revision Changes Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and tf(SCK) to tf(SCL) in Table 52: I2C characteristics and in Figure 40: I2C bus AC waveforms and measurement circuit. Added Table 57: USB OTG FS DC electrical characteristics and updated Table 58: USB OTG FS electrical characteristics.
PAGE 171
STM32F20xxx Revision history Table 95. Document revision history (continued) Date 14-Jun-2011 20-Dec-2011 Revision Changes 7 Added SDIO in Table 2: STM32F205xx features and peripheral counts. Updated VIN for 5V tolerant pins in Table 11: Voltage characteristics. Updated jitter parameters description in Table 34: Main PLL characteristics. Remove jitter values for system clock in Table 35: PLLI2S (audio PLL) characteristics. Updated Table 42: EMI characteristics.
PAGE 172
Revision history STM32F20xxx Table 95. Document revision history (continued) Date 172/178 Revision Changes 20-Dec-2011 Added maximum power consumption at TA=25 °C in Table 23: Typical and maximum current consumptions in Stop mode. Updated md minimum value in Table 36: SSCG parameters constraint. Added examples in Section 6.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Updated Table 54: SPI characteristics and Table 55: I2S characteristics.
PAGE 173
STM32F20xxx Revision history Table 95. Document revision history (continued) Date 24-Apr-2012 Revision Changes Removed support of I2C for OTG PHY in Section 3.29: Universal serial bus on-the-go high-speed (OTG_HS). Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 8: STM32F20x pin and ball definitions and Table 10: Alternate function mapping. Renamed PH10 alternate function into TIM5_CH1 in Table 10: Alternate function mapping. Added Table 9: FSMC pin definition.
PAGE 174
Revision history STM32F20xxx Table 95. Document revision history (continued) Date 29-Oct-2012 174/178 Revision Changes 10 Changed minimum supply voltage from 1.65 to 1.8 V. Updated number of AHB buses in Section 2: Description and Section 3.12: Clocks and startup. Removed Figure 4. Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. Updated Note 2 below Figure 4: STM32F20x block diagram. Changed System memory to System memory + OTP in Figure 16: Memory map.
PAGE 175
STM32F20xxx Revision history Table 95. Document revision history (continued) Date 29-Oct-2012 Revision Changes Replaced td(CLKL-NOEL) by td(CLKH-NOEL) in Table 76: Synchronous multiplexed NOR/PSRAM read timings, Table 78: Synchronous nonmultiplexed NOR/PSRAM read timings, Figure 60: Synchronous multiplexed NOR/PSRAM read timings and Figure 62: Synchronous non-multiplexed NOR/PSRAM read timings. 10 (continued) Added Figure 84: LQFP176 recommended footprint.
PAGE 176
Revision history STM32F20xxx Table 95. Document revision history (continued) Date 04-Nov-2013 176/178 Revision Changes 11 In the whole document, updated notes related to WLCSP64+2 usage with IRROFF set to VDD. Updated Section 3.14: Power supply schemes, Section 3.15: Power supply supervisor, Section 3.16.1: Regulator ON and Section 3.16.2: Regulator OFF. Added Section 3.16.3: Regulator ON/OFF and internal reset ON/OFF availability. Added note related to WLCSP64+2 package.
PAGE 177
STM32F20xxx Revision history Table 95. Document revision history (continued) Date 04-Nov-2013 Revision Changes Removed Appendix A Application block diagrams. Updated Figure 76: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline and Table 87: LQFP64 – 10 x 10 mm 64 pin lowprofile quad flat package mechanical data.
PAGE 178
STM32F20xxx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.