Operating instructions

the feedback amplifier (consisting
of_ U55A and pins 1
and 20 of U65) increases as
the Peak Detector signal
amplitude
is reduced, thereby producing
a constant
trigger signal
level at U65 pins 16 and 17 .
The range of the front-panel
LEVEL control is zero
at
minimum triggering signal
amplitude . The LEVEL range
increases as triggering signal
amplitude increases,
until
it reaches maximum level range
at the Automatic Gain
Control threshold . Refer to
the Specification section in
this
manual for triggering sensitivity
and triggering
LEVEL range
parameters .
Automatic Gain
Control
The Automatic Gain
Control stage limits the trigger
signal amplitude to approximately
450 millivolts peak-to-
peak (at U65 pins 16 and 17)
regardless of the trigger
input signal amplitude . The
level of the peak-detected
signal from R58-59 is sensed by
a feedback amplifier
stage (U55A and pins 1 and 20 of
U65) . When the peak
detected signal is above the
Automatic Gain Control
threshold (resulting from
approximately 2 divisions
of
internal
trigger signal or approximately
50 millivolts of
external trigger
signal), the Automatic
Gain Control stage
limits the
output trigger signal amplitude
at U65 pins 16
and 17 .
Current into U65 pin 3 (established
by R51)
determines
the current reference that
sets the Automatic
Gain Control threshold
.
SLOPE SELECTOR AND
TRIGGER GENERATOR
Integrated
circuit U85 converts the differential
trigger
signal from the Trigger
Source Selector and
Amplifier
block to a differential gate
waveform for use by the
Gate
Generator stage .
SLOPE switch S60 is
connected to U85 pin 1
to
determine whether the trigger
occurs on the positive-
or
negative-going slope . When the
SLOPE switch is set to +,
a positive going signal on pin
13 produces a positive-
going
gate on pin 3 and a negative-going
gate on pin 4 .
When the SLOPE
switch is set to -, a
negative-going
signal
on
pin
13 produces a positive-going
gate on pin 3
and a negative-going
gate on pin 4 .
Slope Balance
adjustment R80
provides optimum input balance
for both
+ and - SLOPE
operation .
The Delay Mode In
signal (to U85 pin 16) functions
only
when the unit is operating
as a delayed sweep in
the B
Horizontal compartment of a
mainframe with 2 horizontal
compartments . When the
unit is operating in
the
"independent"
or "triggerable after
delay" modes (as
determined
by the delaying sweep time-base
unit in the
A horizontal
compartment), there
is no effect on the
Trigger Generator
circuits . However, when
the unit is
operating in the
"B starts after delay" mode, a high
level
at U85 pin 16 supplies
a trigger gate pulse
to U85 pins 3
and 4 in the absence
of a trigger disable pulse
at the
emitter of 0242 .
At the end of each sweep, the Logic
circuits (diagram 3)
supply a trigger
disable pulse through
Q242 to U85 pins
GATE GENERATOR
Theory of
Operation-71387
6 and 10 . A high level
disables the Trigger
Generator to
allow
enough time for the sweep
generator to
stabilize
before another trigger pulse
starts the next sweep .
The
Gate Generator stage provides
an auto enable gate
and Z-axis
gate (unblanking) to the
Sweep Generator
circuit
(diagram 4) . Figure 3-3 shows
the timing of the
Gate Generator
Functions .
When an
adequate trigger signal is applied
to U85 pins
13 and 14, it produces
high and low levels,
respectively,
at its pin
3
and
pin 4 outputs .
The high level from
U85 pin 3 is coupled through
emitter
follower Q88 and J200-2
into the Logic circuit
(diagram
3)
to indicate that a triggering signal
has been received .
The
Logic circuit (diagram 3) sets the
Auto Sense line at
J200-3 high, turning
off Q98 . Simultaneously,
the low
level at U85 pin 4
gates comparator
096-092 . The
collector of Q92
rises high to provide a Sweep
Start Gate
at J200-5 and the
collector of Q96 falls low
to provide a
Z-Axis Gate (unblanking)
at J200-4 .
In the absence
of a trigger output at
U85 pins 13 and 14,
pin
3 is set low and pin 4 is set high .
The low level from
U85 pin
3 is coupled through J200-2
to the Logic circuit
(diagram 3) to indicate
the lack of a triggering
signal . The
Logic circuit
provides a low-level Auto
Sense pulse
through J200-3
to the base of Q98 . The low
level gates
the comparator
(098 and Q96) . The collector
of Q98 of
Q96 falls low to provide
a Z-Axis Gate (unblanking)
at
J200-4 .
LOGIC
The Logic
circuit controls the sweep
modes and
associated functions
of the time-base unit (e .g .,
sweep
display, hold off,
auto sweep, single sweep, etc
.) . The
Logic circuit also generates
control signals for the
mainframe . Figure 3-4 is a block
diagram for the Logic
circuit
.
SWEEP MODES
Integrated circuit U220
controls the Norm, Auto,
and
Single Sweep Modes and
also generates control signals
.
P-P Auto operation is described in
the Trigger Generator
circuit description (diagram 2) .
Normal
Mode
The NormMode is provided
when U220 pin 12
is low . In
the Norm Mode, only an
appropriate trigger signal
can
initiate a sweep gate
to the Sweep Generator
(diagram
4) . Sweep Control integrated
circuit U220 controls
sweep
lockout and hold-off functions
.