Operating instructions

Theory of Operation  71387
DELAY COMPARISON VOLTAGE-'TO-RAMP
CONVERTER
The Delay Comparison Voltage-to-Ramp Converter,
U547, develops a
negative-going ramp
at CR552'sanode .
The current that flows through R537 and R539 (delay
comparison current, determined by the ACQUIRE-STOP
DELAY front-panel control) is integrated by U547 and
C547
to form a negative-going ramp with a slope
proportional to the delay comparison voltage .
Consequently, the more positive the delay comparison
voltage, the more negative the
ramp will run .
After a
period
of
time (determined by U590) diode CR547
turns
on
and adds reference current to the delay
comparison current . This reference current polarity is
opposite to the delay comparison current and at least 10
times greater . Therefore, the output of U547 becomes a
positive-going ramp . When the positive-going ramp
reaches about 7 volts, the Comparator stage switches
and the Ramp control turns off CR547 . The output of
U547 becomes a negative-going ramp, completing the
cycle .
The DVM Zero adjustment, R550, provides
a
do offset
current to set the quiescent operating level of the Delay
Comparison . Voltage to Ramp
Converter . Scaling
adjustment R538 allows
for calibration of the delay
comparison current .
COMPARATOR
The Comparator circuitry drives the comparator input of
U590 .
When the output of U547 rises to about 7 volts, it
forward biases CR552,which turns on 0552- . Inverters
U556B and U566D provide rapid latchup of the positive-
going signal from Q552 and U556C applies it to the
comparator input of U590 .
REFERENCE
CURRENT SOURCE
The Reference Current
Source determines the amount of
current to be used
for cornparison with the delay
comparison current . The front-panel SWP CAL control
determines
the absolute value of reference current . The
Swp Cal reference input, on pin 1 of J100, changes the
reference current value to compensate for different front-
panel SWP CAL settings .
REFERENCE CURRENT INVERTER
The Reference
Current Inverter acts as a current "mirror"
to produce an equivalent current in opposite polarity .
Thus, current flowing through R546 is
reversed
as
it
flows through
R547 . Reversing current flow allows U547
to sum the
reference current with the delay comparison
current .
The ramp control output of U590 controls the reference
current switching . A high on
pin
16
of
U590
causes a
low at U556A's output,
which reverse biases CR555 .
This causes
U535 to forward-bias CR547 and allows
reference
current
to
flow from the summing node at pin
2 of U547
. A low at pin 16 of U590 forward-biases
CR555, turning off CR547 and routing the reference
current away from U547's summing node .
3- 1 2
COUNTER AND ENCODER
The Counter and Encoder circuit consists essentially of a
four-decade counter with a multiplexer and associated
circuitry .
An integration cycle of 100,000 counts beginswith the
ramp control (pin 16) going high and starting a short
internal delay . During the delay, the counters are cleared
and set to their initial state . After the delay, the counters
are enabled and increment until a transition occurs on
the comparison input (pin 8) signaling that the counters
contain the desired
digital
output which is a direct
function of the delay comparison voltage . At this point
clock pulses to the counters are disabled, the ramp
control is set low, and the contents of the counter are
latched . The counter then resumes operation .
Each decade counter counts synchronously with data
read out by sequentially strobing U590's select lines,
pins 3, 4, 5, and 6 . The output appears at pin
18 as
a
current which varies from
0 ma
to 1 ma in
100/ja steps .
Integrated circuit
U590
uses
S800 cam-switch control
voltages at pins
10 and 11 for
accurate
1, 2,
and 5
sweep-speed scaling . The presence of voltages at pins
10
or
1 1
allows
U590 to
determine if
it
should
be dividing by
two or by five . An absence of voltage at both pins
is
interpreted as "divide by one ."
CLOCK
GENERATOR
The Clock board generates a Clock signal for digitizing
mainframes such as the 7854 . Diagram 6 depicts the
circuitry on the Clock board
. There are 10 groups
of
circuitry on diagram 6, as follows :
1 . Control Logic .
The Control Logic generates the signals
that
operate the X1-X10 Multiplexer .
2 . Oscillator . The Oscillator produces a 20.48-MHz signal
that serves as the reference for the Clock Generator .
3 . First Divider . The First Divider produces outputs
of
10 .24, 5 .12, 2 . .048, and
1 .024 MHz and512kHz for the
X1-X10 multiplexer .
4 . X1-X10
Multiplexer . The X1-X10 Multiplexer selects
its output
based on the position of the MAG X1-X10
control
.
5 . Decade Divider . TheDecade Divider furnishes five
inputs to the Internal Clock Multiplexer . It produces the
five inputs by dividing the output of the X1-X10
Multiplexer by 10, 100, 1,000, and 100,000 .
6 .
Internal Clock Multiplexer . The Internal Clock
Multiplexer selects one of the outputs of the Decade
Divider as the
input to the Output Clock Multiplexer .