Operating instructions

7 .
Output Clock Multiplexer . The Output
Clock
Multiplexer selects the
output of the Internal Clock
Multiplexer, the Internal
Clock divided by 1000, or the
signal from the EXT CLOCK IN
connector to be the
"acquire clock" signal .
8 . Intensify Circuit . The Intensify
Circuit causes the
mainframe
to
intensify
the display between sweep start
and the point
selected by the ACQUIRE-STOP DELAY
control .
9 . External Clock Buffer . The External
Clock Buffer is a
high-impedance source follower which
ensures that the
71387 will not load the external
signal source .
10 .
AQS
CLOCK/AQR Switches . The AQS CLOCK/AQR
switches
control the Output Clock Multiplexer and the
Intensify circuit .
CONTROL LOGIC
The Control Logic (CL) circuit produces a
select
input
for
Output Multiplexer U660,and
enable inputs for X1
multiplexer U638 and X10 multiplexer
U637 . TheCL
circuit consists of U621A, U622A, B, C and D,
and
U623B,C and D .
When
section 18 or 35 of TIME/DIV switch
S800 is
closed, U621A will
be active and apply a high-logic level
to multiplexer
U660's pin 15 input . One or both of
sections 18 and35 is
closed from 5s to 50 /us/div, and
frorn 2
us
to 50 us/div . Because
of
this,
U621 A applies a
high-logic level to U660's pin
15 input at all TIME/DIV
settings except 20, 10, and 5
us,
and
20 and 10 ns .
'Operates from
5s to 10us/div, in X1 MAG .
2 0perates from
5s to 50us/div, in X10 MAG .
TABLE 3-1
Truth Table, TIME/DIV
Setting vs . Strobes for U637 and
U638
Gates U622A, B, C andD andU623B,
C andD are wired
so that
they provide low-logic levels to the
enable inputs
of :
a) X1 multiplexer U638 from 5s to 10 ,us/div
when
the MAG button
is set to X1, and b) X10 multiplexer
U637 from 5s to 50 us/div
when the MAG button is
set
to X10 . Table 3-1 is a truth table that
gives details of this
operation .
When the TIME/DIV switch is set
between 5 s and 10
us/Div, section 1 of S800 turns Q607 off . The
high level
output of Q607 permits the Delay Time
Comparator
(diagram
5) to operate . At settings between
5
us
and 10
ns/Div, Q607
is turned on, producing a low output
level
that disables
the Delay Time Comparator .
OSCILLATOR
The Oscillator generates a
20.48-MHz signal that serves
as the reference for the clock-generating
circuitry . Gates
U621 B andC and crystal Y626
form the Oscillator .
the Oscillator has two enable
inputs, which are
connected to the TIME/DIV switch, via
U622D, and to the
AOS CLOCK/AQR switch . Bothenable inputs
must be at
high-logic levels
to allow oscillation .
When the TIME/DIV
switch (S800) is set from
5 s to 10
/us/Div, section 11
is closed . The ground from
S800
section 11 causes
U622D to assert a high-logic level
to
U621 B's pin 5 input, which
enables the oscillator .
When the AQS CLOCK/AQR control
is set to INTERNAL
or INT
-
1000, R646 applies a high-logic level
to U621 C's
pin
10
input
. When the AQS CLOCK/AQR control
is set
Theory of Operation--- .7B87
Strobe for
U638
(U623B)
3-
1
3
MAG
5s to 50us
20 & 10Ns L
L
2jis
to 50ns L
20ns, 10ns L
5s to 50us
20/is, 10us
------- --------
H
5us H
2us to 50ns
H__
20ns, 10 ns H