Operating instructions
Theory
of
Operation---71387
like
the
Delay
Gate
of
a
delaying
time
base
.
By
setting
the
voltage
on the
Delay
Mode
line,
the three
AQS
CLOCK/AQR
pushbuttons,
INTERNAL,
INT
-
1000,
and
EXT/AQR,
cause
operating
modes
that
correspond
to
Independent,
B
Starts
After
Dly,
and
B
Triggerable
After
Dly,
respectively
(if
the
71387
is in
the
A
Horiz
plug-in
compartment)
.
The
Delay
Mode
line
controls
Q576
and
Q574
.
The
voltage
on
the Delay
Mode
line,
that
goes
to
pin B2,
is
0
V,
+5
.0
V,
and
+3
.6
V,
respectively,
when
the
INTERNAL,
INT
divided
by
1000,
or
EXT/AQR
button
is
pressed
.
7887
IN
A
HORIZ
PLUG-IN
COMPARTMENT
INTERNAL
BUTTON
PRESSED
A
low-logic
level
on
the
Delay
Mode
line
turns
on
Q576
(refer
to
diagram
5),
which
saturates
and
removes
the
collector
voltage
from
Q574
.
Without
collector
voltage,
0574
produces
no Delay
Gate
signal
.
Transistor
0678
controls
intensification
in
response
to
the
voltage
on
pin
A16
.
When
the 71387
is
in
the
A
Horiz
plug-in
compartment
pin
Al
6
will
be
at
+5
V
.
Intensification
then
cannot
occur
because
Q678
and
Q680
keep
Q681
turned
off
.
When
0681
is
off,
its
output
turns
off
Q687,
which
prevents
Q574
(diagram
5)
from
producing
the
Delay
Gate
.
Either
of
these events
will
prevent
a Delay
Gate
from
occurring
in
the
A
Horiz
compartment
with the
INTERNAL
button
pressed
;
one
would
be
sufficient
.
When
there
is
no
Delay
Gate
there
is
no
Aux
Z-Axis
signal
and
no
intensification
.
71387
IN
B
HORI
PLUG-IN
COMPARTMENT
INTERNAL
BUTTONPRESSED
A
low-logic
level
on
the
Delay
Mode
line
turns
off
Q576
(refer
to
diagram
5)
.
The
pin
A16
input
is
at
ground,
which
turns
off
Q680
via
Q678,
and
Q680
turns on
Q681
.
The
output
of
Q681
turns
on
Q687,which
has
two
effects
:
a
.
It
supplies
collector
voltage
for
Q574
via
R687,
and
b
.
If
the
Display
B
line
is
at
a
high-logic
level,
it
turns
on
Q691
via
R688
.
Transistor
Q691
conducts
current
from the
mainframe,
which
intensifies
the
display
.
When
the
TIME/DIV
control
is
set
to
10 Ns
or
faster,
+5
V
turns
on
CR677
via
R611
.
This
clamps
the
emitter
of
Q691
to
about
+3
.4
V,
which
turns
it
off
and
prevents
intensification
.
External
Clock
Buffer
The
External
Clock
Buffer
receives
the
signal
from
the
EXT
CLOCK
IN
connector,
buffers
it,
and
applies
it
to
the
Output
Clock
Multiplexer
.
The
External
Clock
Buffer
consists
of
Q642,
Q643
and
U623A
.
3-16
Source-follower
0642
and
current
source
Q643
present
a
high
impedance
to
the
input
signal
.
Inverter
U623A
applies
an
inverted,
TTL
version
of
the
Ext
Clock
In
signal
to
multiplexer
U655
.
Diodes
CR641
and
CR642
limit
the
voltage
at
Q642's
gate
to
the
-0
.6
V
to
+5
.6
V
range
.
AQS
CLOCK/AQR
Switches
the
AQS
CLOCK/AQR
Switches
control
the
Output
Clock
Multiplexer,
activate
the Delay
Mode
line
for
the
Intensify
circuit,
and
insert
different
resistances
in
the
Ch
1,
Analog
Data
Row
line
.
Two
sections
of
S645,
operated
by the
INTERNAL
and
EXT/AQR
buttons,
control
the
select
lines
for
multiplexer
U655
.
When
a
button
is
released,
that
switch's
output
line
will
be
at
a
high-logic
level
;
and
when
a
button
is
pressed
that
switch's
output
line will
be
at
a
low-logic
level
.
When
the
EXT/AQR
line
is
pressed,
the
low-logic
level
on
the
output
line
stops
the
Oscillator
.
Two
sections
of
S645
select
the
voltages
on the Delay
Mode
line,
which
are
:
Acquire
Clock
Mode
Acquire
Clock
Mode
External
INTERNAL,-,-
I
NT
_
1000
+5
V
EXT/AQR
TABLE
3-4
Current
in
CH1
Readout
Line
vs
Acquire
Clock
Mode,
During
TS10
Internal
-
1000
0
.2
mA
When
the
71387
is
in
the
B
Horiz plug-in
compartment,
the
current
in
the
TS10
line
indicates the
Acquire
Clock
Mode,
as
follows
:
_Current
CH
1
Row
m
~
CH
2
Column
When
the
71387
is
installed
in
the
B
Horiz plug-in
compartment,
the
information
during
TS10
is
used by a
digitizing
mainframe
(such
as
the
7854)
to
sense
the
7B87's
clock
mode
.