Specifications

4.6 Index Setting
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4
PROGRAM CONFIGURATION
(d) The following figure shows the examples of index setting and their actual processing
devices.
(With the setting of Z0=20 and Z1=5)
Figure. 4.6-1 Ladder examples and actual processing devices
(3) 32-bit index setting (for Universal model QCPU (excluding Q00UJCPU), LCPU, and
FXCPU)
For Universal model QCPU (excluding Q00UJCPU) and LCPU, either of the following two
methods can be selected to specify index registers used for a 32-bit index setting.
• Specify a range of index registers used for a 32-bit index setting.
• Specify a 32-bit index setting using 'ZZ'.
For FXCPU, combine index registers V (from V0) and Z (from Z0) for a 32-bit index setting.
32-bit index settings using 'ZZ' can be used for the following CPU modules only.
• QnU(D)(H)CPU with a serial number whose first five digits are '10042' or higher
(excluding Q00UJCPU)
•QnUDE(H)CPU
•QnUDVCPU
•LCPU
Ladder example Actual processing device
X0
MOV
EN ENO
dsZ0
K20
MOV
EN ENO
dsZ1K-5
X1
MOV
EN ENO
ds
K1M38Z1
K2X50Z0
K2X(50 + 14) = K2X64
X1
MOV
EN ENO
ds K1M33K2X64
Description
Converts K20 to a hexadecimal number.
K2X50Z0
K1M38Z1
K1M(38 - 5) = K1M33
X0
MOV
EN ENO
ds
Z0K20
MOV
EN ENO
ds
Z1K-5
X1
MOV
EN ENO
ds
K3Y12FZ1D0Z0
X1
MOV
EN ENO
ds K3Y12A
D20
Description
Hexadecimal numbe
r
D0Z0
K3Y12FZ1
D (0 + 20) = D20
K3Y(12F - 5) = K3Y12A