User`s manual

165
CHAPTER 4 FUNCTION
4
4.20 Response Delay Time
4.20 Response Delay Time
This section described the response delay time of I/O signals and buffer memory.
(1) Scan time of the sequence program
The CPU module processes I/O signals by refreshing them all at once before the operation start of a sequence
program. Therefore, the signals are delayed.
Use direct access input (DX) or direct access output (DY) to minimize the delay.
For details on direct access input (DX) or direct access output (DY), refer to the following:
QnUCPU User's Manual (Function Explanation, Program Fundamentals)
Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals)
(2) Control cycle (1ms) of the QD65PD2
The QD65PD2 reads out the output signals and buffer memories updated by the sequence program and
completes processing with up to 2ms (1 control cycle × 2) delay.
The update timing of the input signals and buffer memories vary within the range of the control cycle.
Maximum delay time [ms] = [Time of (1)] + [Maximum time of (2)]
= Sequence program scan time + 2 [ms]