User`s manual

25
CHAPTER 3 SPECIFICATIONS
3
3.1 Performance Specifications
CHAPTER 3 SPECIFICATIONS
This chapter describes the performance specifications of the QD65PD2, I/O signals to the CPU module, and buffer
memories.
For the general specifications of the QD65PD2, refer to the following:
QCPU User's Manual (Hardware Design, Maintenance and Inspection)
The I/O numbers (X/Y), buffer memory addresses, and external input terminals described in this chapter are for CH1.
To check the I/O numbers (X/Y) for CH2, refer to the following:
Page 32, Section 3.3.1
To check the buffer memory addresses for CH2, refer to the following:
Page 42, Section 3.4.1
3.1 Performance Specifications
The following table describes the performance specifications of the QD65PD2.
Item
Specifications
Differential input DC input
Counting speed switch setting
*1
1 multiple
10kpps/100kpps/200kpps/500kpps/
1Mpps/2Mpps
10kpps/100kpps/200kpps 2 multiples
10kpps/100kpps/200kpps/500kpps/
1Mpps/2Mpps/4Mpps
4 multiples
10kpps/100kpps/200kpps/500kpps/
1Mpps/2Mpps/4Mpps/8Mpps
Number of occupied I/O points 32 points (I/O assignment: Intelligent, 32 points)
Number of channels 2 channels
Count input signal
Phase
1-phase input (1 multiple/2 multiples), 2-phase input (1 multiple/2 multiples/
4 multiples), CW/CCW
Signal level (A, B)
EIA Standards RS-422-A, differential
line driver level
(AM26LS31 (manufactured by Texas
Instruments Japan Limited.) or
equivalent)
5/12/24VDC, 7 to 10mA