Technical data

vcom
ModelSim EE/SE Command Reference ModelSim Commands CR-169
vcom
The vcom command is used to invoke VCOM, the Model Technology VHDL
compiler. Use VCOM to compile VHDL source code into a specified working
library (or to the work library by default).
This command may be invoked from within ModelSim or from the operating
system command prompt. This command may also be invoked during simulation.
Syntax
vcom
[-help] [-93] [-87] [-check_synthesiss] [-debugVA] [-explicit]
[-f <filename>] [-just eapbc] [-skip eapbc] [-line <number>]
[-no1164] [-noaccel <package_name>] [-nocheck]
[-nodebug[=ports]] [-nolock] [-nologo] [-novital] [-novitalcheck]
[-nowarn <number>] [-O0 | -O1 | -O4 | -O5] [-quiet] [-refresh] [-s]
[-source] [-version] [-work <library_name>] <filename>
Arguments
-help
Displays the command’s options and arguments. Optional.
-93
Specifies that the simulator is to support VHDL 1076-1993. Optional. If used,
must be the first argument. See additional discussion in the examples.
-87
Disables support for VHDL 1076-1993. This is the VCOM default. Optional. If
used, must be the first argument. See additional discussion in the examples. Note
that the default can be changed with the modelsim.ini file, see "Preference
variables located in INI and MPF files"
(B-394).
-check_synthesis
Turns on limited synthesis rule compliance checking. Optional. Checks to see that
signals read by a process are in the sensitivity list.
-debugVA
Prints a confirmation if a VITAL cell was optimized, or an explanation of why it
was not, during VITAL level-1 acceleration. Optional.
-explicit
Used to ignore an error in packages supplied by some other EDA vendors; directs
the compiler to resolve ambiguous function overloading in favor of the explicit
function definition. See additional discussion in the examples.