Technical data

vlog
ModelSim EE/SE Command Reference ModelSim Commands CR-203
-93
Specifies that the VHDL interface to Verilog modules shall use VHDL 1076-93
extended identifiers to preserve case in Verilog identifiers that contain uppercase
letters.
<filename>
Specifies the name of the Verilog source code file to compile. One filename is
required. Multiple filenames can be entered separated by spaces.
Examples
vlog example.vlg
The example compiles the Verilog source code contained in the file example.vlg.
vlog -nodebug example.v
Hides the internal data of example.v. Models compiled with -nodebug cannot use any of
the ModelSim debugging features; any subsequent user will not be able to see into the
model.
vlog -nodebug=ports level3.v levle2.v
vcom -nodebug
top.v
The first line compiles and hides the internal data, plus the ports, of the lower-level design
units, level3.v and level2.v. The second line compiles the top-level unit, top.v, without
hiding the ports. It is important to compile the top level without =ports because top-level
ports must be visible for simulation.
vlog -nodebug=ports+pli level3.v level2.v
vlog -nodebug=pli top.v
The first command hides the internal data, and ports of the design units, level3.v and
level2.v. In addition it prevents the use of pli functions to interrogate the compiled modules
for information (either =ports+pli or =pli+ports works fine for this command). The second
line compiles the top-level unit without hiding the ports but restricts the use of pli functions
as well.
Note that the =pli switch may be used at any level of the design but =ports should
only be used on lower levels since you can’t simulate without visible top-level
ports.
See "Source code security and -nodebug"
(E-443) for more details.