Technical data

HDL item pathnames
CR-246 Command Syntax and Conventions ModelSim EE/SE Command Reference
Absolute path names
Absolute path names begin with the path separator character. The first name in the
path should be the name of a top-level entity or module, but if you leave it off then
the first top-level entity or module will be assumed. VHDL designs only have one
top-level, so it doesn’t matter if it is included in the pathname. For example, if you
are referring to the signal CLK in the top-level entity named top, then both of the
following pathnames are correct:
/top/clk
/clk
Note: Since Verilog designs may contain multiple top-level modules, a path name may be ambiguous if
you leave off the top-level module name.
Relative pathnames
Relative pathnames do not start with the path separator, and are relative to the
current environment. The current environment defaults to the first top-level entity
or module and may be changed by the environment command or by clicking on
hierarchy levels in the structure window. Each new level in the pathname is first
searched downwards relative to the current environment, but if not found is then
searched for upwards (same search rules used in Verilog hierarchical names).
Indexing signals, memories and nets
VHDL array signals, and Verilog memories and vector nets can be sliced or
indexed. Indexes must be numeric, since the simulator does not know the actual
index types. Slice ranges may be represented in either VHDL or partial Verilog
syntax, irrespective of the setting of the PathSeparator
(B-400). The syntax is
partial Verilog because the range must be contained within parentheses and not in
Verilog square brackets. For example,
mysignal(31:0)
specifies a slice of an array item in partial Verilog syntax.
Name case sensitivity
Name case sensitivity is different for VHDL and Verilog. VHDL names are not
case sensitive except for extended identifiers in VHDL 1076-1993. In contrast, all
Verilog names are case sensitive.