Technical data

ModelSim EE/SE Tutorial Index - 111
Index
A
Assertion errors 33
B
Batch-mode simulation 41
Breakpoints
27
continuing simulation after
28
C
Code Coverage 93
coverage_summary window
94
reload
96
report
95
vsim -coverage command
94
Command history
11
Compile
compile order
76
compile order of Verilog modules
62
mixed HDL design
75
projects
17
Verilog
59
coverage_summary window
94
Cursors
29
find signal transitions
29
measure time intervals
29
probe for values
29
D
Debugging a VHDL design 31
Design
browse libraries
75
create new library
74
Design library
create new
60
creating
21
do command
12
DO files
executing a DO file in batch-mode
41
using a DO file at startup
43
using the transcript as a DO file
documentation
9
drag and drop
11
E
Edit
projects
17
Email
Model Technology’s email address
9
Errors
breaking on assertion
34
finding in VHDL designs
33
viewing in Source window
35
examine command
69
examples
Tcl example solutions
49
F
Find dialog box 99
Finding
a cursor in the Wave window
104
Finding names, and searching for values in windows
99
force command
25
H
Hierarchical Profile 84
update icon
89
Hierarchy
of a mixed VHDL/Verilog design
78