Technical data

Debugging a VHDL design

3-34 ModelSim EE/SE Tutorial

12 First, change the simulation assertion options. Make this Main menu selection:

Options > Simulation.

Select the

Assertions page.

Change the selection

for Break on

Assertion to Error

and click OK. This

will cause the

simulator to stop at

the HDL statement

after the assertion is

displayed.

14 To restart the simulation select the Restart button on the Main toolbar.

(Main MENU: File > Restart) (PROMPT: restart)

Make sure all items in the Restart dialog box are selected, then click Restart.