Technical data

Debugging a VHDL design
3-36 ModelSim EE/SE Tutorial
17 Expand the variable named test_patterns by clicking the [+]. (You may need to resize
the window for a better view.)
18 Also expand the sixth record in the array test_patterns(6), by clicking the [+]. The
Variables window should be similar to the one below.
The assertion shows that the Signal sum does not equal the sum field in the
Variables window. Note that the sum of the inputs a, b, and cin should be equal
to the output sum. But there is an error in the test vectors. To correct this error,
you need to restart the simulation and modify the initial value of the test vectors.
19 In the Main window, type:
restart -f
The -f option causes VSIM to restart without popping up the confirmation dialog.
20 Add variables to the Variables window by selecting the test /testbench process in the
Process window.