Technical data

Mixed VHDL/Verilog simulation
ModelSim EE/SE Tutorial 8-75
4 Now you can map the new library to the work library. From the Main menu select
Design > Browse Libraries. In the Library Browser select the work library, then Edit.
(PROMPT: vmap work mixed)
This opens the Edit Library
dialog box; where you can
set the library mapping
between work and mixed.
Type mixed into the Path:
field, then click OK. Now
you’re ready to compile the
design.
5 Compile the HDL files by selecting the Compile button on the toolbar:
(PROMPT:vlog cache.v memory.v proc.v)
(PROMPT: vcom util.vhd set.vhd top.vhd)
This opens the Compile HDL Source Files dialog box.