Technical data

Mixed VHDL/Verilog simulation
8-76 ModelSim EE/SE Tutorial
A group of Verilog files
can be compiled in any
order. Note, however, in
a mixed VHDL/Verilog
design the Verilog files
must be compiled before
the VHDL files.
Compile the source, by
double-clicking each of
these Verilog files in the
file list (this invokes the
Verilog compiler, vlog):
• cache.v
• memory.v
• proc.v
6 Depending on the design, the compile order of VHDL files can be very specific. In the
case of this lesson, the file top.vhd must be compiled last.
Stay in the Compile HDL Source Files dialog box and compile the VHDL files in
this order (this invokes the VHDL compiler, vcom):
• util.vhd
• set.vhd
• top.vhd
Compiling is now complete, click Done to dismiss the dialog box.
7 Now it’s time to simulate. Start the simulator by selecting the Load Design button
from the Main toolbar:
(PROMPT: vsim top)
This returns the Load Design dialog box.