User`s manual

Signals window
ModelSim Xilinx User’s Manual ModelSim XE Graphic Interface 7-145
HDL items you can view
One entry is created for each of the
following VHDL and Verilog HDL
items within the design:
VHDL items
signals
Verilog items
nets, register variables, and named
events
Virtual items
(indicated by an orange diamond icon)
virtual signals, see "Virtual signals"
(6-
101)
for more information
The names of any VHDL composite types (arrays and record types) are shown in
a hierarchical fashion.
Hierarchy also applies to Verilog nets and vector memories. (Verilog vector
registers do not have hierarchy because they are not internally represented as
arrays.)
Hierarchy is indicated in typical ModelSim fashion with plus (expandable), minus
(expanded), and blank (single level) boxes.
See "Tree window hierarchical view"
(7-111) for more information.