User`s manual

Verilog SDF
8-228 Standard Delay Format (SDF) Timing Annotation ModelSim Xilinx User’s Manual
Timing check edge specifiers may also use explicit edge transitions instead of
posedge and negedge. However, the SDF file is limited to posedge and negedge.
The explicit edge specifiers are 01, 0x, 10, 1x, x0, and x1. The set of [01, 0x, x1]
is equivalent to posedge, while the set of [10, 1x, x0] is equivalent to negedge. A
match occurs if any of the explicit edges in the specify port match any of the
explicit edges implied by the SDF port. For example,
Optional conditions
Timing check ports and path delays may have optional conditions. The annotator
uses the following rules to match conditions:
• A match occurs if the SDF does not have a condition.
• A match occurs for a timing check if the SDF port condition is semantically
equivalent to the specify port condition.
• A match occurs for a path delay if the SDF condition is lexically identical to the
specify condition.
Timing check conditions are limited to very simple conditions, therefore the
annotator can match the expressions based on semantics. For example,
The conditions are semantically equivalent and a match occurs. In contrast, path
delay conditions may be complicated and semantically equivalent conditions may
not match. For example,
The annotator does not match the second condition above because the order of r1
and r2 are reversed.
SDF Verilog
(SETUP data (posedge clock) (5)) $setup(data, edge[01, 0x] clk, 0);
SDF Verilog
(SETUP data (COND (reset!=1) (posedge clock)) (5)) $setup(data, posedge clk &&& (reset==0), 0);
SDF Verilog
(COND (r1 || r2) (IOPATH clk q (5))) if (r1 || r2) (clk => q) = 5; // matches
(COND (r1 || r2) (IOPATH clk q (5))) if (r2 || r1) (clk => q) = 5; // does not match