User`s manual

ModelSim Xilinx User’s Manual Index - 305
U
Unbound Component 198
UnbufferedOutput .ini file variable
265
UpCase .ini file variable
262
Use 1076-1993 language standard
197
Use clause
specifying a library
32
Use explicit declarations only
197
user-defined buses
100
UserTimeUnit .ini file variable
265
V
Values of HDL items 156
Variable settings report
267
Variables window (see also, Windows)
161
Variables, HDL
changing value of with the GUI
161
Variables, referencing
loading order at ModelSim startup
282
simulator state variables
iteration number
283
name of entity or module as a variable
283
resolution
283
simulation time
283
Variables, setting
environment variables
255
VCD files
VCD system tasks
234
Verilog
cell libraries
71
compiler directives
78
compiling design units
55
compiling with XL ’uselib compiler directive
63
creating a design library
55
library usage
58
SDF annotation
222
sdf_annotate system task
222
simulating
65
delay modes
71
event order issues
66
XL compatible options
68
simulation hazard detection
67
simulation resolution limit
65
source code viewing
152
system tasks
72
XL compatible compiler options
60
XL compatible routines
92
XL compatible system tasks
75
verilog .ini file variable
259
Verilog PLI
80–94
specifying the PLI file to load
83
support for VHDL objects
88
verilog standards
18
Veriuser .ini file variable
265
VHDL
delay file opening
270
Dependency checking
45
file opening delay
270
library clause
32
object support in PLI
88
simulating
45
source code viewing
152
timing check disabling
46
vhdl standards
18
VHDL93 .ini file variable
260
Viewing design hierarchy
111
virtual hide command
101
Virtual objects
100
virtual functions
102
virtual regions
102
virtual signals
101
virtual types
103
virtual region command
102
Virtual regions
reconstruct the RTL Hierarchy in gate level design
102
virtual save command
101
virtual signal command
101
Virtual signals
reconstruct RTL-level design busses
101
reconstruct the original RTL hierarchy
101