User`s manual

Simulating VHDL designs
4-46 VHDL Simulation ModelSim Xilinx User’s Manual
Selecting the time resolution
The simulation time resolution is 1 ns by default. You can select a specific time
resolution with the vsim
(CR-148) -t option or from the Load Design dialog box.
Available resolutions are: 1x, 10x or 100x of fs, ps, ns, us, ms, or sec.
For example, to run in picosecond resolution, or 10ps resolution respectively:
vsim -t ps topmod
vsim -t 10ps topmod
The default time resolution can also be changed by modifying the resolution (A-
283)
in the modelsim.ini file. You can view the current resolution by invoking the
report command
(CR-82) with the simulator state option.
See "Projects and system initialization"
(3-35) for more information on modifying
the modelsim.ini file.
vsim
(CR-148) is capable of annotating a design using VITAL compliant models
with timing data from an SDF file. You can specify the min:typ:max delay by
invoking vsim
(CR-148) with the -sdfmin, -sdftyp and -sdfmax options. Using the
SDF file f1.sdf in the current work directory, the following invocation of vsim
(CR-
148)
annotates maximum timing values for the design unit my_asic:
vsim -sdfmax /my_asic=f1.sdf
Timing check disabling
By default, the timing checks within VITAL models are enabled. They are also
disabled with the +notimingchecks option.
For example:
vsim +notimingchecks topmod