User`s manual
Compilation
5-64   Verilog Simulation ModelSim Xilinx User’s Manual
ModelSim Verilog supports the ‘uselib directive in a different manner than 
Verilog-XL. The library files referenced by the ‘uselib directive are not 
automatically compiled by ModelSim Verilog. The reason for this is that an object 
library is not allowed to contain multiple modules having the same name, and the 
results of a single invocation of the compiler can be placed in only one object 
library. Because it is an important feature of ‘uselib to allow a design to reference 
multiple modules having the same name, independent compilation of the source 
libraries referenced by the ‘uselib directives is required. Each source library 
should be compiled into its own object library. The compilation of the code 
containing the ‘uselib directives only records which object libraries to search for 
each module instantiation when the design is loaded by the simulator.
Because the ‘uselib directive is intended to reference source libraries, ModelSim 
Verilog must infer the object libraries from the library references. The rule is to 
assume an object library named work in the directory defined in the library 
reference dir=<library_directory> or the directory containing the file in the 
library reference file=<library_file>. The library reference 
libext=<file_extension> is ignored. For example, the following ‘uselib directives 
infer the same object library:
‘uselib dir=/h/vendorA
‘uselib file=/h/vendorA/libcells.v
In both cases ModelSim Verilog assumes that the library source is compiled into 
the object library /h/vendorA/work.
ModelSim Verilog also extends the ‘uselib directive to explicitly specify the 
object library with the library reference lib=<library_name>. For example,
‘uselib lib=/h/vendorA/work
The library name can be a complete path to a library, or it can be a logical library 
name defined with the vmap command. Since this usage of ‘uselib is an 
extension, it may be desirable to qualify it with an ‘ifdef to make it portable to 
other Verilog systems. For example,
‘ifdef MODEL_TECH
‘uselib lib=vendorA
‘else
‘uselib dir=/h/vendorA libext=.v
‘endif
The MODEL_TECH macro is automatically defined by the ModelSim compiler.










