User`s manual

Simulation
ModelSim Xilinx User’s Manual Verilog Simulation 5-65
Simulation
The ModelSim simulator can load and simulate both Verilog and VHDL designs,
providing a uniform graphic interface and simulation control commands for
debugging and analyzing your designs. The graphic interface and simulator
commands are described elsewhere in this manual, while this section focuses
specifically on Verilog simulation.
Invoking the simulator
A Verilog design is ready for simulation after it has been compiled into one or
more libraries. The simulator may then be invoked with the names of the top level
modules (many designs contain only one top level module). For example, if your
top level modules are "testbench" and "globals", then invoke the simulator as
follows:
vsim testbench globals
If a top-level module name is not specified, VSIM will present the Load Design
dialog box from which you can choose one or more top-level modules. See
"Simulating with the graphic interface"
(7-202) for more information.
After the simulator loads the top level modules, it iteratively loads the instantiated
modules and UDPs in the design hierarchy, linking the design together by
connecting up the ports and resolving hierarchical references. By default, all
modules and UDPs are loaded from the library named work.
On successful loading of the design, the simulation time is set to zero, and you
must enter a run command to begin simulation. Commonly, you enter run -all to
run until there are no more simulation events or until $finish is executed in the
Verilog code. You may also run for specific time periods, i.e., run 100 ns. Enter
the quit command to exit the simulator.
Simulation resolution limit
The simulator internally represents time as a 64-bit integer in units equivalent to
the smallest unit of simulation time, also known as the simulation resolution limit.
The resolution limit defaults to the smallest time precision found among all of the
‘timescale compiler directives in the design. The time precision is the second
number in the ‘timescale directive. For example, "10 ps" in the following:
‘timescale 1 ns / 10 ps