User`s manual
Simulation
ModelSim Xilinx User’s Manual Verilog Simulation  5-67
Tracking down event order dependencies is a tedious task, so ModelSim Verilog 
aids you with a couple of compiler options: 
-compat
This option turns off optimizations that result in different event ordering than 
Verilog-XL. ModelSim Verilog generally duplicates Verilog-XL event ordering, 
but there are caseswhere it is inefficient to do so. Using this option does not help 
you find the event order dependencies, but it allows you to ignore them. Keep in 
mind that this option does not account for all event order discrepancies, and that 
using this option may degrade performance.
-hazards 
This option detects event order hazards involving simultaneous reading and 
writing of the same register in concurrently executing processes. To enable hazard 
detection you must invoke vlog 
(CR-141) with the -hazards option when you 
compile your source code and you must also invoke vsim 
(CR-148) with the 
-hazards option when you simulate.
The vsim command 
(CR-148) detects the following kinds of hazards:
• WRITE/WRITE: 
Two processes writing to the same variable at the same time.
• READ/WRITE: 
One process reading a variable at the same time it is being written to by another 
process. VSIM calls this a READ/WRITE hazard if it executed the read first.
• WRITE/READ: 
Same as a READ/WRITE hazard except that VSIM executed the write first.
The vsim command 
(CR-148) issues an error message when it detects a hazard. The 
message pinpoints the variable and the two processes involved. You can have the 
simulator break on the statement where the hazard is detected by setting the break 
on assertion level to error. 
To enable hazard detection you must invoke vlog 
(CR-141) with the -hazards 
option when you compile your source code and you must also invoke vsim 
(CR-
148)
 with the -hazards option when you simulate.
Limitations of hazard detection:
• Reads and writes involving bit and part selects of vectors are not considered for 
hazard detection. The overhead of tracking the overlap between the bit and part 
selects is too high.
• A WRITE/WRITE hazard is flagged even if the same value is written by both 
processes.










