User`s manual

APPENDIX E – ANALOG I/O MEZZANINE CARD E-6
CDS7324 (FORMERLY LSF-0819)
Rev. A INSTALLATION & USER’S MANUAL
Paramete
r Number
Parameter Name Configuratio
n (stored) or
Realtime
Parameter
Default
Value
Description
2030 inc_Enc_Config Realtime 0 Sim Enc Config Register
2031 enc_sim_enable Configuration FALSE Sim Enc Enable (0 = off, 1 = on to enable
A & B simulated signals)
2032 enc_sim_reset Realtime FALSE Sim Enc Reset (0 = No, 1 = zero
accumulator)
2033 enc_sim_index_typ Configuration FALSE Sim Enc Index Type (0 = def. for non-
simulated generation, 1 = 50/50 index
marker)
2034 fpga_update_freq Configuration 20 Sim Enc FPGA Update Freq (multiples of
MHz)
2035 fpga_counter_mod Configuration 536870912 Sim Enc FPGA Counter Modulus (MSB)
2036 encoder_ppr Configuration 8192 Sim Enc Encoder pulser per rev (ppr)
2037 drv_resol Configuration 65536 Sim Enc Drive Resolution (counts/rev)
2038 delta_Pos_mult Realtime 3.2768 Sim Enc Delta Position scale multiplier
2039 enccnt_k Realtime - Sim Enc Encoder Counts (past position k)
2040 enccnt_k1 Realtime - Sim Enc Encoder Counts (current position
k+1)
2041 delta_Pos Realtime - Sim Enc Encoder Counts (current - past)
2042 delta_Fraction Realtime - Sim Enc Delta Fraction
2043 scaled_Delta_Pos Realtime - Sim Enc Scaled Delta Position
2044 integer_Delta_Pos Realtime - Sim Enc Integer Delta Position
2045 delta_Pos_Output Realtime - Sim Enc Delta Position Output to FPGA
Figure E10 Parameters
E.6.3 Simulated Encoder Signal Generation
The Simulated Encoder Signal Generation is a collaboration between the firmware and the FPGA. The firmware
implements a 16 bit delta value which is an input to the FPGA.
The firmware calculates a delta position count. This count is processed by the control card FPGA into A and B
quadrature signals which are output on the AnalogIO Mezzanine Card. The wiring of the AnalogIO Mezzanine
Card is as shown below:
DS2110 Connector, Pin, Signal
J5B – 6 – ENCODER_OUT_A(-)
J5B – 7 – ENCODER_OUT_B(-)
J5B – 1 – ENCODER_OUT_A(+)
J5B – 2 – ENCODER_OUT_B(+)
The FPGA takes the 16 bit delta value from the firmware and processes it to generate the A and B quadrature
signals and outputs them on the AnalogIO Mezzanine Card.
The simulated sine output will translate the sine information from the encoder to a reconstructed Quadrature
Differential signal based on the position of the motor. The simulated cosine output will translate the cosine
information from the encoder to a reconstructed analog cosine signal based on the position of the motor.
Encoder resolution is programmable. Typical DS2110 resolution = 65,536 counts/rev.