PENT/ATCA−717 Reference Guide P/N 6806800A15A April 2006
Copyright ECopyright 2006 Motorola GmbH All rights reserved. Motorola and the stylized M logo are trademarks of Motorola,Inc., registered in the U.S. Patent and Trademark Office. All other product or service names mentioned in this document are the property of their respective owners. Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola GmbH assumes no liability resulting from any ommissions in this document, or from the use of the information obtained herein.
Contents Using This Guide Other Sources of Information Safety Notes Sicherheitshinweise 1 Introduction About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Organization of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hard Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 CompactFlash Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 CMC Debug Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Restoring BIOS Default Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Updating BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 BIOS Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 BIOS Post Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPMC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Transfer Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 80 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPMC Extensions . . . . . . . . . . . . .
Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 80 Register . . . . . . . . . . . . . . . . . . .
Tables Introduction Tablei1aaaaaaaOrganization of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Tablei2aaaaaaaOrdering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Tablei3aaaaaaaAccessories Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tablei33aaaaaaUpper Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tablei34aaaaaaReference Clock Pulse Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tablei35aaaaaaVersion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tablei36aaaaaaAccess Control Register . . . . . . . . . .
Figures Installation Figurei1aaaaaaaLocation of Critical Blade Temperature Spots (Blade Top Side) . . . . . . . . . . . . . . . . . . . . . . . . Figurei2aaaaaaaLocation of Critical Blade Temperature Spots (Blade Bottom Side) . . . . . . . . . . . . . . . . . . . . . Figurei3aaaaaaaLocation of On−board Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figurei4aaaaaaaLocation of PMC Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figurei38aaaaaaClock Synchronization Building Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figurei39aaaaaaBlade Power Supply Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figurei40aaaaaaVLAN Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maps and Registers Figurei41aaaaaaPCI Structure . . . . .
Using This Guide This Reference Guide is intended for users qualified in electronics or electrical engineering. Users must have a working understanding of Peripheral Component Interconnect (PCI), AdvancedTCAR, and telecommunications. Conventions Notation Description 57 All numbers are decimal numbers except when used with the notations described below. 00000000 16 or 0x00000000 Typical notation for hexadecimal numbers (digits 0 through F), e.g.
Notation Description Dangerous situation: injuries to people or severe damage to objects possible Abbreviations Abbreviationa Descriptiona A A AC ANSI API APIC Alternating Current American National Standards Institute Application Programming Interface Advanced Programmable Interrupt Controller ATA ATCA Advanced Technology Attachment Advanced Telecommunications Computing Architecture B B BIOS BMC Basic Input/Output System Base Board Management Controller C C CMC CMOS CPU Common Mezzanine Car
Abbreviationa FCC Descriptiona Federal Communications Commission FIFO First In First Out FPGA Field−Programmable Gate Array FRU Field Replacable Unit G G GND Ground I I IDE Integrated Device Electronics IEC International Electric Code IPMB Intelligent Platform Management Bus IPMC Intelligent Platform Management Controller IPMI Intelligent Platform Management Interface ISA Industry Standard Architecture ISO International Organization for Standardization L L LCCB Line Card C
Abbreviationa Descriptiona R R RAM ROM RTC RTM Random Access Memory Read−Only Memory Real Time Clock Rear Transition Module S S S.M.A.R.T.
Order No.a Rev. Date Description 226132 AA May 2005 Changed logo, copyright, ...
Order No.a 6806800A15A PENT/ATCA−717 Rev.
Other Sources of Information For further information refer to the following documents.a Note:aCheck the Motorola literature catalog for errata sheets that may be applicable to the blade.a Company or Organisation www. Document Motorola motorola.com/co mputing ACC/ARTM−717 Installation Guide ACC/CABLE/RJ45/DSUB Installation Information aa aa ACC/ATCA−715/HDD Installation Guide ACC/ATCA−715/HDD−SATA Installation Guide aa aa ACC/ATCA*CMC*MODULE Installation Guide.
Company or Organisation www. Document PICMG picmg.org PICMG 3.0 Revision 1.0 Advanced TCA Base Specification PICMG 3.1 Revision 1.0 Specification Ethernet/Fiber Channel for AdvancedTCA Systems SMSC smsc.
Safety Notes This section provides safety precautions to follow when installing, operating, and maintaining the product. We intend to provide all necessary information to install and handle the product in this manual. However, as the product is complex and its usage manifold, we do not guarantee that the given information is complete. If you need additional information, ask your Motorola representative. The product has been designed to meet the standard industrial safety requirements.
Damage of Blade and Additional Devices and Modules Incorrect installation of additional devices or modules may damage the blade or the additional devices or modules. Before installing or removing an additional device or module, read the respective documentation Operation Blade damage Blade surface High humidity and condensation on the blade surface causes short circuits. Do not operate the blade outside the specified environmental limits.
Environment Always dispose of used blades according to your country’s legislation, if possible in an environmentally acceptable way. PMC Modules Limited Power on PMC Modules and RTMs The blade does not provide an extra fuse for PMC modules and RTMs.
Data loss Exchanging the battery always results in data loss of the devices which use the battery as power backup.a Therefore, back up affected data before exchanging the battery. Data loss If installing another battery type than is mounted at blade delivery may cause data loss since other battery types may be specified for other environments or may have a shorter lifetime. Therefore, only use the same type of lithium battery as is already installed.
Sicherheitshinweise Dieser Abschnitt enthält Sicherheitshinweise, die bei Installation, Betrieb und Wartung des Produkts zu beachten sind. Wir sind darauf bedacht, alle notwendigen Informationen, die für die Installation und den Betrieb erforderlich sind, in diesem Handbuch bereit zu stellen. Da es sich jedoch um ein komplexes Produkt mit vielfältigen Einsatzmöglichkeiten handelt, können wir die Vollständigkeit der im Handbuch enthaltenen Informationen nicht garantieren.
Datenverlust Wenn Sie das Blade aus dem Shelf herausziehen, und die blaue LED blinkt noch, gehen Daten verloren. Warten Sie bis die blaue LED durchgehend leuchtet, bevor Sie das Blade herausziehen. Beschädigung des Blades und von Zusatzmodulen Fehlerhafte Installation von Zusatzmodulen, kann zur Beschädigung des Blades und der Zusatzmodule führen. Lesen Sie daher vor der Installation von Zusatzmodulen die zugehörige Dokumentation.
Schaltereinstellungen Fehlfunktion des Blades Schalter, die mit ’Reserved’ gekennzeichnet sind, können mit produktionsrelevanten Funktionen belegt sein. Das Ändern dieser Schalter kann im normalen Betrieb Störungen auslösen.a Verstellen Sie nur solche Schalter, die nicht mit ’Reserved’ gekennzeichnet sind. Prüfen und ändern Sie die Einstellungen der nicht mit ’Reserved’ gekennzeichneten Schalter, bevor Sie das Blade installieren.
Beschaedigung einer installierten Festplatte Falls PPMC/270 oder PPMC/280−PMC−Module in PMC−Slot 1 oder 2 installiert sind, erhitzen die Kuehlkoerper dieser PMC−Module eine moeglicherweise gleichzeitig installierte Festplatte.a Falls PPMC/270− oder PPMC/280−PMC−Module in den PMC−Slots 1 oder 2 installiert sind, stellen Sie sicher, dass keine Festplatte zur gleichen Zeit auf dem Blade installiert ist.
1 Introduction About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Organization of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Features . . . . . . . . . . . . .
About this Manual Introduction About this Manual This Reference Guide provides the information you need to install, access and operate the blade.a Organization of this Manual The Reference Guide is organized as follows.
Introduction S About this Manual reader−comments@mcg.mot.com In all your correspondence, please list your name, position, and company. Be sure to include the title, part number, and revision of the manual and tell how you used it.
Features Introduction Features The PENT/ATCA−717 is an AdvancedTCA compliant single blade computer offering high processing performance. Four on−board PMC sites, GBit Ethernet connection to the AdvancedTCA Base and Fabric interface as well as standard I/O interfaces make it ideal for telecommunication and datacom applications. An on−board 16−port Ethernet switch allows switching between PMC sites, Base and Fabric interface and the base board.aaa Important features are: S Pentium M processor with up to 1.
Introduction Standard Compliances Standard Compliances Standard Description UL 60950−1 EN 60950−1 IEC 60950−1 CAN/CSA C22.2 No 60950−1 Legal safety requirements EN 55022 EN 55024 EN 300386 FCC Part 15a EMC requirements on system level (predefined Motorola system) ANSI/IPC−A610 Rev.C Class 2 ANSI/IPC−7711 ANSI/IPC−7721 ANSI−J−001...
Ordering Information Introduction Ordering Information When ordering the board variants, upgrades and accessories, use the order numbers given below. Product Nomenclature In the following you find the key for the product name extensions.aa PENT/ATCA−717/xx−yyyy aa xx Main memory in GByte yyyy CPU frequency in MHz Order Numbers The table below is an excerpt from the blade’s ordering information. Ask your local Motorola representative for the current ordering information.
Introduction 34 Ordering Information Order Number Accessory Description 122240 ACC/ATCA−715/HDD−SATA Serial ATA hard disk 122241 ACC/ATCA−CMC−MODULE CMC module for debugging 121793 ACC/CABLE/RJ45/DSUB Adapter cable: RJ−45 <−> DSUB 122242 ACC/CABLE/PMC/RJ45 Splitter cable for accessing serial interfaces of installed PMC*8260/DS1 or PPMC*280 modules 121792 ACC/CABLE/USB Adapter cable: mini USB B−male <−> USB A female PENT/ATCA−717
2 Installation Action Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .
Installation Action Plan Action Plan To install the blade, the following steps are necessary and described in detail in the sections of this chapter. The installation takes about five minutes.
Requirements Installation Requirements In order to meet the environmental requirements, the blade has to be tested in the system in which it is to be installed.a Before you power up the blade, calculate the power needed according to your combination of blade upgrades and accessories. Environmental Requirements The environmental conditions must be tested and proven in the shelf configuration used. The conditions refer to the surrounding of the blade within the user environment.
Installation Requirements Requirement Operating Non−Operating Rel.
Requirements Installation Figure 1: Location of Critical Blade Temperature Spots (Blade Top Side) PENT/ATCA−717 39
Installation Requirements 10 Figure 2: Location of Critical Blade Temperature Spots (Blade Bottom Side) Power Consumption The blade′s power requirements depend on the installed hardware accessories. If you want to install accessories on the board, the load of the respective accessory has to be added to that of the blade.In the following table you will find typical examples of power requirements with and without accessories installed.
Requirements Installation Characteristic Value Max. current 3.6A Max. power consumption of blade equipped with 4 GByte SDRAM without accessories 75W Max. total power consumption of all four PMC sites 60W Max. total power consumption of all installed blade accessories (PMCs + hard disk) 65W The blade provides two independent power inputs according to the AdvancedTCA Specification. Each input has to be equipped with an additional fuse of max.
Installation Switch Settings Switch Settings The blade provides the on−board switches SW2, SW3, SW4 and SW7. The following figure shows their location. Note that in the switch drawings the switch handle is represented by a little white square and that the shown switch settings reflect the default switch settings.
Switch Settings Installation S Blade Malfunction Switches marked as ’reserved’ might carry production−related functions and can cause the blade to malfunction if their setting is changed. Therefore, do not change settings of switches marked as ’reserved’. The setting of switches which are not marked as ’reserved’ has to be checked and changed before blade installation. S Blade Damage Setting/resetting the switches during operation can cause blade damage.
Installation Switch Switch Settings Description Note: the routing described above is only applicable to BIOS versions w 2.0.0. Earlier BIOS versions used a different routing. For further information refer to theaPENT/ATCA−715/717/7105/7107 BIOS Information Sheeta which can be downloaded from the former Force Computers S.M.A.R.T. server or the Motorola literature catalog web site.a Note: The COM port swapping can also be enabled via a System Boot Option IPMI command.
Switch Settings Installation Switch Description SW7−3 Routing of PMC slot 3 Pn4 connector pins 30 and 31 OFF: Pin 30 and 31 are routed to zone 3 backplane connector and are available as PMC I/O signals (default) ON: Pin 30 and 31 hold clock reference signals generated by clock synchronization building block SW7−4 Routing of PMC slot 4 Pn4 connector pins 30 and 31 OFF: Pin 30 and 31 are routed to zone 3 backplane connector and are available as PMC I/O signals (default) ON: Pin 30 and 31 hold clock ref
Installation On−Board Hardware Accessories On−Board Hardware Accessories The following hardware upgrades can be installed on the blade: S PMC modules S Hard Disk S CompactFlash card S CMC module PMC Modules The blade provides four PMC slots supporting PCI/PCI−X based PMC modules. When operated in PCI mode, PMC modules run at 33/66Mhz, when operated in PCI−X mode they run at 66/100MHz. All four PMC slots use a signaling level of 3.3V.aaaaa The four PMC slots are numbered from 1 to 4.
On−Board Hardware Accessories Installation Figure 4: Location of PMC Slots PMC slots 1 and 2 belong to one PCI segment and PMC slots 3 and 4 belong to another PCI segment. Within the same PCI segment, it is possible to install two PMC modules of different modes (PCI/PCI−X) and speeds (33/66/100 MHz). The PMC module with the overall lower performance (combination of speed and PCI mode) determines the speed and PCI mode of the second PMC module.
Installation On−Board Hardware Accessories S Limited Power on PMC Modules and RTMs The blade does not provide an extra fuse for PMC modules and RTMs. PMC modules and RTMs used together with the blade have to be qualified according to the following standards: IEC 60950−1, EN 60950−1, UL 60950−1, CAN/CSA C22−2 No 60950−1 S Excession of blade‘s power consumption Exceeding the maximum combined power dissipation of installed PMC modules may damage the blade.
On−Board Hardware Accessories Installation Hard Disk The blade allows to install one 2.5" hard disk which may be connected to either an on−board parallel or serial Advanced Technology Attachment (ATA) interface connector. The hard disk can be mounted directly on the blade without the need for an additional wire.aaa Figure 5: Location of On−Board Hard Disk The serial ATA interface supports up to 150 MByte/s data transfer rate and the parallel ATA supports all PIO and DMA modes up to Ultra ATA100.
Installation On−Board Hardware Accessories 1. Position hard disk above blade so that the blade′s parallel ATA or serial ATA or SATA connector faces the hard disk′s interface connector 2. Connect hard disk with blade′s connectora 3. Turn blade to face its bottom side 4. Fasten four screws to blade’s bottom side Removing a Hard Disk 1. Removing Hard Disk 2. Place blade on table with blade’s bottom side facing you 3. Remove four screws holding hard disk 4.
On−Board Hardware Accessories Installation Figure 6: Location of CompactFlash Disk Connector The CompactFlash card is operated in True IDE mode and is connected to the secondary IDE interface where it acts as IDE master.a CompactFlash Installation 1. Open locking bow 2.
Installation On−Board Hardware Accessories 3. Plug CompactFlash into socket 4. Close locking bow over CompactFlash disk Note:aThe locking bow must enclose the disk completely.a Removal Procedure 1. Open locking bow 2. Take CompactFlash disk′s ends and pull CompactFlash disk carefully out of socket 3. Close locking bow again CMC Debug Module A CMC debug module is available as accessory kit for the blade.
Rear Transition Modules Installation Rear Transition Modules At the time of writing this manual the following Rear Transition Modules (RTMs) was available for the blade: ACC/ARTM−717aa It provides the following interfaces:a S Two USB 2.
Installation Blade Installation Blade Installation The blade is fully compatible to the AdvancedTCA standard and is designed to be used in AdvancedTCA shelfs. Since the installation and removal procedures are different for powered and nonpowered shelfs, they are described in separate sections.aaaaa Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life.
Blade Installation Installation 7. Tighten the face plate screws which secure the blade to the shelfa 8. Connect cables to the face plate, if applicable Removal Procedure 1. Remove face plate cables, if applicableaa 2. Unfasten the screws of face plate until the blade is detached from shelf 3. Open the lower and the upper handle by pressing the two handle components together and turning the handles outwarda The blue LED blinks indicating that the blade power−down process is on−going.a 4.
Installation Blade Installation 7. Tighten the face plate screws which secure the blade to the shelf.a 8. Connect cables to the face plate, if applicable Removal Procedure 1. Remove face plate cables, if applicableaa 2. Unfasten the screws of the face plate until the blade is detached from the shelf 3. Open the lower and the upper handle by pressing the two handle components together and turning the handles outward 4.
Cable Accessory Kits Installation Cable Accessory Kits At the time of writing this manual the following cable accessory kits are available:aa S ACC/CABLE/PMC/RJ−45 S ACC/CABLE/RJ45/DSUB S ACC/CABLE/USB Note:aCheck with your local Motorola representative for the availability of further accessory kits.a ACC/CABLE/PMC/RJ−45 The ACC/CABLE/PMC/RJ45 is an accessory kit compiled for the ACC/ARTM−717 rear transition module.
3 Controls, Indicators, and Connectors Face Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Face Plate Controls, Indicators, and Connectors Face Plate The following figure shows the connectors, keys and LEDs available on the face plate.a P M C 1 OOS OK ACT HDD U S B 1 P M C 2 U S B 2 P M C 3 R E S E T H/S P M C 4 Figure 7: Face Plate LEDs The following figure shows all LEDs available at the face plate.
Controls, Indicators, and Connectors Face Plate OOS OK ACT HDD H/S Figure 8: Location of Face Plate LEDs The meaning of these LEDs is described in the following table.
Face Plate Controls, Indicators, and Connectors LED Description HDD After power−up or reset If no valid BIOS image has been found, the LED is lit red and the blade enters into BIOS crisis recovery mode.a Note that the enterring into BIOS crisis recovery mode can also be enforced via the on−board switch SW2−4.a For further details about the BIOS crisis recovery mode, refer toasection "BIOS Crisis Recovery Mode" on pagea86. During booting During booting this LED indicates the boot status.
Controls, Indicators, and Connectors Face Plate Reset Key P M C 3 R E S E T Figure 9: Location of Reset Key On pressing it, a hard reset is triggered and all attached on−board devices are reset. Note:aThe IPMC is not reset via this key.a Connectors The blade provides two mini USB 2.0 connectors of type AB at its face plate. They correspond to the USB interfaces 1 and 2. An adapter cable accessory kit called ACC/CABLE/USB is available for the blade.
Face Plate Controls, Indicators, and Connectors ACT USB 1 HDD U S B 1 USB 2 P M C 2 U S B 2 Figure 10: Location of USB Connectors Their pinout is given below.a 1 2 3 4 5 +5V USB_X_D− USB_X_D+ n.c.
Controls, Indicators, and Connectors On−Board Connectors On−Board Connectors The blade provides the following on−board connectors: S CompactFlash S PMC S Parallel ATAa S Serial ATA S CMC S ATCA backplane connectors Note:aThe blade may provide further on−board connectors. These are used for debug purposes only and are therefore not documented in this guide.a CompactFlash The CompactFlash connector is standard and is therefore not further described in this guide.
On−Board Connectors Controls, Indicators, and Connectors Figure 12: Location of PMC Connectors Pn1 to Pn4 The connectors Pn1 to Pn3 implement the PMC pinouts as specified by the IEEE P1386.1 standard. Therefore they are not documented in this guide. The connector Pn4 contains PMC I/O signals and is described in the following.
Controls, Indicators, and Connectors On−Board Connectors On the PMC sites 1 and 4, two Ethernet ports (signals named ETH*_) are routed to the on−board switch. On the PMC sites 2 and 3, only one port is routed to the on−board switch. The following two figures show the connector pinouts.aaa 1 n.c. 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 n.c. n.c. n.c. GND ETHB_DA+ ETHB_DA− GND ETHB_DB+ ETHB_DB− NETREF PMC_IO_25 n.c.
On−Board Connectors Controls, Indicators, and Connectors 1 ETHA_DA+ 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 GND ETHA_DB+ ETHA_DB− GND ETHB_DA+ ETHB_DA− GND ETHB_DB+ ETHB_DB− NETREF PMC_IO_25 n.c. PMC_IO_29 CLK8_B or PMC_IO_31 PMC_IO_33 PMC_IO_35 PMC_IO_37 PMC_IO_39 PMC_IO_41 PMC_IO_43 PMC_IO_45 PMC_IO_47 PMC_IO_49 PMC_IO_51 PMC_IO_53 PMC_IO_55 PMC_IO_57 PMC_IO_59 PMC_IO_61 PMC_IO_63 Diff. Pair { 3 ETHA_DA− Diff. Pair { Diff. Pair { Diff. Pair { Diff.
Controls, Indicators, and Connectors On−Board Connectors Figure 15: Location of Parallel ATA Connector The pinout of the connector is as follows.
On−Board Connectors 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 IDE1_RST# IDE1_D7 IDE1_D6 IDE1_D5 IDE1_D4 IDE1_D3 IDE1_D2 IDE1_D1 IDE1_D0 GND IDE1_DREQ IDE1_IOW# IDE1_IOR# IDE1_IORDY IDE1_DACK# IDE1_INT IDE1_A1 IDE1_A0 IDE1_CS0# IDE1_DASP# 5V GND Controls, Indicators, and Connectors GND IDE1_D8 IDE1_D9 IDE1_D10 IDE1_D11 IDE1_D12 IDE1_D13 IDE1_D14 IDE1_D15 KEY GND GND GND IDE1_CSEL GND n.c. IDE1_CBLID# IDE1_A2 IDE1_CS1# GND 5V n.c.
Controls, Indicators, and Connectors On−Board Connectors Figure 17: Location of Serial ATA Connector The pinout of the SATA connector is given in the following figure.
On−Board Connectors 1 2 3 4 5 6 7 GND SATA0_TX+ SATA0_TX− GND SATA0_RX− SATA0_RX+ GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND RSV 12V 12V 12V 12V Controls, Indicators, and Connectors 1 7 1 15 CMC Module Connector The blade provides one CMC connector which allows to connect a CMC debug module to the blade. A CMC debug module is available as accessory kit for the blade. The CMC module uses the same mounting holes as PMC slot #4.
Controls, Indicators, and Connectors On−Board Connectors Figure 18: Location of CMC Connector The pinout of the CMC connector is given in the following figure.
On−Board Connectors 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 V3P3 RS232_1_DCD− RS232_1_RXD RS232_1_TXD RS232_1_DTR− RS232_3_DCD− RS232_3_RXD RS232_3_TXD RS232_3_DTR− GND KBD_DATA KBD_CLK VP5_KBD GND Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GND Reserved Reserved Reserved Reserved n.c. Reserved n.c.
Controls, Indicators, and Connectors On−Board Connectors The pinouts of all these connectors are given in this section.
On−Board Connectors 33 30 Controls, Indicators, and Connectors 28 32 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 31 21 17 25 13 1 16 4 27 29 26 Reserved Reserved Reserved Reserved ABP_P10_HA0 ABP_P10_HA1 ABP_P10_HA2 ABP_P10_HA3 ABP_P10_HA4 ABP_P10_HA5 ABP_P10_HA6 ABP_P10_HA7 ABP_P10_IPMB0_A_SCL ABP_P10_IPMB0_A_SDA ABP_P10_IPMB0_B_SCL ABP_P10_IPMB0_B_SDA n.c. 24 20 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 n.c. n.c. n.c. n.c. n.c. n.c. n.c.
Controls, Indicators, and Connectors a CLK_1A+ b On−Board Connectors ab cd ef gh d CLK1A− c CLK1B+ CLK1B− 1 2 n.c. n.c. TERM_RX4_UP+ TERM_RX4_UP− 2 3 n.c. n.c. TERM_RX2_UP+ TERM_RX2_UP− 3 4 FAB8_TX+ FAB8_TX− FAB8_RX+ FAB8_RX− 4 5 n.c. n.c. TERM_RX15_2+ TERM_RX15_2− 5 6 n.c. n.c. TERM_RX15_0+ TERM_RX15_0− 6 7 n.c. n.c. TERM_RX14_2+ TERM_RX14_2− 7 8 n.c. n.c. TERM_RX14_0+ TERM_RX14_0− 8 9 n.c. n.c. TERM_RX13_2+ TERM_RX13_2− 9 10 n.c. n.c.
On−Board Connectors e 1 n.c. Controls, Indicators, and Connectors f n.c. ab cd ef gh TERM_RX7_3+ h TERM_RX7_3− 1 2 g 2 n.c. n.c. TERM_RX7_1+ TERM_RX7_1− 3 n.c. n.c. TERM_RX6_3+ TERM_RX6_3− 3 4 n.c. n.c. TERM_RX6_1+ TERM_RX6_1− 4 5 n.c. n.c. TERM_RX5_3+ TERM_RX5_3− 5 6 n.c. n.c. TERM_RX5_1+ TERM_RX5_1− 6 7 n.c. n.c. TERM_RX4_3+ TERM_RX4_3− 7 8 n.c. n.c. TERM_RX4_1+ TERM_RX4_1− 8 9 n.c. n.c. TERM_RX3_3+ TERM_RX3_3− 9 10 n.c. n.c.
Controls, Indicators, and Connectors On−Board Connectors Zone 3 contains the three connectors P30 to P32.
On−Board Connectors a Controls, Indicators, and Connectors b ab cd ef gh c d 1 PMC1_IO_26 PMC1_IO_28 PMC1_IO_25 PMC1_IO_30 1 2 PMC1_IO_34 PMC1_IO_36 PMC1_IO_37 PMC1_IO_39 2 3 PMC1_IO_42 PMC1_IO_44 PMC1_IO_45 PMC1_IO_47 3 4 PMC1_IO_52 PMC1_IO_54 PMC1_IO_53 PMC1_IO_55 4 5 PMC1_IO_61 PMC1_IO_63 PMC1_IO_62 PMC1_IO_64 5 6 PMC2_IO_29 PMC2_IO_31 PMC2_IO_33 PMC2_IO_35 6 PMC2_IO_38 PMC2_IO_40 PMC2_IO_41 PMC2_IO_43 7 8 PMC2_IO_46 PMC2_IO_48 PMC2_IO_49 PMC2_IO_51 8 9
Controls, Indicators, and Connectors e 1 PMC3_IO_29 f PMC3_IO_31 On−Board Connectors ab cd ef gh g h PMC3_IO_33 PMC3_IO_35 1 2 2 PMC3_IO_38 PMC3_IO_40 PMC3_IO_41 PMC3_IO_43 3 PMC3_IO_46 PMC3_IO_48 PMC3_IO_49 PMC3_IO_51 3 4 PMC3_IO_58 PMC3_IO_60 PMC3_IO_57 PMC3_IO_59 4 5 PMC4_IO_26 PMC4_IO_28 PMC4_IO_25 PMC4_IO_30 5 6 PMC4_IO_34 PMC4_IO_36 PMC4_IO_37 PMC4_IO_39 6 7 PMC4_IO_42 PMC4_IO_44 PMC4_IO_45 PMC4_IO_47 7 8 PMC4_IO_52 PMC4_IO_54 PMC4_IO_53 PMC4_IO_55 8
4 BIOS Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Serial Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIOS Introduction Introduction BIOS (Basic Input Output System) provides an interface between the operating system and the hardware of the blade. It is used for hardware configuration. Before loading the operating system, BIOS performs basic hardware tests and prepares the blade for the initial boot−up procedure. During blade production, identical BIOS images are programmed into the blade′s boot and user flash. By default the blade boots from the boot flash.
Introduction BIOS The BIOS complies to the following specifications: S Plug and Play BIOS Specification 1.0A S PCI BIOS Specification 2.1 S SMBIOS Specification 2.3 S BIOS Boot Specification 1.01 S PXE 2.
BIOS Serial Console Redirection Serial Console Redirection The firmware of the blade provides a serial console redirection feature. This allows remote blade configuration by connecting a terminal to the blade via a serial communication link.a The terminal can be connected to display VGA text information. Terminal keyboard input is redirected and treated as a normal PC keyboard input. The serial console redirection feature can be configured via setup utility.
Serial Console Redirection BIOS Note:a S The COM port routing described above is only applicable to BIOS versions w 2.0.0. Earlier BIOS versions used a different routing. For details refer to theaPENT/ATCA−715/717/7105/7107 BIOS Information Sheeta which can be downloaded from the Motorola literature catalog web site. S COM port swapping can also be enabled via an IPMI System Boot Options command.
BIOS BIOS Crisis Recovery Mode BIOS Crisis Recovery Mode Immediately after a reset or power−up a routine in the boot flash boot block is invoked which checks whether a valid BIOS image is available. If no valid image is found and consequently the blade is unable to boot, the blade enters into BIOS crisis recovery mode. In this mode a routine tries to load a BIOS crisis recovery image from a disk drive connected to the blade’ s USB interface.
Changing Configuration Settings BIOS Changing Configuration Settings When the system is turned on or rebooted, the presence and functionality of the system components is tested by POST (Power−On Self−Test).a Press when requested. The main menu appears. It looks similar to the menu shown in the following figure. Note that the layout may slightly vary with new BIOS versions.
BIOS Selecting The Boot Device Selecting The Boot Device There are two possibilities to determine the device from which BIOS attempts to boot: S Via setup to select a permanent order of boot devices S Via boot selection menu to select any device for the next boot−up procedure only Via Setup 1. In the menu line, select [Boot] A menu similar to the one shown in the following figure appears. Note that the layout may vary slightly with new BIOS versions.a 2.
Selecting The Boot Device BIOS 3. Select the order of the devices from which BIOS attempts to boot the operating system If BIOS is not successful at booting from one device, it tries to boot from the next device on the list. If there is more than one device of the same type, e.g. several hard disks, the displayed entry represents the first of these devices as specified in the boot configuration via setup.
BIOS Selecting The Boot Device Figure 33: Boot Menu Continue with one of the following options: a) Override existing boot sequence by selecting another boot device from the boot order list or b) Select [Enter Setup] to enter setup utility or c) Press to return to POST screen and continue with previous boot sequence Note:aIf the selected device does not load the operating system, BIOS reverts to the previous boot sequence.
Restoring BIOS Default Settings BIOS Restoring BIOS Default Settings The blade provides an on−board configuration switch that allows to clear the blade’s CMOS and thus to restore the BIOS default settings. In order to restore the BIOS default settings using this switch, you have to proceed as follows.aa Procedure 1. Remove the blade from the system Seeasection "Installation into Powered Shelves" on pagea54a for the exact procedure 2.
BIOS Updating BIOS Updating BIOS For the blade a BIOS upgrade kit is offered. It is available via the former Force Computers S.M.A.R.T. web site or the Motorola web site.aaa Note:aWhen upgrading the BIOS, all BIOS settings are reset to their default state.
BIOS Messages BIOS BIOS Messages If your system fails after you made changes in the setup menus, you may be able to correct the problem by entering setup and restoring the original values.a Message Explanationa Corrective Action nnnn Cache SRAM Passed nnnn is amount of system cache in KBytes successfully tested None CD−ROM Drive Identified Autotyping identified CD−ROM Drive None Diskette drive A errorDiskette drive B error Drive A: or B: fails the BIOS POST disk tests.
BIOS 94 BIOS Messages Message Explanationa Corrective Action Keyblade error Keyblade not working Check for correct keyblade connection. Keyblade error nnn BIOS discovered a stuck key and displays scan code nn for stuck key Replace keyblade, check for stuck keys Operating system not found Operating system cannot be located on either drive A: or drive C:. Enter setup and check if fixed disk and drive A: are properly identified. Parity Check 1 nnnn Parity error found in system bus.
BIOS Messages BIOS Message Explanationa System battery is dead − Replace and run SETUP The NVRAM (CMOS) clock Replace battery and run battery indicator shows the setup to reconfigure battery is dead. system. System BIOS shadowed System BIOS copied to shadow RAM None System cache error − Cache disabled RAM cache failed BIOS test. BIOS disabled cache Contact your local sales representative or FAE for further support.
BIOS BIOS Post Codes BIOS Post Codes The following table lists BIOS post codes applicable to the used Phoenix 4.0 Release 6.0 BIOS. The BIOS POST codes are stored in the blade′s Port 80 register and can also be obtained by reading an on−board IPMI sensor. For details refer to theaPENT/ATCA*715/717/7105/7107: Control via IPMI Programmer’s Guide which can be downloaded from the Motorola literature catalog.
BIOS Post Codes BIOS Post Code Description 24 Set ES segment register to 4GB 26 Enable gate A20 line 28 Autosize DRAM 29 Initialize POST memory manager 2A Clear 512KB base RAM 2C RAM failure on address line xxxx 2E RAM failure on data bits xxxx of low byte of memory bus 2F Enable cache before system BIOS shadow 30 RAM failure on data bits xxxx of high byte of memory bus 32 Test CPU bus clock frequency 33 Initialize Phoenix Dispatch Manager 36 Warm start shut down 38 Shadow syste
BIOS 98 BIOS Post Codes Post Code Description 52 Test keyboard 54 Set key click if enabled 55 Enable USB devices 58 Test for unexpected interrupts 59 Initialize POST display service 5A Display prompt "Press F2 to enter SETUP" 5B Disable CPU cache 5C Test RAM between 512KB and 640KB 60 Test extended memory 62 Test extended memory address lines 64 Jump to UserPatch1 66 Configure advanced cache registers 67 Initialize Multi Processor APIC 68 Enable external and CPU caches 69 S
BIOS Post Codes BIOS Post Code Description 85 Initialize PC compatible PnP ISA devices 86 Reinitialize onboard I/O ports 87 Configure motherboard configurable devices (optional) 88 Initialize BIOS data area 89 Enable non−maskable interrupts (NMI’s) 8A Initialize extended BIOS data area 8B Test and initialize PS/2 mouse 8C Initialize floppy controller 8F Determine number of ATA drives (optional) 90 Initialize hard disk controllers 91 Initialize local bus hard disk controllers 92 Ju
BIOS 100 BIOS Post Codes Post Code Description B0 Check for errors B1 Inform RomPilot about the end of POST B2 POST done − prepare to boot operating system B4 One short beep B5 Terminate QuietBoot (optional) B6 Check password B7 Initialize ACPI BIOS B9 Prepare boot BA Initialize DMI parameters BB Initialize PnP option ROM’s BC Clear parity checkers BD Display multiboot menu BE Clear screen BF Check virus and backup reminders C0 Try to boot with interrupt 19 C1 Initialize
BIOS Post Codes BIOS Post Code Description D2 Unknown interrupt aa The following are for boot block in Flash ROM E1 Initialize the bridgea E2 Initialize the CPUa E3 Initialize the system timera E4 Initialize system I/Oa E5 Check recovery boota E6 Checksum BIOS ROMa E7 Go to BIOSa E8 Set Huge Segmenta E9 Initialize Multi Processora EA Initialize OEM special codea EB Initialize PIC and DMAa EC Initialize Memory typea ED Initialize Memory sizea EE Shadow Boot Blocka EF Syst
BIOS 102 BIOS Post Codes Post Code Description E6 Checksum BIOS ROMa E7 Go to BIOSa E8 Set Huge Segmenta E9 Initialize Multi Processora EA Initialize OEM special codea EB Initialize PIC and DMAa EC Initialize Memory typea PENT/ATCA−717
5 Devices’ Features and Data Paths Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Host Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . .
IPMC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Transfer Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 80 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPMC Extensions . . . . . . . . . . . . .
Block Diagram Devices’ Features and Data Paths Block Diagram RS−232 (via CMC Module) RS−232 KBD/MSE (via CMC Module) PCI Bridge P64H2 2x USB 2.
Devices’ Features and Data Paths CPU CPU The used Central Processing Unit (CPU) is a Pentium M processor. The CPU provides 32 kBytes of on−die data and instruction cache as well as two MByte L2 cache.aaa An on−die temperature sensor measures the CPU temperature. It is connected to the blade’s Intelligent Peripheral Management Controller (IPMC). This way software can monitor the CPU temperature via IPMI.
Host Bridge Devices’ Features and Data Paths Host Bridge The used host bridge is an Intel E7501 Memory Controller Hub (MCH) device. It is part of the Intel Plumas chipset and provides bus control signals, address and data paths for transfers between the CPU front side bus, main memory and the four hub interfaces provided by the host bridge.aaa Host Interface The host interface supports a 64−bit wide data bus and a 32−bit wide address bus.
Devices’ Features and Data Paths South Bridge South Bridge The used South Bridge is an Intel 6300ESB I/O controller hub device. It provides the interface between the Host Bridge and the legacy I/O. Integrated into the South Bridge are:aa S Two 8237 DMA controllers S One 8254 counter timer S Interrupt controller S Real−time clock S Watchdog The interfaces provided by the South Bridge include:a S Hub interface 1.5 S PCI 2.2 interface S PCI−X 1.
South Bridge Devices’ Features and Data Paths S Hub interface ECC and parity errors S PCI bus parity errors Real−Time Clock The Real−Time Clock (RTC) resides inside the South Bridge and is sourced by an external 32.768 crystal providing a frequency tolerance of 20 ppm. The RTC provides 242 bytes backed−up CMOS RAM and is fully compliant to:aa S DS1287 S MC14618 S Y2K S PC87911 Watchdog The Southbridge incorporates a two−stage watchdog timer.
Devices’ Features and Data Paths South Bridge Secondary Parallel ATA Interface The secondary parallel ATA interface is connected to an on−board CompactFlash connector which supports CompactFlash cards of type I and II. An inserted card runs in true IDE mode and is master on the secondary parallel ATA interface.a USB Interfaces The South Bridge provides four USB interfaces. Two are routed to the blade′s face plate and two to the rear transition module. All interfaces are compliant to the USB 2.0 standard.
South Bridge Devices’ Features and Data Paths S Boot flash S User flash S Glue Logic FPGA SMBus Interface The following table lists all devices which are connected to the South Bridge via its SMBus interface:aaaa Device Name Device Type SMBus Address SPD EEPROM (contains memory configuration data of memory module, used by BIOS) 24C02 0xA0 SPD EEPROM (contains memory configuration data of memory module, used by BIOS) 24C02 0xA1 Host Bridge Intel E7501 0x60 PCI bridge P64H2 0xC0 South B
Devices’ Features and Data Paths Super I/O Super I/O The used Super I/O is a Standard Microsystems Corporation LPC47S422 device. It provides the following interfaces:aa S Two serial interfaces S Floppy disk interface S Keyboard/Mouse interface S Parallel interface Serial Interfaces The Super I/O device provides two serial full−duplex RS232 interfaces. Supported baud rates are: 600, 1200, 2400, 4800, 9600, 19200, 38400 and 115200 kb/s. Both serial interfaces are +/− 15 KV ESD protected.
Flash Devices Devices’ Features and Data Paths Flash Devices The blade provides two redundant boot flash devices: one default boot flash and one backup boot flash. During blade production, both flashes are programmed with identical BIOS images. The presence of two redundant flash devices allows for remotely updating BIOS images from the operating level without interrupting running processes and without being affected by possibly corrupt BIOS images.
Devices’ Features and Data Paths Flash Devices some reserved spaces in the data/instruction area. The boot block of default and backup boot flash are writeable per default, too. The on−board switches SW4−1, SW4−2 and SW4−4 allow to enable/disable the write−protection of both default and backup boot flash as well as the data/instruction area of the backup boot flash.
FPGA Devices’ Features and Data Paths FPGA The FPGA implements the following functions:aaaaa S LPC interface S IPMC interface S Clock synchronization extensions S Reset controller S Interrupt routing unit S Miscellaneous glue logic S Ethernet switch interface The FPGA loads its configuration stream from one of two EEPROMs which are connected to the FPGA. One EEPROM serves as default, the second as backup EEPROM. The IPMC controls which EEPROM the configuration stream is loaded from.
Devices’ Features and Data Paths FPGA compliant to the IPMI specification V1.5 Rev. 1.0 and share one Interrupt Source register. The first BT interface is used as the only System Interface and uses IPMI channel 0x0F. The second BT interface uses IPMI channel 0x06.aaa Port 80 Register The FPGA provides an 8−bit wide register to store POST codes. The register is located at I/O address 8016.. It is only readable for the IPMC and read−writeable for the host.
FPGA Devices’ Features and Data Paths During a hard reset all internal registers, state machines and caches of the CPU are reset. Furthermore all on−board PCI devices as well as the host bridge are reset.a During a soft reset the CPU is reset, with the exception of the internal caches and state machinesaaa Reset Sources The following table lists all possible reset sources and the corresponding reset types.
Devices’ Features and Data Paths S LEDs S Version register FPGA Serial Interface The FPGA provides routing options of one of the two serial interfaces provided by the Southbridge. This feature is intended for Motorola−internal purposes and should be ignored. .a Reset Mask and Source Register The FPGA provides two registers which allow to obtain the last reset source and to mask resets. Seeasection "Reset Registers" on pagea139.
Intelligent Platform Management Controller Devices’ Features and Data Paths Intelligent Platform Management Controller The blade provides an Intelligent Platform Management Controller (IPMC) unit based an the 8−bit Atmel ATmega AVR microcontrollers. The IPMC is fully compliant to the IPMI V1.
Devices’ Features and Data Paths Intelligent Platform Management Controller Sensors The blade provides various sensors which are accessible via IPMI. Some of these sensors measure on−board temperatures. Their names and locations are shown in the following figure.aaa Memory Temp CPU Board Temp (other side of PCB) CPU Die Temp 12V DCDC Temp Ambient Temp Figure 37: IPMI Temperature Sensors Other sensors available on−board include voltage sensors and sensors which provide particular status information.
Intelligent Platform Management Controller Devices’ Features and Data Paths Table 11: On−board Sensors Accessible via IPMI Sensor Name Type of Measurement What Does It Measure? Sensor Type Availability Ambient Temp Temperature Ambient temperature near Compact flash connector Analog Always Memory Temp Temperature Temperature of on−board memorya Analog Always CPU Board Temp Temperature Board temperature near the CPU Analog Always CPU Die Temp Temperature CPU temperature Analog Always
Devices’ Features and Data Paths 122 Intelligent Platform Management Controller Sensor Name Type of Measurement What Does It Measure? Sensor Type Availability Mem Volt +2.5V Voltage +2.5V voltage level of the memory supply voltage Analog While Payload powered ON Sw Volt +1.2V Voltage +1.
Intelligent Platform Management Controller Devices’ Features and Data Paths Sensor Name Type of Measurement What Does It Measure? Sensor Type Availability 715 FPGA Version Version FPGA version of ATCA−715 Discrete Always after payload has first been powered ON FW Revision ISC0 Revision Revision of the Intelligent Slave Controller 0 (ISC0) firmware Discrete Always FW Revision ISC1 Revision Revision of the Intelligent Slave Controller 1 (ISC1) firmware Discrete Always 715 IPMC Status I
Devices’ Features and Data Paths Clock Synchronization Interface Clock Synchronization Interface AdvancedTCA systems provide a telecom clock synchronization interface which allows to synchronize elements within a telecommunication network. The telecom clock synchronization interface consists of three redundant clock buses (CLK1, CLK2 and CLK3) which are available at the system backplane. Each clock bus is implemented as a differential pair of MDS/LDS signals which connects to each system slot.
Clock Synchronization Interface Devices’ Features and Data Paths S 8 kHz frame clock/pulse with programmable pulse width and polarity (SYNC_0,1,2,3)) S Automatic hit−less switch−over if one system clock fails S Activity monitor for system clocks S Phase build−out for output clock phase continuity during switch−over S Meets jitter requirements up to OC−3 line rates S Programmable reference clock divider The DPLL is clocked by an external oscillator running at 12.8 MHz.
Devices’ Features and Data Paths Power Supply Module Power Supply Module The blade is fed via two redundant −48V inputs. Both are converted via a DC/DC converter to an intermediate voltage of +12V. This voltage, in turn, is converted via further DC/DC converters to on−board voltages which are used by the on−board devices. A −48V/+3.3V DC/DC converter converts the −48V input voltage to +3.3V which is used to feed the IPMC and power−up logic.
PCI Bridge P64H2 Devices’ Features and Data Paths PCI Bridge P64H2 The Intel P64H2 PCI bridge provides two PCI/PCI−X interfaces. Each interface is connected to two PMC sites. The P64H2 device supports peer−to−peer communication between the two PCI/PCI−X interfaces. This way no host intervention is required when PMC sites connected to different PCI/PCI−X interfaces communicate with each other. In PCI mode up to 533 MHz/s transfer rate is possible, in PCI−X up to 800 MByte/s.
Devices’ Features and Data Paths Switching Unit Switching Unit The on−board switching unit is based on the Marvell 98DX160 Ethernet layer 2+ switch and provides switching functionality between on−board Ethernet ports, PMC sites and the backplane interfaces. It provides 16 Ethernet switching ports as well as one Serial Management interface (SMI) and one additional Ethernet port for configuration.
Switching Unit Devices’ Features and Data Paths At blade start−up the Ethernet switch reads a serial PROM which contains switch configuration information such as predefined Virtual Local Area Networks (VLANs).a The following table shows how the Ethernet interfaces are distributed across the 16 Ethernet switch ports.
Devices’ Features and Data Paths Host A Host B 14 Switching Unit 8+4 15 Fabric channel 1 9+7 PMC 1A n/a PMC 1B PMC 2A 10 0 Fabric channel 3 11 Fabric channel 4 5 PMC 2B 1 PMC 3A 6 PMC 3B Fabric channel 2 2 PMC 4A n/a 12 PMC 4B Base channel 1 3 13 Base channel 2 Tagged VLAN Untagged VLAN Figure 40: VLAN Configuration The following table summarizes the Ethernet switch configuration by listing Ethernet interfaces, port numbers, VLAN IDs and Ethernet types.
Switching Unit Devices’ Features and Data Paths Note:aOnly port 0 and 1 of the fabric channels are used.
6 Maps and Registers I/O and Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 FPGA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O and Memory Maps Maps and Registers I/O and Memory Maps The following table shows the blade′s main address map.a Table 14: Memory Address Map Base Address Size Device FFF0.000016 1 MByte Boot Flash FFE0.000016 1 MByte User Flasha 0000.0000 16 Up to 4GByte Main Memory The I/O addresses of all on−board functional units are listed below.aaa Table 15: I/O Address Map Device Base Address DMA Controller #1 00016...01F16a and 08016...09F16 Interrupt Controller #1 02016...03F16 Timer 04016..
Maps and Registers 134 I/O and Memory Maps Device Base Address COM 3 2F816...2FF16a or 2E816...2EF16a or 3E816...3EF16a or 3F816...3FF16 COM 4 2F816...2FF16a or 2E816...2EF16a or 3E816...3EF16a or 3F816...
Hardware Interrupts Maps and Registers Hardware Interrupts The following table lists the blade′s hardware interrupts and the corresponding interrupt sources.a Note:aAll interrupts marked with an asterisk (*) must not be used for PCI interrupt routing.
Maps and Registers PCI Devices PCI Devices The following figure shows the on−board PCI device structure.aaa PCI I/O Bridge Bus #5 PMC#1 Dev. No. = 3 PMC#2 Dev. No. = 1 PMC#3 Dev. No. = 2 PMC#4 Dev. No. = 4 Dev. No. = 31 PCI Host Bridge PCI Bus #3 PCI PCI Dev. No. = 2 Bus #4 Dev. No. = 29 PCI South Bridge PCI Dev. No. = 30 PCI Intel 82540EM Bus #2 PCI Bus #0 PCI PCI Dev. No. = 28 ETH#2 Dev. No. = 4 Bus #1 Intel 82546EB/GB ETH#0/1 Dev. No.
FPGA Registers Maps and Registers FPGA Registers The FPGA provides various control and status registers. Some of these registers are accessible from the CPU host via the LPC bus, some by the IPMC, others by both. In the following all registers will be described which are accessible from the CPU. These registers are listed in the following table.
Maps and Registers FPGA Registers IPMI Block Transfer Interface Registers The host can access the IPMC via the two Block Transfer (BT) Interfaces 0 and1. Both are fully compliant to the IPMI specification V1.5. Each BT interface provides the following registers.
FPGA Registers Maps and Registers Address Offset Register 0216 Lower data register 0316 Upper data register 0416 Clock divider register 0516 I2C Control and Status Register Command and Status Register This register controls the transfer of configuration data to and from the Ethernet switch.a Table 22: Command and Status Register Bit Description Access 4..
Maps and Registers S FPGA Registers Reset mask register (index address 0x01) The reset source register stores the source of the most recent reset. A write access clears this register.Each bit is associated with one reset source. If the bit is set to one, the corresponding reset has occurred. After a reset has occurred, this register should be cleared. Otherwise, after the next reset of another source, more than one bit is set and you may not be able to determine the most recent reset source.
FPGA Registers Maps and Registers Bit Signal Description Default Access 2 PB_RES Face plate push button Reset 0: Disabled 1: Enabled 12 r/w 3 DB_RES ITP debug reset 0: Disabled 1: Enabled 12 r/w 4 RTM_RES RTM reset 0: Disabled 1: Enabled 12 r/w 5 PMC_RSTa PMC slots reset 0 : Disabled 1: Enabled 12 r/w 6 − Reserved 02 r 7 − Reserved 02 r Flash Control and Status Register This register, which is accessible via the index address 0x02, indicates the status of the default and
Maps and Registers FPGA Registers Bit Description Default Access 4 Select status of default and backup boot flash write protection 0: Write−protection determined by on−board switches 1: Write−protection determined by this register 02 r 6:5 Indicates flash that is booted from 002: Default boot flash 012: Backup boot flash 002 r 7 Crisis recovery (indicates status of crisis recovery switch) 0: Crisis recovery 1: Normal operation 12 r LED Control Register This register, which is accessible vi
FPGA Registers Maps and Registers PMC Status Register This register, which is accessible via the index address 0x04, indicates the current status of all four on−board PMC sites.
Maps and Registers FPGA Registers Clock Synchronization Interface Registers These registers are related to the clock synchronization building block of the blade.
FPGA Registers Maps and Registers DPLL Input Select and Control Register Table 29: DPLL Input Select and Control Register Bit Description Default Access 0 Selects DPLL clock sourcea 0: System clock 1: Reference clock 02 r/w 1 Selects system clock source CLK1 or CLK2 0: CLK2 1: CLK1 02 r/w 2 Unused 02 r 3 SPI interface is ready for access 0: Wait 1: SPI Ready 12 r 4 Enabling of 2 kHz system clock interrupt 0: Disabled 1: Enabled 02 r/w 5 2 kHz system clock interrupt status 0: Not a
Maps and Registers FPGA Registers Bit Description Default Access 4 Enable reference clock CLK3_A 0: Disabled 1: Enabled 02 r/w 5 Enable reference clock CLK3_B 0: Disabled 1: Enabled 02 r/w 6 Selects if clock divider is bypassed 0: Divide clock 1: Bypass divider 12 r/w 7 Selection between pulse/clock on REF_CLK output signal 0: Pulse enabled 1: Pulse disabled 12 r/w Reference Clock Divider Registers The FPGA contains a clock divider which can be used in systems where the reference clock
FPGA Registers Maps and Registers Recovered Clock Frequency Reference Clock Frequency Division Factor 38.88 MHz 19.44 MHz 2 77.76 MHz 19.44 MHz 4 Note:aIf the division factor is 1, i.e. no clock division is done, the clock divider should be bypassed. This can be done via the reference clock source register.a Lower Divider Register Table 32: Lower Divider Register Bit Description Default Access 7..
Maps and Registers FPGA Registers Table 35: Version Register Bit Description Default Access 7..0 FPGA version FD16a(at the time of writing this guide) r Access Control Register This register determines the current owner of the following interfaces: S Clock synchronisation building block interface S Ethernet switch management interface S SPROM update interface The current owner of each interface is either the IPMC or the host CPU.
A Troubleshooting PENT/ATCA−717 149
Troubleshooting Error List Error List A typical ATCA system is highly sophisticated. This chapter can be taken as an error list for detecting erroneous system configurations and strange behaviors. It cannot replace a serious and sophisticated presales and postsales support during application development. If it is not possible to fix a problem with the help of this chapter, contact your local sales representative or Field Application Engineer (FAE) for further support.
B Battery Exchange PENT/ATCA−717 151
Battery Exchange Battery Exchange Battery Exchange The blade contains an on−board battery. Its location is shown in the following figure.a Figure 42: Location of On−board Battery The battery provides data retention of seven years summing up all periods of actual data use. Motorola therefore assumes that there usually is no need to exchange the battery except, for example, in case of long−term spare part handling.
Battery Exchange Battery Exchange S Data loss If the battery does not provide enough power anymore, the RTC is initialized and the data in the NVRAM is lost. Therefore, exchange the battery before seven years of actual battery use have elapsed. S Data loss Exchanging the battery always results in data loss of the devices which use the battery as power backup.a Therefore, back up affected data before exchanging the battery.
Index A Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 B Backplane connectors . . . . . . . . . . . . . . . . . . . . . . . . 73 BIOS Boot device order . . . . . . . . . . . . . . . . . . 88 Main features . . . . . . . . . . . . . . . . . . . . . . 82 POST codes . . . . . . . . . . . . . . . . . . . . . . . 96 Restore default settings . . . . . . . . . 43,a91 Serial Console Redirection . . . . . . . . . . 84 Update . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main features . . . . . . . . . . . . . . . . . . . . . 124 Compact flash disk . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 COM ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110,a112 Configuration switches . . . . . . . . . . . . . . . . . . . . . . . . 42 D Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 E Environmental Requirements . . . . . . . . . . . . . . . . . . 37 Ethernet switching unit Main features . . . . . . . . . . . . . . . . . . . .
N Non−maskable interrupts . . . . . . . . . . . . . . . . . . . . . 108 O On−board Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 P PCI devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 PCI Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 PMC modules Performance limitations . . . . . . . . . . . . . 47 PMC connector pinout . . . . . . . . . . . . . .
