Computer Accessories User Manual

Host Bridge Devices’ Features and Data Paths
PENT/ATCA−717 107
Host Bridge
The used host bridge is an Intel E7501 Memory Controller Hub (MCH) device. It is part of
the Intel Plumas chipset and provides bus control signals, address and data paths for
transfers between the CPU front side bus, main memory and the four hub interfaces
provided by the host bridge.
aaa
Host Interface
The host interface supports a 64−bit wide data bus and a 32−bit wide address bus. The
data bus is quadpumped and runs at 100 MHz, resulting in a total bandwidth of 3.2 GB/s.
The memory bus is double pumped and supports an address range of up to 4 GByte. Its
bandwidth is 200 Mb/s per data line resulting in a total bandwidth of 128 x 200MB/S =
3.2GB/s.
a
Memory Interface
The memory interface is a 144−bit wide SDRAM interface supporting 64, 128, 256 and 512
MBit DDR SDRAM technology. The bus speed is 100 MHz running synchronously to the
front side bus. Additionally ECC is supported.
a
Although theoretically up to 16 GByte are supported by the memory interface, the actual
maximum memory size is limited to 4 GByte due to the CPU′s 32−bit address bus.
a
Hub Interfaces
The Host Bridge provides the four hub interfaces A, B, C and D.a
Hub interface A is quad pumped, 8−bit wide and runs at 66 MHz. It is connected to the
South Bridge and provides a maximum data transfer rate of 266MByte/s. Parity
protection is provided for hub interface A. Any parity errors are detected by the host
bridge and reported to the South Bridge, which in turn generates an NMI.
a
The hub interfaces B, C and D are octal pumped, 16−bit wide and run at 66 MHz. The
maximum data transfer rate provided by each hub interface is 1.066 GByte/s.
a
ECC protection is provided for hub interfaces B, C and D. Any ECC errors are detected by
the host bridge and reported to the South Bridge, which in turn generates an NMI.
a