Computer Accessories User Manual

FPGA Registers Maps and Registers
PENT/ATCA−717 145
DPLL Input Select and Control Register
Table 29: DPLL Input Select and Control Register
Bit
Description Default Access
0 Selects DPLL clock sourcea
0: System clock
1: Reference clock
0
2
r/w
1 Selects system clock source CLK1 or CLK2
0: CLK2
1: CLK1
0
2
r/w
2 Unused 0
2
r
3 SPI interface is ready for access
0: Wait
1: SPI Ready
1
2
r
4 Enabling of 2 kHz system clock interrupt
0: Disabled
1: Enabled
0
2
r/w
5 2 kHz system clock interrupt status
0: Not active
1: Interrupt pending
0
2
r
6 Clear 2 kHz system clock interrupt
Writing 0 clears the interrupt
Read accesses always return 0
− r/w
7
Reset signal for DPLL
0: Reset asserted
1: Normal operation
0
2
r/w
Reference Clock Source Register
Table 30: Reference Clock Source Register
Bit
Description Default Access
1..0 Selects clock source for reference clock
00
2
: RCVD_CLK_0
01
2
: RCVD_CLK_1
10
2
: RCVD_CLK_2
11
2
: RCVD_CLK_3
00
2
r/w
3..2 Selects interrupt rate for interrupt
LCCB_INT_N clocked by 2 kHz system
clock reference
00
2
: 500 µs
01
2
: 1 ms
10
2
: 10 ms
11
2
: 1 s
00
2
r/w