CPX8000 Series CPX8216/CPX8216T CompactPCI® System Reference Manual CPX8216A/RM4 August 2002 Edition
© Copyright 2002 Motorola Inc. All rights reserved. Printed in the United States of America. Motorola® and the Motorola symbol are registered trademarks of Motorola, Inc. PowerPC® and the PowerPC logo are registered trademarks of International Business Machines Corporation (IBM) and are used by Motorola, Inc. under license from IBM. CompactPCI® is a registered trademark of the PCI Industrial Computer Manufacturer’s Group (PICMG).
Safety Summary The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware.
Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. CE Notice (European Community) Warnin g ! Warning This is a Class A product. In a domestic environment, this product may cause radio interference, in which case the user may be required to take adequate measures. Motorola Computer Group products with the CE marking comply with the EMC Directive (89/336/EEC).
FCC Class A This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
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Contents About this Manual Summary of Changes ................................................................................................xix Systems Supported ....................................................................................................xxi Overview ..................................................................................................................xxii Comments and Suggestions .....................................................................................
Hot Swap Control Status Register (CSR) ........................................................ 1-16 The Hot Swap Process ............................................................................................ 1-16 Physical Connection Process ........................................................................... 1-17 Hardware Connection Process ......................................................................... 1-17 Software Connection Process ................................................
CHAPTER 4 PMC Modules Overview .................................................................................................................. 4-1 SCSI-2 Controller PMC ........................................................................................... 4-1 Switch Settings .................................................................................................. 4-3 Connector Pin Assignments ..............................................................................
Indicator LED/Miscellaneous Header (J2) ............................................... 5-43 CHAPTER 6 Subassembly Reference Chapter Overview ..................................................................................................... 6-1 Parts of the System ................................................................................................... 6-2 CompactPCI Card Cage Reference .......................................................................... 6-4 Backplane Reference ........
APPENDIX A Specifications Environmental Characteristics .................................................................................A-1 Power Supply Electrical Specifications ...................................................................A-2 APPENDIX B Related Documentation Motorola Computer Group Documents ...................................................................B-1 Related Specifications ..............................................................................................
List of Figures Figure 1-1. CPX8216 Domains ............................................................................... 1-2 Figure 1-2. CPX8216 Standard System Layout ...................................................... 1-3 Figure 1-3. CPX8216T H.110 System Layout ........................................................ 1-4 Figure 1-4. CPX8216 I/O Bus Connectivity ........................................................... 1-5 Figure 1-5. The CPX8216T H.110 Bus ........................................
List of Tables Table 2-1. CompactPCI Boards ............................................................................... 2-1 Table 2-2. USB 0 Connector J18 ............................................................................. 2-4 Table 2-3. USB 1 Connector J17 ............................................................................. 2-4 Table 2-4. 10BaseT/100BaseTx Connector J8 ........................................................ 2-5 Table 2-5. COM1 Connector J15 .........................
Table 5-13. PMC I/O Connector (J2) .................................................................... 5-14 Table 5-14. PMC I/O Connector (J21) .................................................................. 5-15 Table 5-15. Keyboard/Mouse P/S2 Connector Pin Assignments (J14) ................. 5-32 Table 5-16. Ethernet Connector Pin Assignments (J13 and J18) .......................... 5-33 Table 5-17. Serial Port Connector Pin Assignments (J21 and J10) ...................................................
Table 6-24. P5 Connector, CPU Transition Module Slots .................................... 6-27 Table 6-25. P3 Connector, CPU Transition Slots 7 and 9 ..................................... 6-28 Table 6-26. P5 Connector, HSC/Bridge (Slots 8 and 10) ...................................... 6-29 Table 6-27. P4 Connector, HSC/Bridge (Slots 8 and 10) ...................................... 6-29 Table 6-28. P3 Connector, HSC Slots 8 and 10 .................................................... 6-31 Table 6-29.
About this Manual This manual is directed at the person who needs detailed configuration and specification information for CompactPCI modules and system subassemblies of the CPX8000 series computer system. Included is an overview of the system architecture for the CPX8216 and CPX81216T systems. It also presents the correct strapping and pin-out information for the modules and subassemblies covered. This manual does not provide installation, removal, or use procedures.
Date Change Power distribution information added, see Power Distribution Panel on page 6-54. August 2001 Details about assigning chassis IDs on the CPX8216T system added. See Chassis ID for CPX8216T on page 1-13. Updated model numbers, see Systems Supported in this section. April 2001 Added cautions regarding hot swap software and hot swappable drives. July 2000 Updated pin assignment tables for connector P2 (HSC and CPU slots.) March 2000 DC Input voltage changed to -36Vdc to -72Vdc.
Systems Supported This information in this manual applies to the modules and subassemblies supported by the following systems: Model Number Description CPX8216SK24 CPX8216 Dual SCSI 466 MHz PowerPC Starter Kit, 256MB CPX8216TSK24 CPX8216T Dual EIDE 700 MHz Pentium Starter Kit, 512MB CPX8216SK25 CPX8216 Dual EIDE 700 MHz Pentium Starter Kit, 512MB CPX8216TSK25 CPX8216T Dual EIDE 466 MHz PowerPC Starter Kit, 256MB xxi
Overview This manual is divided into the following topics: ❏ Chapter 1, System Architecture ❏ Chapter 2, CPU Modules ❏ Chapter 3, CPX8540 Carrier Card ❏ Chapter 4, PMC Modules ❏ Chapter 5, Transition/Bridge Modules ❏ Chapter 6, Subassembly Reference ❏ Appendix A, Specifications ❏ Appendix B, Related Documentation Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better.
Conventions Used in This Manual The following typographical conventions are used in this document: bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files. italic is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.
1System Architecture 1 PICMG Compliance The CPX8216 system is designed to be fully compliant with the CompactPCI Hot Swap Specification developed by the PCI Industrial Computers Manufacturing Group (PICMG). With the proper software support and testing, it should be possible to integrate all proprietary and third-party I/O modules which are compatible with this specification.
1 System Architecture Alarm Controls Bus A Bus B Drive Bays Power Supply/Fan Trays Domain A Domain B Domain A/B Figure 1-1. CPX8216 Domains System Layout The CPX8216 is a 16-slot, high-availability CompactPCI system with two separate 6-slot CompactPCI I/O domains and the capability to contain redundant CPU modules and redundant Hot-Swap Controller (HSC) modules. It is also possible to configure the system as a simplex, high I/O system containing a single CPU-HSC pair.
CPX8216 Rear Card Locations Segment A CPU Transition Module Segment B HSC Segment B Transition Slots 1 2 3 4 5 Segment B CPU Transition Module 6 7 Segment A HSC 9 11 Segment B Transition Slots 12 13 14 15 Segment A I/O Slots Segment B I/O Slots Compact PCI Segment A Compact PCI Bus Segment B 16 Front Card Locations 2450 9812 Figure 1-2. CPX8216 Standard System Layout Each of the two independent I/O domains has its own system processor slot.
1 System Architecture CPX8216T (H.110) The CPX8216T H.110 system consists of two 8-slot subsystems, or domains, each with one slot for the host processor, one slot for the frontloaded HSC, and six slots for nonhost CompactPCI boards. Figure 1-3 on page 1-4 provides a diagram of this configuration.
The Hot Swap Controller/Bridge (HSC) Module Special Backplane PCI Interconnects C H P S U C C H P S U C A B B A I/O Domain A I/O Domain B I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S L O T S L O T S L O T S L O T S L O T S L O T S L O T S L O T S L O T S L O T S L O T S L O T Primary CompactPCI Buses Figure 1-4.
1 System Architecture ❏ Controlling power and resets to each system module through radial connections ❏ Monitoring and controlling CPU boards, nonhost boards, and peripherals, including power and fan sleds, board and system LEDs, and alarms Hot Swap Controller Each of the nonhost slots in the system can be controlled from either HSC. When an HSC has control over a domain it has control over the nonhost boards in that domain.
System Processor Configurations Subsequent to the default, the system software must determine the configuration of the system and then proceed to change it. System Processor Configurations The CPX8216 is a flexible system that allows for multiple configurations of processor control, I/O redundancy, and peripheral configurations. The following sections briefly touch on possible configurations.
1 System Architecture The simplex configuration is illustrated in the following figure. C P U H S C A A I/O Domain A I/O Domain B I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S L O T S L O T S L O T S L O T S L O T S L O T S L O T S L O T S L O T S L O T S L O T S L O T The Active/Passive Configuration In the active/passive configuration, one CPU manages all twelve I/O slots, much like in the simplex configuration.
The Active/Active or Load-Sharing Configuration The Active/Active or Load-Sharing Configuration In the load sharing configuration, each CPU manages six of the twelve I/O slots, much like a dual 8-slot system with the added benefit of one CPU being able to control all twelve I/O slots if the other CPU fails.
1 System Architecture I/O Configurations The CPX8216 contains two independent 8-slot CompactPCI buses. One slot in each bus is dedicated to a system processor, and another is needed for the HSC. This leaves six slots on each bus to support I/O devices or nonsystem processors. One possible configuration is to use the CPX8216 as a high I/O CompactPCI system with redundant CPUs. With this configuration, it is possible to run twelve independent I/O modules within a CPX8216 system.
Drive Modules The fans run at either high speed (default) or temperature controlled, which can be changed using the operating system software via the API. Drive Modules The CPX8216 contains four hot-swappable peripheral bays, all of which support both SCSI and EIDE protocols. Caution ! Caution The hot swapping of hard drives is supported when your system is configured with the appropriate software support for hot swap and when the drives are in a hot-swap drive carrier.
1 System Architecture CPU Complex Architecture The CPU complex in the CPX8216 contains two CPU modules and their corresponding Hot Swap Controller (HSC) modules. The figure below illustrates the architecture, including elements on the boards as well as local connections between the CPU modules and the PCI-to-PCI (P2P) connections to the local CompactPCI buses.
Switching Service to the Passive CPU Switching Service to the Passive CPU The switchover from one CPU to another is initiated by the passive CPU when there is an indication that there is something wrong with the active CPU--such as a failed heartbeat protocol. The passive side notifies the active side that it is about to begin a switchover process. If the active side agrees to the switchover, then the two sides coordinate the hand-off and no bus signals, clocks, or devices should be corrupted.
1 System Architecture H.110 Telephony Bus The CPX8216T supports an H.110 Computer Telephony Bus. The H.110 bus uses P4/J4 as defined in the PICMG specification for CompactPCI. P5 P4 H. 110 Bus P3 P2 CompactPCI Bus P1 System Slot HSC Slot 2557 9906 Figure 1-5. The CPX8216T H.110 Bus Board Insertion and Extraction Features The PICMG specification details software and hardware features, in order to support hot swapping of I/O boards.
Staged Pins Staged Pins The PICMG CompactPCI hot swap specification provides for three separate pin lengths in order to control the insertion and extraction voltages and to notify the system when boards are inserted or extracted. The longest pins, which include VCC pins and GND pins, are the first to mate during the insertion process and the last to break contact during extraction. These pins are used to supply power to pre-charge the PCI interface signals to a neutral state before they contact the bus.
1 System Architecture Hot Swap Control Status Register (CSR) The CPX8216 supports hot swap CompactPCI cards with the standard control status register defined by the PICMG Hot Swap Specification. The register is visible in PCI configuration space and provides hot swap control and status bits: INS and EXT. The INS signal is set when ENUM# is asserted by a board being inserted into the system. The EXT signal is asserted when ENUM# is asserted by an operator triggering the microswitch in the board handles.
Physical Connection Process (H0), it said to be in the P1/H0 state. Similarly, one can speak of a board being in the H2/S0 state. Physical Connection Process The physical connection process is the basic process of putting a board into a live system, or physically removing the board. The process includes two states: ❏ P0 - The board is physically separate from the system ❏ P1 - The board is fully seated, but not powered, and not active on the PCI bus. All pins are connected.
1 System Architecture Software Connection Process The software connection process includes the tasks needed to configure and load software. This process contains four states: ❏ S0 - The Software Connection Process has not been initiated. The board’s configuration space registers are accessible but not yet initialized. ❏ S1 - The board is configured by the system. The system has initialized the board’s PCI configuration space registers with I/O space, memory space, interrupts and PCI bus numbers.
Typical Insertion and Extraction Processes Typical Insertion and Extraction Processes Many of the steps in the insertion and extraction processes are automated by software. After the operator installs a board, it automatically advances to P1. The hardware connection process proceeds automatically and asserts the ENUM# signal to initiate the software connection process.
2CPU Modules 2 Overview This chapter provides reference information for the CompactPCI system controller/host CPU modules supported in the CPX8216 system. The correct jumper setting and pin-out information is provided for each module. Note The CPX750HA is sometimes identified as an MCP750HA in some chassis and firmware documentation, for packaging and ordering purposes, but both numbers apply to the same board.
CPU Modules The CPX750HA offers many standard features desirable in a CompactPCI computer system, such as: 2 ❏ PCI Bridge and Interrupt Controller ❏ ECC Memory Controller chipset ❏ 5MB to 9MB of linear FLASH memory ❏ IDE CompactFlash memory ❏ 16MB to 256MB of ECC-protected DRAM ❏ Interface to a CompactPCI bus ❏ Several I/O peripherals The I/O peripheral interfaces present on the onboard PCI bus include: ❏ One 10/100-BASE-T Ethernet interface ❏ One USB host controller ❏ One SA master/slave interface ❏ One
CPX750HA The base board supports PMC I/O for the front panel or through backplane connector J3 to a CPX750HATM transition module. J6 3 1 1 2 J11 J12 49 50 49 50 1 2 1 2 J13 J14 49 50 49 50 J5 1 2 PCI MEZZANINE CARD J4 2 1 10/1 00 BASE T J8 2 1 8 7 F1 J3 J9 9 5 F2 1 6 XU1 J15 COM 1 J10 F3 XU2 S1 RST J2 S2 ABT 190 DS3 DS4 189 DS1 DS2 BFL CPU CPCI CPI 1 J17 4 USB 1 J1 1 J18 4 USB 0 2 1 J19 190 189 2213 9804 http://www.motorola.
CPU Modules 2 Connectors and Jumper Settings The next sections provide pinout information and jumper settings for the CPX750HA board. Additional pinout assignments can be found in Chapters 3 through 6. Backplane Connectors (P5, P4, P3, P2, P1) Refer to the backplane reference section for the backplane connector pin assignments. Front USB Connectors (J17 and J18) Two USB Series A receptacles are located at the front panel of the CPX750HA board.
Connectors and Jumper Settings 2 Table 2-4. 10BaseT/100BaseTx Connector J8 1 TD+ 2 TD- 3 RD+ 4 AC Terminated 5 AC Terminated 6 RD- 7 AC Terminated 8 AC Terminated COM1 Connector (J15) A standard DB9 receptacle is located on the front panel of the CPX750HA to provide the interface to the COM1 serial port. These COM1 signals are also routed to J11 on the transition module. A terminal may be connected to J15 or J11 on the transition module but not both at the same time.
CPU Modules 2 Debug Connector (J19) A 190-pin connector (J19 on the CPX750HA base board) provides access to the processor bus (MPU bus) and some bridge/memory controller signals. It can be used for debugging purposes. The pin assignments are listed in the following table. Table 2-6.
Connectors and Jumper Settings Table 2-6.
CPU Modules Table 2-6.
Connectors and Jumper Settings Table 2-6.
CPU Modules 2 DRAM Mezzanine Connector (J10) A 190-pin connector (J10 on the CPX750HA base board) supplies the interface between the memory bus and the RAM300 DRAM mezzanine. The pin assignments are listed in the following table. Table 2-7.
Connectors and Jumper Settings Table 2-7.
CPU Modules Table 2-7.
Connectors and Jumper Settings Table 2-7.
CPU Modules 2 EIDE Compact FLASH Connector (J9) A 50-pin Compact FLASH card header connector provides the EIDE interface to the Compact FLASH Memory Card. The pin assignments for this connector are as follows: Table 2-8.
Connectors and Jumper Settings Table 2-8. EIDE Compact FLASH Connector J9 45 NO CONNECT NO CONNECT 46 47 DATA8 DATA9 48 49 DATA10 GND 50 2 Flash Bank Selection (J6) The CPX750HA base board has provision for 1MB of 16-bit flash memory. The RAM300 memory mezzanine accommodates 4MB or 8MB of additional 64-bit flash memory. The flash memory is organized in either one or two banks, each bank either 16- or 64-bits wide. Bank B contains the onboard debugger, PPCBug.
CPU Modules 2 CPV5350 The CPV5350 Single Board Computer (SBC) is a hot swap, CompactPCI (Compact Peripheral Communication Interface) compliant computer with high availability platform support. It is powered by a PICMG (PCI Industrial Computer Manufacturers Group) compatible Pentium® II Deschutes Mobile Module. The CPV5350’s 6U CompactPCI standard form factor (160mm x 233mm x 61mm), 4HP (.8 inch) is designed for installation into PICMG CompactPCI-compliant backplanes.
CPV5350 2 Video V I D E O COM 1 1 COM 2 2 Ethernet 1 Ethernet 2 USB 1 E T H E R N E T 2 Keyboard/Mouse RESET Indicator Lights RESET ALRM SPKR HDD PWR CPV5350 http://www.motorola.
CPU Modules 2 Connectors The next table lists the connectors available to support devices on the CPV5350. Figure 2-1 on page 2-19 shows the location of the connectors described in the table. Table 2-9.
Transition Module 2 J5 J3 J4 J1 J2 U50 U34 U35 U30 U31 U38 8 2 1 J17 J20 1 U25 1 2 BT1 2475 9901 J12 U26 U55 J21 U11 T1 U62 T2 2 J23 J24 J25 J13 J6 J14 J51 CR2 CR4 1 J50 CRI CR3 Figure 2-1. CPV5350 Component Side View Transition Module The CPV5350TM80 transition module provides backplane I/O through the J3 and J5 connectors on the CPV5350 controller module.
CPU Modules 2 DRAM Memory Configuration The CPV5350 has one 168-pin DIMM site for memory expansion. The DIMM sites accept industry standard PC100-compliant DIMM modules (8, 16, 32, 64, 128, or 256MB) with or without ECC. You can use either registered or unbuffered memory modules. Keyboard/Mouse PS2 Connector The keyboard/mouse connector (J50) uses a 6-pin, female PS/2 connector. Table 2-10.
Ethernet Connectors Ethernet Connectors 2 Ethernet 1 (J13) and Ethernet 2 (J6) use standard RJ-45 connectors. Table 2-11. Ethernet Connector Pin Assignments (J13 and J6) Pin Number Signal Mnemonic Signal Description 1 TX+ Differential transmit lines 2 TX- Differential transmit lines 3 RX+ Differential receive lines 4 -- -- 5 -- -- 6 RX- Differential receive lines 7 -- -- 8 -- -- Universal Serial Bus (USB) Connector USB Port 1 and Port 2 (J14) use a 2 x 4 pin USB connector.
CPU Modules 2 Serial Port Connectors COM 1 (Serial Port 1) (J24) and COM 2 (Serial Port 2) (J25) use 2 x 9-pin D-sub connectors. Table 2-13.
Video Connector Table 2-14.
3CPX8540 Carrier Card 3 Overview This chapter provides reference information for the CPX8540 carrier card. The CPV8540 is a 64-bit, 6U, single-width (4HP) CompactPCI® card that provides front access to PMC modules with both front and rear I/O connectivity. Rear I/O connections via J3 and J5 allow its use in both standard CompactPCI backplanes and CompactPCI backplanes with the H.110 CT bus. The correct jumper settings and pin-out information is provided for each connector on the carrier card.
CPX8540 Carrier Card The CPX8540 reports itself to the system as a bridge chip with the PMC functions behind it. The following two figures provide overviews of the card. 3 J5 PMC2 J3 PMC1 J2 Bridge J1 Figure 3-1.
CPX8540 Carrier Card 3 J22 J21 J24 J23 J12 J11 J14 J13 Single Width PMC Module Figure 3-2. Installing a PMC Module http://www.motorola.
CPX8540 Carrier Card Connector Pinouts The tables in this section provide the connector pinout information for the rear connectors on the carrier card. 3 Table 3-1. CPCI J3 I/O Connector Pinout ROW A ROW B ROW C ROW D ROW E 14 +3.3V +3.3V +3.
Connector Pinouts Table 3-2.
CPX8540 Carrier Card Table 3-3.
Connector Pinouts Table 3-4. PCI 32-bit Interface Connector P12/J12, P22/J22 Pin# Signal Name Signal Name Pin # 1 +12V TRST# 2 3 TMS TDO 4 5 TDI GND 6 7 GND PCI-RSVD* 8 9 PCI-RSVD* PCI-RSVD* 10 11 BUSMODE2# +3.3V 12 13 RST# BUSMODE3# 14 15 +3.3V BUSMODE4# 16 17 PCI-RSVD* GND 18 19 AD[30] AD[29] 20 21 GND AD[26] 22 23 AD[24] +3.3V 24 25 IDSEL AD[23] 26 27 +3.
CPX8540 Carrier Card Table 3-4. PCI 32-bit Interface Connector P12/J12, P22/J22 (continued) 3 Pin# Signal Name Signal Name Pin # 51 AD[07] PMC-RSVD 52 53 +3.3V PMC-RSVD 54 55 PMC-RSVD GND 56 57 PMC-RSVD PMC-RSVD 58 59 GND PMC-RSVD 60 61 ACK64# +3.3V 62 63 GND PMC-RSVD 64 Table 3-5.
Connector Pinouts Table 3-5. PCI 64 bit PCI extension on PMC Connector J13, J23 Pin# Signal Name Signal Name Pin # 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 V(I/O) AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 V(I/O) AD32 58 59 - - 60 61 - GND 62 63 GND - 64 3 Table 3-6.
4PMC Modules 4 Overview This chapter provides reference information for the PMC module supported in the CPX8216 system. SCSI-2 Controller PMC The SCSI-2 controller provides fast and wide, single-ended, SCSI-2 (Small Computer System Interface-2) high throughput connectivity for host carrier boards equipped with PMC (PCI Mezzanine Card) connections. The PMC adapter is a plug-and-play device with systems that are compliant with the PCI Local Bus Specification (revision 2.0).
PMC Modules The following figure shows the PMC150 component layout and front panel.
Switch Settings Switch Settings Use this table as a guideline for configuring the 6-position dip switch on your PMC. Table 4-1. PMC Switch Settings 4 Switch On Function Off Function Default 1 Use INTA No Use INTA On 2 Use INTB No Use INTB Off 3 Use INTC No Use INTC Off 4 Use INTD No Use INTD Off 5 TERM Enable TERM Disable On 6 Little Endian Big Endian On Configure the Big/Little endian mode to your appropriate application for proper software operation.
PMC Modules Connector Pin Assignments The table below provides the connector pin assignments for the SCSI connector on the PMC adapter. The connector uses a 68-pin Euro-style SCSI cable, either shielded for external or internal cabinet applications or non-shielded for internal cabinet applications only. For rear I/O, a 64-pin conductor cable is used. The pin assignments are also provided in the following table. 4 Table 4-2.
Connector Pin Assignments Table 4-2. PMC Pin Assignments (continued) Signal name 68-Pin Connector Number 64-Pin Conductor Cable Number Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground 24 25 26 27 28 29 30 31 32 33 34 43 45 47 49 51 53 55 57 59 61 63 http://www.motorola.
5Transition/Bridge Modules 5 Overview This chapter provides reference information for the various transition and bridge modules supported in the CPX8216 system. The correct jumper setting and pin-out information is provided for each module. Note The CPX750HATM is also used with the MCP750HA in some chassis configurations. Your system may not contain all boards listed in this chapter, or it may contain third-party boards that are not listed in this chapter.
Transition/Bridge Modules The CPX750HATM transition module includes: ❏ Industry-standard connectors for these interfaces: – Two asynchronous RJ-45 serial ports (DTE) – Two asynchronous/synchronous HD-26 serial ports, labeled Serial 3 and Serial 4 on the face plate, which can be configured for EIA-232-D, EIA-530, V.35, or X.
13 26 J24 J1 SERIAL 4 1 2 1 14 59 60 13 26 J6 1 2 SERIAL 3 J2 1 14 J23 17 34 64 63 59 60 J7 PARALLEL 2 1 1 18 J9 1 J10 1 2 3 1 J8 3 2 1 7 1 2 8 COM 2 J21 J11 J14 J13 J4 7 8 COM 1 J3 2 1 2 1 J16 KB/MS 64 63 1 1 4 J19 4 J17 J18 J15 J5 USB 1 http://www.motorola.com/computer/literature USB 0 2 1 34 33 40 39 2214 9804 Serial Ports 3 and 4 Default Configuration 5 Figure 5-1.
Transition/Bridge Modules Serial Port Interface Jumper (J8 and J9) J8 (for serial port 3) and J9 (for serial port 4) set the serial ports to either DTE or DCE communication. For more information about configuring the serial port, see Installing the Serial Interface Modules on page 5-16. 1 5 2 3 DTE 1 2 3 DCE 11650 9610 Figure 5-2.
Connectors assignments for J5 are as follows (the outer row F is assigned and used as ground pins but is not shown in the table): Table 5-2 and Table 5-3 provide the pin assignments and signal mnemonics for connectors J3 and J5 (J4 is not shown) Table 5-2.
Transition/Bridge Modules Table 5-3.
Connectors for these ports are tied to chassis ground. The pin assignments and signal mnemonics for these connectors are listed in the next table. Table 5-4. COM1 (J11) and COM2 (J10) Pin Signal 1 DCD 2 RTS 3 GND 4 TXD 5 RXD 6 GND 7 CTS 8 DTR 5 Asynchronous/Synchronous Serial Port Connectors (J6 and J24) The interface for the asynchronous/synchronous serial ports 3 and 4 is provided by two HD-26 connectors, J6 and J24. The connector shields for these ports are tied to chassis ground.
Transition/Bridge Modules Table 5-5. Serial Port 3 (J6) (continued) 5 Pin Signal Signal Pin 6 DSR3 SP3_P19 19 7 GND DTR3 20 8 DCD3 RLB3 21 9 SP3_P9 RI3 22 10 SP3_P10 SP3_P23 23 11 SP3_P11 TXCO3 24 12 SP3_P12 TM3 25 13 SP3_P13 SP3_P26 26 Table 5-6.
Connectors Parallel I/O Port Connector (J7) The interface for the parallel port is a standard IEEE P1284-C, 36-pin connector, J7. The functionality of each signal depends on the mode of operation of this bidirectional Parallel Peripheral Interface. Refer to the IEEE P1284 D2.00 Standard for a complete description of each signal function. The connector shield is tied to chassis ground. The pin assignments and signal mnemonics for this connector are listed in the next table. Table 5-7.
Transition/Bridge Modules Keyboard/Mouse Connector (J16) The Keyboard/Mouse interface is provided by a 6-pin circular DIN connector. To use the keyboard function only, a keyboard may be connected directly to this connector. To use both the keyboard and the mouse functions, use the Y-adapter cable provided with the CPX750HATM. Refer to the following table for pin assignments. Table 5-8.
Connectors EIDE Connector (J15) The CPX750HATM provides a 40-pin header (J15) to interface to the CPX750 secondary EIDE port. The pin assignments and signal mnemonics for this connector are listed in the next table. Table 5-9.
Transition/Bridge Modules Floppy Port Connector (J17) The CPX750HATM provides a 34-pin header (J17) to interface to a floppy disk drive. The pin assignments and signal mnemonics for this connector are listed in the next table. Table 5-10.
Connectors must not draw more than 200mA. The pin assignments are listed in the following table. Table 5-11. +5Vdc Power Connector (J14) Pin Signal 1 +5Vdc 2 GND 3 GND 4 No Connect 5 Speaker Output Connector (J13) The 2-pin header (J13) provides connection to an external speaker from the CPX750 PCB Counter 2 output. The speaker driver, located on the CPX750 PCB, consists of a 500 mA (max) current sink transistor in series with a 33 ohm resistor.
Transition/Bridge Modules PMC I/O Connectors The PMC I/O connectors consist of two 64-pin header connectors J2 and J21. The pin assignments and signal mnemonics for these connectors are listed below. Table 5-13.
Connectors Table 5-13. PMC I/O Connector (J2) (continued) Pin Signal Signal Pin 43 GND PMCIO22 44 45 GND PMCIO23 46 47 GND PMCIO24 48 49 GND PMCIO25 50 51 GND PMCIO26 52 53 GND PMCIO27 54 55 GND PMCIO28 56 57 GND PMCIO29 58 59 GND PMCIO30 60 61 GND PMCIO31 62 63 GND PMCIO32 64 5 Table 5-14.
Transition/Bridge Modules Table 5-14.
Installing the Serial Interface Modules Prior to installing the SIMs, set the jumpers on header J8 (for Serial Port 3) and header J9 (for Serial Port 4) for either DCE or DTE. Set the jumper to position 1-2 if the SIM is for a DTE interface. Set the jumper to position 2-3 if the SIM is for a DCE interface. 1 2 3 1 2 3 DCE DTE 5 You must set the jumpers and install the SIMs prior to installing the CPX750HATM transition module in the system chassis.
Transition/Bridge Modules 3. Gently press the top of the SIM to seat it on the transition module SIM connector. If the SIM does not seat with gentle pressure, re-check the alignment of the connectors. Note Do not force the SIM onto the transition module. 4. Secure the SIM to the transition module standoffs with the two Phillips-head screws provided. Do not over tighten the screws.
Port Configuration Diagrams 9 1 6 COM1 8 (Front J15 Panel) 2 4 7 3 5 5 TXD SOUT1 4 RTS RTS1# 2 DTR DTR1# 8 RXD SIN1 CTS CTS1# 5 7 COM1 (J11) DSR1# DCD DCD1# RI1# 1 3 GND PC87307 J5 TXD SOUT2 6 4 RTS RTS2# 2 DTR DTR2# RXD SIN2 CTS CTS2# 8 5 7 COM2 (J10) DSR2# DCD DCD2 RI2# 1 3 GND 6 CPX750 CPX750HATM Transition Module 2105 9710 Figure 5-3. DTE Port Configuration (COM1 and COM2) http://www.motorola.
Transition/Bridge Modules Asynchronous/Synchronous Serial Ports The asynchronous/synchronous serial port (Port 3 and Port 4) interface configuration diagrams are on the following pages.
Port Configuration Diagrams Z85230 SCC DB25 RXD TXD CTS# RTS# TXD RXD RTS# CTS# DTR# DCD# TRXC RTXC J3/MX 3 TXC 2 1 RXC# J8, J9 ETXC 3 5 2 4 5 20 15 17 24 Z8536 CIO DCD# DTR# TM# LLB# RI# RLB# RL RI# 18 GND CPX750 CPX750HATM Transition Module 6 21 LL TM# 25 22 DSR# DSR# 8 7 EIA-232-D DCE SIM 2106 971 Figure 5-4. EIA-232-D DCE Port Configuration (Ports 3 and 4) http://www.motorola.
Transition/Bridge Modules Z85230 SCC DB25 TXD TXD RTS# RTS# RXD RXD CTS# CTS# 5 DCD# DCD# TRXC RTXC J3/MX 2 4 3 5 8 3 ETXC 24 2 1 TXC# J8, J9 RXC 15 17 Z8536 CIO DTR DTR# LL LLB# 18 RL RLB# 21 DSR# DSR# RI# RI# GND# CPX750 CPX750HATM Transition Module 6 22 TM# TM# 20 25 7 EIA-232-D DTE SIM 2107 971 Figure 5-5.
Port Configuration Diagrams Z85230 SCC DB25 TXD RXDB RXDA RTS_ CTSB CTSA TXDB RXD + - CTS_ + + - 14 2 RTSB RTSA 19 TXCB TXCA 2 1 TRXC RXCB RXCA J8, J9 RTXC ETXCB ETXCA + - J3/MX DCDB DCDA Z8536 CIO DTR_ TM LL_ + - RI_ + - TM_ -V -V RL LL GND CPX750 CPX750HATM Transition Module 12 15 9 17 11 24 10 8 26 DSRB DSRA DSR_ 23 20 25 RI RL_ 5 4 DTRA 3 13 5 TXDA DTRB DCD_ 16 3 22 6 21 18 7 EIA-530-D DCE SIM 2108 9710 Figure 5-6.
Transition/Bridge Modules Z85230 SCC DB25 TXD TXDB TXDA RTS_ RTSB RTSA 19 4 RXDB 5 RXD + - CTS_ + - DCD_ + - RXDA CTSB CTSA DTRB DTRA ETXCB ETXCA 3 2 1 TRXC + - J8, J9 RTXC TXCB TXCA RXCB RTXCA + - J3/MX DTRB DTRA Z8536 CIO DTR_ LL LL_ + - RI_ + - TM_ -V -V (R) TM GND CPX750 CPX750HATM Transition Module 13 5 10 20 8 11 15 24 12 17 15 9 17 23 20 21 DSRB DSRA DSR_ 16 3 18 RL RL_ 14 2 22 6 26 25 7 EIA-530-D DTE SIM 2109 9710 Figure 5-7.
Port Configuration Diagrams Z85230 SCC DB25 Term TXD RXDB RXDA CTS RTS_ Term + - RXD TXDB TXDA RTS DCD_ DTR CTS_ Term 3 2 1 TRXC J3/MX Term J8, J9 Term + - RTXC TXCB TXCA RXCB RXCA ETXCB ETXCA 16 3 5 14 2 4 5 20 12 15 9 17 11 24 Z8536 CIO DCD 8 DTR_ LL_ RL_ TM 25 RI 22 DSR DSR_ RI_ TM_ 6 RL 21 LL 18 GND 7 V.35-DCE SIM CPX750 CPX750HATM Transition Module Term = V.35 Termination Network 2110 971 Figure 5-8. V.35-DCE Port Configuration (Ports 3 and 4) http://www.
Transition/Bridge Modules Z85230 SCC DB25 Term TXD RTS RTS_ Term + - RXD DCD DCD_ Term 3 2 1 TRXC Term + - J8, J9 Term + - RTXC Z8536 CIO RXDB RXDA CTS CTS_ 5 TXDB TXDA J3/MX RXCB RXCA 9 17 RI RI_ TM TM_ GND CPX750 CPX750HATM Transition Module 8 12 15 17 DSR DSR_ 5 TXCB TXCA RL RL_ 16 3 11 24 15 LL LL_ 4 ETXCB ETXCA DTR DTR_ 14 2 20 18 21 6 22 25 7 V.35-DCE SIM Term = V.35 Termination Network 2111 971 Figure 5-9. V.
Port Configuration Diagrams Z85230 SCC DB25 RXDB RXDA TXD 16 3 RTS_ RXD + - CTS_ + - TXDB TXDA CTRLB CTRLA 14 2 11 24 5 DCD_ 3 2 1 TRXC J3/MX SETB SETA 12 15 17 +V J8, J9 RTXC Z8536 CIO INDB INDA DTR_ LL_ NC RL_ NC 9 17 DSR_ RI_ +V TM_ +V GND 7 X.21 DCE SIM CPX750 CPX750HATM Transition Module 2112 971 Figure 5-10. X.21-DCE Port Configuration (Ports 3 and 4) http://www.motorola.
Transition/Bridge Modules Z85230 SCC DB25 TXDB TXDA TXD CTRLB CTRLA RTS_ RXDB + - RXD 14 2 11 24 RXDA 16 3 INDB INDLA 9 17 SETB SETA 12 15 CTS_ 5 + - DCD_ 3 2 1 TRXC J3/MX NC + - J8, J9 RTXC Z8536 CIO DTR_ LL_ NC RL_ NC DSR_ RI_ +V TM_ +V GND 7 X.21 DTE SIM CPX750 CPX750HATM Transition Module Figure 5-11. X.
CPV5350TM80 Transition Module CPV5350TM80 Transition Module The CPV5350TM80 transition module provides rear I/O connectivity for the CPV5350 CPU controller module.
Transition/Bridge Modules The next figure shows the CPV5350TM80 front panel and on-board connectors and jumpers.
Connectors Connectors The following table lists the connectors available to support devices on the CPV5350. The figure on the preceding page shows the location of the connectors described in the table.
Transition/Bridge Modules Keyboard/Mouse PS2 Connector The keyboard/mouse connector (J14) uses a 6-pin, female PS/2 connector. Table 5-15. Keyboard/Mouse P/S2 Connector Pin Assignments (J14) 5 Pin Signal Mnemonic Signal Description 1 KBDDAT Keyboard Data 2 AUXDAT Auxiliary Data 3 GND Ground 4 KBDVCC Keyboard Power (current limited to .75 Amp) 5 KBDCLK Keyboard Clock 6 AUXCLK Auxiliary Clock 7 CGND Common Ground 6 5 4 3 2 1 7 2489 9902 Figure 5-12.
Connectors Ethernet Connectors Ethernet 1 (J13) and Ethernet 2 (J18) use standard RJ-45 connectors. Table 5-16. Ethernet Connector Pin Assignments (J13 and J18) Pin Signal Mnemonic Signal Description 1 TX+ Differential transmit lines 2 TX- Differential transmit lines 3 RX+ Differential receive lines 4 -- -- 5 -- -- 6 RX- Differential receive lines 7 -- -- 8 -- -- 5 Serial Port Connectors COM 1 (Serial Port 1, J21) and COM 2 (Serial Port 2, J10) use 2 x 9-pin D-sub connectors.
Transition/Bridge Modules Table 5-17. Serial Port Connector Pin Assignments (J21 and J10) (continued) 5 Pin Signal Mnemonic Signal Description 6 DSR- Data set is ready to establish a communication link 7 RTS- Indicates to data set that UART is ready to exchange data 8 CTS- Data set is ready to exchange data 9 RI- Modem has received a telephone ringing signal Video Connector The video connector (J16) uses a 15-pin high density D-sub connector. Table 5-18.
Connectors Table 5-18. Video Connector Pin Assignments (J16) Pin Signal Mnemonic Signal Description 12 DDCDAT Display data channel data signal for DDC2 support 13 HSYNC Horizontal synchronization 14 VSYNC Vertical synchronization 15 DDCCLK Display data channel clock signal for DDC2 support Parallel Port Connector (J20) The parallel port (J20) uses a 25-pin, D-sub connector. Table 5-19.
Transition/Bridge Modules Table 5-19. Parallel Connector Pin Assignments (J20) 5 Pin Signal Mnemonic Signal Description 15 ERR- Set low when an error is detected 16 INIT- Initializes the printer 17 SLIN- Selects the printer 18 GND Ground 19 GND Ground 20 GND Ground 21 GND Ground 22 GND Ground 23 GND Ground 24 GND Ground 25 GND Ground EIDE Headers (J5) Table 5-20.
Connectors Table 5-20.
Transition/Bridge Modules Table 5-20.
Connectors Table 5-21.
Transition/Bridge Modules Table 5-21.
Connectors Table 5-22. Keyboard/Mouse/Power LED Header (J6) Pin Assignments (continued) Pin Signal Mnemonic Signal Description Pin Signal Mnemonic Signal Description 5 GND Ground 6 AUXDAT Data line for mouse 7 - - 8 GND Ground 9 GND Ground 10 KBDVCC Keyboard power (.75A) 11 - - 12 AUXCLK Clock for mouse USB Headers (J12 and J19) Table 5-23.
Transition/Bridge Modules SM Bus and LM78 Header (J1) Table 5-24.
Connectors Fan Tachometer Headers (J3 and J4) Refer to the next table for pin assignments and signal descriptions for the Fan Tachometer headers (J3 and J4) on the CPV5350 Transition Module. Table 5-25. Fan Tachometer Header (J3 and J4) Pin Assignments Pin Signal Mnemonic Signal Description 1 VCC SM bus power 2 TACH Tachometer input for fan 3 GND Ground 4 +12V 12 volt power 5 Indicator LED/Miscellaneous Header (J2) Table 5-26.
Transition/Bridge Modules Table 5-26. Indicator LED/Miscellaneous Header (J2) Pin Assignments (continued) 5 5-44 Pin Signal Mnemonic Signal Description Pin Signal Mnemonic Signal Description 5 VCC +5V power (limited to .75A total) 6 EIDE_LED Secondary channel EIDE activity LED 7 VCC +5V power (limited to .75A total) 8 - - 9 VCC +5V power (limited to .
6Subassembly Reference 6 Chapter Overview This chapter provides reference information for the various subassemblies of the CPX8216 and CPX8216T system. It covers only those items associated with the system enclosure. For information about CompactPCI board components, refer to the appropriate chapter in this manual. The following table lists the system components covered in this chapter: Table 6-1.
Subassembly Reference Parts of the System Front Peripheral Bay Alarm Board SYSTEM STATUS 1 6 2 SYSTEM IN SERVICE 3 4 COMPONENT OUT OF SERVICE 5 6 TELCO STATUS TBD 7 8 9 MINOR 10 MAJOR 11 ALARM CONNECTION CRITICAL 12 13 14 15 1 16 CompactPCI Cardcage 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 4 16 ESD BONDING POINT Cable Pass-Thru OUT OF SERVICE IN SERVICE 1 OUT OF SERVICE IN SERVICE 2 OUT OF SERVICE IN SERVICE 3 Power Supplies Figure 6-1.
Parts of the System Floppy Housing Transition Module Cage ESD BONDING POINT 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 6 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 l 0 Power Distribution Panel Figure 6-2. CPX8216 Rear View http://www.motorola.
6-4 I/O Slot (Black) 2 3 None I/O Trns (Black) I/O Trns (Black) I/O Trns (Black) I/O Trns (Black) I/O Trns (Black) H.
Backplane Reference Backplane Reference The backplane provides the interconnect for all 16-slot, 6U CompactPCI bus, N+1 power distribution, alarm signal distribution, and IDE device signal/status distribution. All sixteen CompactPCI slots accept any standard 6U CompactPCI board or transition module which meet IEEE 1101.1, IEEE 1101.10, and IEEE1101.11 specifications. The slots are 64-bit, 33 MHz PCI compliant.
Subassembly Reference Power Supply Connectors (PS1, PS2, PS3) The three power supply connectors, PS1, PS2, and PS3, are located on the primary side of the backplane. Note The shaded pins are high current pins. Present[n]# is grounded on the backplane. Table 6-2. PS1, PS2, and PS3 Pin Assignments 6 6-6 Pin Signal Signal Pin 1 GND Present[n]# 16 2 GND -12Vdc 17 3 +3.3Vdc A_DOUT# 18 4 +3.3Vdc PS[n]_DIN# 19 5 +S5Vdc -12Vdc 20 6 -S5Vdc N/C 21 7 +5_Share N/C 22 8 +S3.
H.110 Power Connector (CPX8216T Only) Table 6-3. Fan Module Pin Assignments Pin Signal Color Pin Signal 1 N/C 2 +12V_System In 3 Color 6 N/C Grey 7 +12V_System Out Brown +12V_Fan Red 8 +12V_Fan_Rtn Black 4 Tach Blue 9 Speed Ctl Yellow 5 N/C 10 N/C 6 H.110 Power Connector (CPX8216T Only) H.110 BAT and Ring voltages are supplied to the backplane directly from the Power Distribution Panel. This section applies to CPX8216T systems only. Table 6-4. H.
Subassembly Reference Alarm Interface Connector (ALARM) The alarm interface connector is located on the secondary side of the backplane. Alarm signals are routed through the backplane to the ALARM connector. The alarm board attaches to this connector by ribbon cable. Table 6-5.
IDE Drive Connectors (IDEA and IDEB) Table 6-6.
Subassembly Reference Table 6-7.
Peripheral Signal Connectors (SIG1, SIG2, SIG3, SIG4) Table 6-8. PWR1, PWR2, PWR3, PWR4 Pin Assignments Pin Signal 3 Ground 4 +12 Volts Peripheral Signal Connectors (SIG1, SIG2, SIG3, SIG4) The four peripheral signal connectors are located on the secondary side of the CPX8216 backplane. All four connectors have the same pin-out. The connectors map to different locations in the Hot Swap Controller peripheral registers, and cannot be used interchangeably. Table 6-9.
Subassembly Reference Connectors P1 and P2 carry the CompactPCI bus (bus A for slots 1-6, bus B for slots 11-16). Table 6-10. P5 Connector, I/O Slots 1-6 and 11-16 (User I/O) POS Row Z Row A Row B Row C Row D Row E Row F 22-1 GND I/O I/O I/O I/O I/O GND All I/O pins pass through the backplane to the transition module, they do not make any connection to the backplane. 6 Table 6-11.
Primary (Front) Side I/O Connectors (Slots 1-6 and 11-16) Table 6-13.
Subassembly Reference Table 6-13.
Primary (Front) Side I/O Connectors (Slots 1-6 and 11-16) Table 6-14. P1 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus) POS Row Z Row A Row B Row C Row D Row E Row F 23 GND 3.3V _AD[4] _AD[3] 5V _AD[2] GND 22 GND _AD[7] GND 3.3V _AD[6] _AD[5] GND 21 GND 3.3V _AD[9] _AD[8] _M66EN _C/BE[0]# GND 20 GND _AD[12] GND VIO _AD[11] _AD[10] GND 19 GND 3.3V _AD[15] _AD[14] GND _AD[13] GND 18 GND _SERR# GND 3.3V _PAR _C/BE[1] GND 17 GND 3.
Subassembly Reference Table 6-14. P1 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus) POS Row Z Row A Row B Row C Row D Row E Row F 4 GND _BRSVP1A 4 HLTY[N]# VIO _INTP _INTS GND 3 GND _INTA# _INTB# _INTC# 5V _INTD# GND 2 GND TCK 5V TMS TDO TDI GND 1 GND 5V -12V TRST# +12V 5V GND Signals beginning with an underscore (_) are prefixed with the bus name: 6 *For boards located in slots 1-6 (Domain A), the signal name is prefixed with PCI_A (for example, PCI_A_AD[49]).
Primary (Front) Side CPU Slot Connectors (7 and 9) Primary (Front) Side CPU Slot Connectors (7 and 9) Table 6-15.
Subassembly Reference Table 6-15.
Primary (Front) Side CPU Slot Connectors (7 and 9) Table 6-16. P4 Connector, CPU Slots 7 and 9 (continued) POS Row Z Row A Row B Row C Row D Row E Row F 20 GND _AD57 _+3.3 _AD56 _AD55 _AD54 GND 19 GND _AD61 _AD60 _AD59 GND _AD58 GND 18 GND _CBE4# _+3.3 _PAR64 _AD63 _AD62 GND 17 GND _REQ64# _CBE7# _CBE6# GND _CBE5# GND 16 GND _AD2 _+3.
Subassembly Reference Table 6-17. P3 Connector, CPU Slots 7 and 9 6 POS Row Z Row A Row B Row C Row D Row E Row F 19 GND I/O I/O I/O I/O I/O GND 18 GND HS_REQ_ I/O I/O I/O I/O GND 17 GND HS_GNT_ I/O I/O I/O I/O GND 16 GND HS_FLT_ I/O I/O I/O I/O GND 15 GND HS_EJ_ I/O I/O I/O I/O GND 14-1 GND I/O I/O I/O I/O I/O GND All I/O pins pass through the backplane to the transition module; they do not make any connection to the backplane.
Primary (Front) Side CPU Slot Connectors (7 and 9) Table 6-18.
Subassembly Reference Table 6-19.
Primary (Front) Side CPU Slot Connectors (7 and 9) Table 6-19. P2 Connector, CPU Slot 9 (Domain B) (continued) POS Row Z Row A Row B Row C Row D Row E Row F 3 GND CLK14 GND GNT13# REQ14# GNT14# GND 2 GND CLK12 CLK13 _SYSEN# GNT12# REQ13# GND 1 GND CLK11 GND REQ11# GNT11# REQ12# GND Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example, PCI_B_AD[49]). Signals RSV are not connected. Signals beginning with _BRSV are bussed, but not used.
Subassembly Reference Table 6-20. P1 Connector, CPU Slots 7 and 9 (continued) 6 POS Row Z Row A Row B Row C Row D Row E Row F 18 GND _SERR# GND 3.3V _PAR _C/BE[1] GND 17 GND 3.3V _SDONE _SBO# GND _PERR# GND 16 GND _DEVSE L# GND VIO _STOP# _LOCK# GND 15 GND 3.3V _FRAME # _IRDY# BD_SEL [n]# _TRDY# GND 14-12 KEY AREA 11 GND _AD[18} _AD[17] _AD[16] GND _C/BE[2] # GND 10 GND _AD[21] GND 3.
Primary (Front) Side CPU Slot Connectors (7 and 9) Table 6-20. P1 Connector, CPU Slots 7 and 9 (continued) POS Row Z Row A Row B Row C Row D Row E Row F 2 GND TCK 5V TMS TDO TDI GND 1 GND 5V -12V TRST# +12V 5V GND Signals beginning with an underscore (_) are prefixed with the bus name: *For boards located in slot 7 (Domain A), the signal name is prefixed with PCI_A (for example, PCI_A_AD[49]).
Subassembly Reference Secondary (Rear) Side I/O Connectors Note I/O slot connectors P2 and P1 do not connect through to the transition module. Table 6-21. P5 Connector, I/O Slots 1-6 and 11-16 (User I/O) POS Row Z Row A Row B Row C Row D Row E Row F 22-1 GND I/O I/O I/O I/O I/O GND All I/O pins pass through the backplane to the transition module, they do not make any connection to the backplane. 6 Table 6-22.
CPU Transition Module Connectors (Transition Slots 7 and 9) CPU Transition Module Connectors (Transition Slots 7 and 9) Note CPU transition module connectors P4, P2, and P1 are not connected. Table 6-24.
Subassembly Reference Table 6-24. P5 Connector, CPU Transition Module Slots 6 POS Row Z Row A Row B Row C Row D Row E Row F 6 GND RSVD I/O RSVD RSVD RSVD GND 5 GND RSVD RSVD RSVD RSVD RSVD GND 4 GND RSVD RSVD I/O RSVD RSVD GND 3 GND RSVD RSVD RSVD RSVD RSVD GND 2 GND RSVD RSVD RSVD RSVD RSVD GND 1 GND I/O RSVD RSVD RSVD RSVD GND All I/O pins pass through the backplane; they do not make any connection to the backplane.
Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10) Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10) The Hot Swap Controller/Bridge for Domain A resides in transition module slot 10. The Hot Swap Controller/Bridge for Domain B resides in transition module slot 8. Table 6-26. P5 Connector, HSC/Bridge (Slots 8 and 10) POS Row Z Row A Row B Row C Row D Row E Row F 22-1 GND RSVD RSVD RSVD RSVD RSVD GND 6 Connector P5 is reserved for future use. Table 6-27.
Subassembly Reference Table 6-27. P4 Connector, HSC/Bridge (Slots 8 and 10) (continued) 6 POS Row Z Row A Row B Row C Row D Row E Row F 17 GND _REQ64# _CBE7# _CBE6# _GND _CBE5# GND 16 GND _AD2 _+3.
Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10) Table 6-28.
Subassembly Reference Table 6-28. P3 Connector, HSC Slots 8 and 10 (continued) POS Row Z Row A Row B Row C Row D Row E Row F 5 GND BD_SEL5# HLTY5# BD_SEL7# HLTY15# BD_SEL15 # GND 4 GND BD_SEL4# HLTY4# RST10# HLTY14# BD_SEL14 # GND 3 GND BD_SEL3# HLTY3# RST9# HLTY13# BD_SEL13 # GND 2 GND BD_SEL2# HLTY2# RST8# HLTY12# BD_SEL12 # GND 1 GND BD_SEL1# HLTY1# RST7# HLTY11# BD_SEL11 # GND 6 A/B# GND Domain B (slot 8).
Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10) Table 6-29.
Subassembly Reference Table 6-30.
Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10) Table 6-30. P2 Connector, HSC Slot 8 (continued) POS Row Z Row A Row B Row C Row D Row E Row F 2 GND CLK12 CLK13 _SYSEN# GNT12# REQ13# GND 1 GND CLK11 GND REQ11# GNT11# REQ12# GND Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example, PCI_A_AD[49]). Signals in parentheses are not used. Table 6-31.
Subassembly Reference Table 6-31. P1 Connector, HSC Slots 8 and 10 (continued) 6 POS Row Z Row A Row B Row C Row D Row E Row F 8 GND _AD[26] GND VIO _AD[25] _AD[24] GND 7 GND _AD[30] _AD[29] _AD[28] GND _AD[27] GND 6 GND REQ[N]# GND 3.
H.110 Bus Connectors—CPX8216T System Only H.110 Bus Connectors—CPX8216T System Only On each domain, the H.110 bus passes through connector P4 across the I/O and HSC slots. It does not connect to the CPU slot (see Figure 6-6). P5 P4 6 H. 110 Bus P3 P2 CompactPCI Bus P1 System Slot HSC Slot 2557 9906 Figure 6-6. The CPX8216T H.110 Bus http://www.motorola.
Subassembly Reference Primary (Front) Side I/O Connectors The tables in the next few sections provide pin assignments for all I/O, HSC and CPU slots. For further connector pinouts, refer to the table below.
Primary (Front) Side (Slots 1-6 and 11-16) Table 6-32. P4 Connector, I/O Slots 1-6, 11-16 (continued) POS Row Z Row A Row B Row C Row D Row E Row F 21 NP -SELVbat PSF1# RSVD RSVD SELVbat RTN FG 20 NP NP NP NP NP NP NP 19 NP NP NP NP NP NP NP 18 NP VRG NP NP NP VRG RTN NP 17 NP NP NP NP NP NP NP 16 NP NP NP NP NP NP NP 15 NP -Vbat NP NP NP Vbat RTN NP 14-12 KEY AREA 11 NP CT_D29 CT_D30 CT_D31 V(I/O) CT_FRAME_A# GND 10 NP CT_D27 +3.
Subassembly Reference Primary (Front) Side CPU Connectors The CPU connectors on the CPX8216T H.110 backplane use the same pinouts as the CPX8216 standard backplane. 6 For Pinout Information for Connector: See: P5 Table 6-15 on page 6-17 P4 Table 6-16 on page 6-18 P3 Table 6-17 on page 6-20 P2-Domain A Table 6-18 on page 6-20 P2-Domain B Table 6-19 on page 6-22 P1 Table 6-20 on page 6-23 Primary (Front) Side HSC Connectors The HSC/Bridge slot is unique.
Primary (Front) Side HSC Connectors Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10) (continued) POS Row Z Row A Row B Row C Row D Row E Row F 21 GND _AD53 _AD52 _AD51 _GND _AD50 GND 20 GND _AD57 _+3.3 _AD56 _AD55 _AD54 GND 19 GND _AD61 _AD60 _AD59 _GND _AD58 GND 18 GND _CBE4# _+3.3 _PAR64 _AD63 _AD62 GND 17 GND _REQ64# _CBE7# _CBE6# _GND _CBE5# GND 16 GND _AD2 _+3.
Subassembly Reference Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10) (continued) POS Row Z Row A Row B Row C Row D Row E Row F 2 GND _GNT# _REQ# _AD31 _AD30 _AD29 GND 1 GND _INTA# _INTB# _INTC# _INTD# _RST# GND The _GND, _+5 and _+3 in the shaded cells are provided by the CPU board; they are not connected to the system power plane. These signals are prefixed with CPUA if the board resides in slot 10 or CPUB if the board resides in slot 8 (for example, CPUA_+5).
Primary (Front) Side HSC Connectors Table 6-34. P4 Connector, HSC Slots 8 and 10 (continued) POS Row Z Row A Row B Row C Row D Row E Row F 17 NP NP NP NP NP NP NP 16 NP NP NP NP NP NP NP 15 NP -Vbat NP NP NP Vbat RTN NP 1412 KEY AREA 11 NP CT_D29 CT_D30 CT_D31 V(I/O) CT_FRAME_A# GND 10 NP CT_D27 +3.
Subassembly Reference Table 6-35.
Primary (Front) Side HSC Connectors Table 6-35. P3 Connector, HSC Slots 8 and 10 (continued) POS Row Z Row A Row B Row C Row D Row E Row F 5 GND BD_SEL5# HLTY5# BD_SEL7# HLTY15# BD_SEL15 # GND 4 GND BD_SEL4# HLTY4# RST10# HLTY14# BD_SEL14 # GND 3 GND BD_SEL3# HLTY3# RST9# HLTY13# BD_SEL13 # GND 2 GND BD_SEL2# HLTY2# RST8# HLTY12# BD_SEL12 # GND 1 GND BD_SEL1# HLTY1# RST7# HLTY11# BD_SEL11 # GND A/B# GND Domain B (slot 8).
Subassembly Reference Table 6-36.
Primary (Front) Side HSC Connectors Table 6-37.
Subassembly Reference Table 6-37. P2 Connector, HSC Slot 8 (continued) POS Row Z Row A Row B Row C Row D Row E Row F 2 GND CLK12 CLK13 _SYSEN# GNT12# REQ13# GND 1 GND CLK11 GND REQ11# GNT11# REQ12# GND Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example, PCI_A_AD[49]). Signals in parentheses are not used. Table 6-38. P1 Connector, HSC Slots 8 and 10 6 POS Row Z Row A Row B Row C Row D Row E Row F 25 GND 5V _REQ64# A_ENUM # 3.
Primary (Front) Side HSC Connectors Table 6-38. P1 Connector, HSC Slots 8 and 10 (continued) POS Row Z Row A Row B Row C Row D Row E Row F 10 GND _AD[21] GND 3.3V _AD[20] _AD[19] GND 9 GND _C/BE[3] _IDSEL _AD[23] GND _AD[22] GND 8 GND _AD[26] GND VIO _AD[25] _AD[24] GND 7 GND _AD[30] _AD[29] _AD[28] GND _AD[27] GND 6 GND REQ[N]# GND 3.
Subassembly Reference Secondary (Rear) Side I/O Connectors Note I/O slot connectors P4, P2, and P1 do not connect through to the transition module. Table 6-39. P5 Connector, I/O Slots 1-6 and 11-16 (User I/O) POS Row Z Row A Row B Row C Row D Row E Row F 22-1 GND I/O I/O I/O I/O I/O GND All I/O pins pass through the backplane to the transition module, they do not make any connection to the backplane. 6 Table 6-40.
Alarm Display Panel Alarm Display Panel Telco Relay LEDs Uncommitted Digital Inputs Alarm PLD o o o o o o o o POR 6 REG GND POWER System LEDs PWR A PWR B HSC IFC Conn System Alarm Conn The alarm display panel provides the system LEDs and remote alarm functions for the CPX8216 and the CPX8216T. It is powered and controlled from each of the two Hot Swap Controllers within the system (see Figure 6-7).
Subassembly Reference SYSTEM SYSTEM IN SERVICE STATUS 1 2 3 COMPONENT 4 5 TELCO COMPONENT OUT OF SERVICE 6 MINOR MAJOR ALARM CRITICAL STATUS 7 8 CONNECTION 9 10 11 12 13 14 15 16 Figure 6-8. Alarm Display Panel—Front View The alarm display panel LEDs are controlled by bits in the Hot Swap Controller’s register, which are set by the system software. This allows full user customization of alarm event reporting.
Alarm Display Panel Interface Connector (J4) Alarm Display Panel Interface Connector (J4) Connector J4 receives system alarm signals from the backplane connector ALARM. Table 6-42.
Subassembly Reference Power Distribution Panel The power distribution panel, located in the rear of the chassis below the transition module cardcage, distributes the AC or DC input power to the system’s power supplies. There are three versions of the power distribution panel: ❏ AC (CPX8216) ❏ Dual Input DC (CPX8216) ❏ Dual Breaker DC (CPX8216) 6 ❏ H.110 DC (CPX8216T) The CPX8216T can be configured with AC or DC power, however only the DC version has the dual input option and the H.
Dual Input DC Power Distribution Panel (CPX8216) Dual Input DC Power Distribution Panel (CPX8216) The dual input DC version allows redundant input power supplies for full high-availability applications. It is recommended that each input source be independent of the other. -48 VDC ON ON -48 VDC RTN -48 VDC -48 VDC RTN 2572 9907 Figure 6-10. Dual Input DC Power Distribution Panel—Front View Use 12 AWG or larger wire with a #10 ring terminal to connect the DC power source to the system.
Subassembly Reference Figure 6-11. Dual Breaker DC Power Distribution Panel—Front View The dual breaker DC power distribution panel is available without the two 30A circuit breakers, provided that circuit breaker protection is provided elsewhere and there is allowance for a rating of 30A for each feed. 6 Use either a standard Smart cable or the optional right-angle Smart cable (for limited space requirements) to connect the DC power source to the system. Cable length is 10 feet.
H.110 DC Power Distribution Panel (CPX8216T) -SEL VBAT System Power Terminal Blocks SEL VBAT RTN VRG VRG RTN VBAT RTN -VBAT H.110 BAT and Ring Voltage Terminal Block -48 VDC ON ON -48 VDC RTN -48 VDC -48 VDC RTN 2573 9907 Figure 6-12. H.110 DC Power Distribution Panel The analog voltages on the H.110 bus are: 6 Table 6-44. DC Analog Voltages for H.
Power Supplies Power Supplies The AC and DC power supplies are mounted on a sled along with the replaceable cooling fans and are discussed in the CPX8000 Series CPX8216 and CPX8216T System Installation and Use manual. For the power coupling to the backplane, refer to the information in Power Supply Connectors (PS1, PS2, PS3) on page 6-6. For the electrical specification for the power supply, refer to Power Supply Electrical Specifications on page A-2. 6 http://www.motorola.
ASpecifications A Environmental Characteristics ENVIRONMENTAL CHARACTERISTICS Temperature Operating: 0º to 50º C (32º to 122º F) continuous duty with linear current derating between +50º C to +60º C (122º to 140º F) to 50% maximum rated power Storage and Transit: -25º TO +85º C (-13º to 185º F) Maximum Altitude Operating: Linear current derating to 85% between 8,000 feet and 12,000 feet Storage and Transit: 30,000 feet Shock No degradation at 25g shock of 11ms duration at 1/2 sine wave in three p
A Specifications Power Supply Electrical Specifications AC Input AC Voltage: 90 Vac to 132 Vac or 190 Vac to 260 Vac (autoranging) AC Frequency: 47 Hz to 63 Hz Power Factor: Minimum 0.98 at full load and nominal line Turn-on Surge Current: 20 Amps at +/- 2A for one line cycle Efficiency: -72% typical at full load and nominal line, including output Oring diodes Input Current: Measured 6.
Power Supply Electrical Specifications Table A-1. Total Regulation (per Output) Output Number Voltage Set Point at Load Maximum Current Loads Total Regulation V1 +5.0V +5.06Vdc@20A +/- 5 mV 40A 0 to 40A ±3% V2 +3.3V +3.36Vdc@20A +/- 5 mV 40A 0 to 40A ±3% V3 +12.0V +12.1Vdc@4A +/- 24 mV 10.4A cont. (11.5A peak for max. 5 sec.) 0 to 10.4A ±5% V4 -12.0V -12.1Vdc@2A +/- 12 mV 4A 0 to 4A ±5% Output Power 400 Watts total continuous maximum from all outputs.
A Specifications Overshoot Overshoot does not exceed 2.0% of any output voltage under the following conditions: power failure, enabled, disabled, and AC input cycled on/off. Overshoot is the phenomena where the magnitude of voltage of an output temporarily exceeds its final or stabilized value. Load Change Transient Any DC voltage returns to 1% within 2mS in response to a 25% change Response in the load. The +5V output does not vary more than 3% in response to a 25% change in load.
Power Supply Electrical Specifications Over Voltage Protection A Single Fault condition is the failure of any one device within the power supply. The condition includes both the shorting of any output and the failure of any one device within the power supply. Under any single fault condition: The +5V outputs limit voltage at 6.4Vdc maximum. The +3.3V output limits voltage at 4.2Vdc maximum The ±12V outputs do not exceed ±15.0Vdc, respectively.
BRelated Documentation B Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: ❏ Contacting your local Motorola sales office ❏ Visiting MCG’s World Wide Web literature site, http://www.motorola.com/computer/literature ❏ To locate and view the most up-to-date product information in PDF or HTML format, visit http://www.motorola.com/computer/literature.
Related Documentation B Document Title Motorola Publication Number TMCP700 Transition Module Installation and Use TMCP700A/IH CPV5350 CompactPCI Single Board Computer and Transition Module installation and Reference CPV5350A/IH CPV8540 CompactPCI Hot Swap Carrier Card User Manual (Single PMC) CPV8540A/UM CPV8540 CompactPCI Hot Swap Carrier Card User Manual (Dual PMC) CPV8540B/UM Related Specifications For additional information, refer to the following table for related specifications.
Related Specifications Table B-1. Related Specifications (continued) Document Title and Source Versatile Backplane Bus: VMEbus Institute of Electrical and Electronics Engineers, Inc. OR B Publication Number ANSI/IEEE Standard 1014-1987 Microprocessor system bus for 1 to 4 byte data Bureau Central de la Commission Electrotechnique Internationale 3, rue de Varembé Geneva, Switzerland IEEE Standard for Compact Embedded PC Modules IEEE P996.
Related Documentation B URLs The following URLs (uniform resource locators) may provide helpful sources of additional information about this product, related services, and development tools. Please note that, while these URLs have been verified, they are subject to change without notice. ❏ Motorola Computer Group, http://www.motorola.com/computer ❏ Motorola Computer Group OEM Services, http://www.motorola.com/computer/support ❏ Technobox Inc., http://www.technobox.
Index A AC power input A-2 acoustic noise A-1 adapters, PMC 4-1 alarm board. See alarm display panel alarm display panel 1-13, 6-51 to 6-53 alarm interface connector 6-8 altitude, operating A-1 B backplane connectors 6-6 reference 6-5 board insertion, features 1-14 branch circuits, TNV 6-56 bridge connector slots 6-29 bus access in CPX8216T 1-4 bus connectors, H.
I N D E X USB 5-10 connectors (CPX8216) alarm 6-8 alarm display panel 6-53 CPU slot 6-17 fan module 6-7 floppy drive 6-8 HSC/bridge 6-29 I/O 6-11 I/O slot 6-26 IDE drive 6-9 power 6-10 power supply 6-6 signal 6-11 transition module 6-27 connectors (CPX8216T) bus, H.
SIMs 5-16 speaker connector 5-13 USB connectors 5-10 CPX8216 bus access 1-4 CPU modules 1-12 hot swap controller 1-12 standard system 1-2 subsystems 1-2 system description 1-1 CPX8216T bus connectors, H.110 6-37 to 6-50 chassis ID 1-13 H.
I I/O connectors, H.
DRAM mezzanine 2-10 Ethernet 2-5 USB 2-4 pin assignments (CPX750HATM) COM1/COM2 5-6 EIDE connector 5-11 floppy port 5-12 I/O connector 5-5, 5-6 keyboard/mouse 5-10 parallel port 5-9 PMC I/O connector 5-14 power connector 5-12 serial port 5-7 speaker connector 5-13 pin assignments (CPX8216) alarm display panel connector 6-53 CPU slots 6-17 fan module 6-7 floppy connector 6-8 HSC/bridge 6-29 I/O 6-11 I/O slots 6-26 IDE drive 6-9 power connector 6-10 signal connectors 6-11 transition module slots 6-27 pin assi
software and the HSC 1-7 speaker connector 5-13 specifications electrical A-2 environmental A-1 status indicators 2-16 status LEDs 1-13, 6-51 switch settings MPMC150 4-3 PMC Adapter 4-3 system active/active configuration 1-9 architecture 1-4 configurations 1-4 device drivers 1-19 EIDE devices 1-11 peripherals 1-10 SCSI devices 1-11 simplex configuration 1-7 slots 6-4 status LEDs 1-13, 6-51 system domains, description 1-1 T IN-6 Computer Group Literature Center Web Site Telephone Network Voltage (TNV) 6-
