MVME162 Embedded Controller Installation Guide (MVME162IG/D2)
Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Preface This manual provides a general board level hardware description, hardware preparation and installation instructions, debugger general information, and using the debugger in the MVME162 Embedded Controller.
The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., first published 1990, and may be used only under a license such as the License for Computer Programs (Article 14) contained in Motorola’s Terms and Conditions of Sale, Rev. 1/79. ! WARNING This equipment generates, uses, and can radiate radio frequency energy and if not installed and used in accordance with the documentation for this product, may cause interference to radio communications.
Safety Summary Safety Depends On You The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the customer’s failure to comply with these requirements.
BOARD LEVEL HARDWARE DESCRIPTION 1 Introduction This chapter describes the board level hardware features of the MVME162 Embedded Controller. The chapter is organized with a board level overview and features list in this introduction, followed by a more detailed hardware functional description. Front panel switches and indicators are included in the detailed hardware functional description. The chapter closes with some general memory maps.
1 Board Level Hardware Description The VMEbus interface is provided by an ASIC called the VMEchip2. The VMEchip2 includes two tick timers, a watchdog timer, programmable map decoders for the master and slave interfaces, and a VMEbus to/from local bus DMA controller, a VMEbus to/from local bus non-DMA programmed access interface, a VMEbus interrupter, a VMEbus system controller, a VMEbus interrupt handler, and a VMEbus requester. Processor-to-VMEbus transfers can be D8, D16, or D32.
Introduction Document Title Motorola Publication Number Single Board Computers SCSI Software User’s Manual SBCSCSI MVME162 Embedded Controller Programmer’s Reference Guide MVME162PG MVME712M Transition Module and P2 Adapter Board User’s Manual MVME712M MVME712-12, MVME712-13, MVME712A, MVME712AM, and MVME712B Transition Modules and LCP2 Adapter Board User’s Manual MVME712A M68040 Microprocessors User’s Manual M68040UM N otes The SIMVME162 manual contains the connector interconnect signal infor
1 Board Level Hardware Description 68-1X7DS for use with the MVME162 and 167. NCR 53C710 SCSI Controller Data Manual and Programmer’s Guide Intel i82596 Ethernet Controller User’s Manual Cirrus Logic CD2401 Serial Controller User’s Manual SGS-Thompson MK48T08 NVRAM/TOD Clock Data Sheet The following publications are also available from the sources indicated. Versatile Backplane Bus: VMEbus, ANSI/IEEE Std 1014-1987, The Institute of Electrical and Electronics Engineers, Inc.
Introduction Requirements These boards are designed to conform to the requirements of the following documents: ❏ VMEbus Specification (IEEE 1014-87) ❏ EIA-232-D Serial Interface Specification, EIA ❏ SCSI Specification, ANSI ❏ IndustryPack Specification, GreenSpring Features ❏ 25MHz 32-bit MC68040 or MC68LC040 Microprocessor ❏ 1 MB, 4 MB, or 8 MB of shared DRAM with parity protection ❏ 512 KB of SRAM with battery backup ❏ One JEDEC standard 32-pin PLCC EPROM socket (EPROMs may be shipped sepa
1 Board Level Hardware Description ❏ – VMEbus interface to local bus (A24/A32, D8/D16/D32 (D8/D16/D32/D64 BLT) (BLT = Block Transfer) – Local bus to VMEbus interface (A16/A24/A32, D8/D16/D32) – VMEbus interrupter – VMEbus interrupt handler – Global CSR for interprocessor communications – DMA for fast local memory - VMEbus transfers (A16/A24/A32, D16/D32 (D16/D32/D64 BLT) Switches and Light-Emitting Diodes (LEDs) – Two pushbutton switches (ABORT and RESET) – Eight LEDs (FAIL, STAT, RUN, SCO
Introduction Special Considerations for Elevated Temperature Operation The following information is for the user who has an application for the MVME162 which will subject it to high temperature. The MVME162 uses commercial grade devices. Therefore, it can operate in an environment with ambient air temperature from 0° C to 70° C.
1 Board Level Hardware Description Manual Terminology Throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric format as follows: $ dollar specifies a hexadecimal character % percent specifies a binary number & ampersand specifies a decimal number For example, "12" is the decimal number twelve, and "$12" is the decimal number eighteen. Unless otherwise specified, all address references are in hexadecimal.
Block Diagram Block Diagram Figure 1-1 is a general block diagram of the MVME162. MC68040 or MC68LC040 82596CA LAN ETHERNET Z85230 SCC SERIAL IO 53C710 SCSI FLASH MEMORY MCchip DRAM VMEchip2 IPIC SRAM PROM SOCKET MK48T08 BBRAM & CLOCK VMEbus bd072 9212 Figure 1-1.
1 Board Level Hardware Description Functional Description This section contains a functional description of the major blocks on the MVME162 Embedded Controller. Front Panel Switches and Indicators There are switches and LEDs on the front panel of the MVME162. The switches are RESET and ABORT. The RESET switch resets all onboard devices and drives SYSRESET* if the board is system controller. The RESET switch may be disabled by software.
Functional Description Data Bus Structure The local data bus on the MVME162 is a 32-bit synchronous bus that is based on the MC68040 bus, and which supports burst transfers and snooping. The various local bus master and slave devices use the local bus to communicate. The local bus is arbitrated by priority type arbiter and the priority of the local bus masters from highest to lowest is: 82596CA LAN, 53C710 SCSI, VMEbus, and MPU.
1 Board Level Hardware Description Memory Options The following memory options are used on the different versions of MVME162 boards. DRAM Options The MVME162 implementation includes a 1 MB, 4 MB, or 8 MB DRAM option. The DRAM architecture is non-interleaved for 1 MB and 8 MB; while the 4 MB architecture is interleaved. Parity protection can be enabled with interrupts or bus exception when a parity error is detected.
Functional Description C aution For proper operation of the SRAM, some jumper combination must be installed on the Backup Power Source Select Header (J20). If one of the jumpers is used to select the battery, the battery must be installed on the MVME162. The SRAM may malfunction if inputs to the DS1210S are left unconnected. The SRAM is controlled by the MCchip, and the access time is programmable.
1 Board Level Hardware Description ! WARNING Lithium batteries incorporate inflammable materials such as lithium and organic solvents. If lithium batteries are mistreated or handled incorrectly, they may burst open and ignite, possible resulting in injury and/or fire. When dealing with lithium batteries, carefully follow the precautions listed below in order to prevent accidents. ❏ Do not short circuit. ❏ Do not disassemble, deform, or apply excessive pressure. ❏ Do not heat or incinerate.
Functional Description is an 8 bit device; however, the interface provided by the MCchip supports 8bit, 16-bit, and 32-bit accesses to the MK48T08. Refer to the MCchip description in the MVME162 Embedded Controller Programmer’s Reference Guide and to the MK48T08 data sheet for detailed programming and battery life information. VMEbus Interface and VMEchip2 The local bus to VMEbus interface and the VMEbus to local bus interface are provided by the optional VMEchip2.
1 Board Level Hardware Description ❏ The DB-25 connector marked SERIAL PORT 1/CONSOLE on the front panel of the MVME162. SERIAL PORT 1/CONSOLE is an EIA-232-D DCE port. NOTE: This port can be connected to the TX and RX clocks which may be present on the DB-25 connector. These connections are made via jumper header J11 on the MVME162 board. (The TxC and RxC clock lines are not available on the MVME712X transition modules.
Functional Description ❏ One of the following output connectors on the MVME712X transition module: MVME712M: The DB-25 connector marked SERIAL PORT 4 on the front panel. SERIAL PORT 4 can be configured as an EIA-232-D DTE or DCE port, via the jumper headers J18 and J19 on the MVME712M. MVME712A, AM, -12, or -13: The DB-9 connector marked SERIAL PORT 4 on the front panel. SERIAL PORT 4 is hard-wired as an EIA-232-D DTE port.
1 Board Level Hardware Description VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus. Every MVME162 that has the Ethernet interface is assigned an Ethernet Station Address. The address is $08003E2XXXXX where XXXXX is the unique 5-nibble number assigned to the board (i.e., every MVME162 has a different value for XXXXX).
Functional Description Local Resources The MVME162 includes many resources for the local processor. These include tick timers, software-programmable hardware interrupts, watchdog timer, and local bus timeout. Programmable Tick Timers Six 32-bit programmable tick timers with 1 µs resolution are provided, two in the VMEchip2 and four in the MCchip. The tick timers can be programmed to generate periodic interrupts to the processor.
1 Board Level Hardware Description The access timer logic is duplicated in the VMEchip2 and MCchip ASICs. Because the local bus timer in the VMEchip2 can detect an offboard access and the MCchip local bus timer cannot, the timer in the VMEchip2 is used in all cases except for the version of the MVME162 which does not include the VMEbus interface ("No-VMEbus-Interface option"). Local Bus Arbiter The local bus arbiter implements a fixed priority which is described in the following table. Table 1-2.
Memory Maps Local Bus Memory Map The local bus memory map is split into different address spaces by the transfer type (TT) signals. The local resources respond to the normal access and interrupt acknowledge codes. Normal Address Range The memory map of devices that respond to the normal address range is shown in the following tables. The normal address range is defined by the Transfer Type (TT) signals on the local bus. On the MVME162, Transfer Types 0, 1, and 2 define the normal address range.
1 Board Level Hardware Description NOTES: 1-22 1. Reset enables the decoder for this space of the memory map so that it will decode address spaces $FF800000 - $FF9FFFFF and $00000000 $003FFFFF. The decode at 0 must be disabled in the MCchip before DRAM is enabled. DRAM is enabled with the DRAM Control Register at address $FFF42048, bit 24. PROM/Flash is disabled at the low address space with PROM Control Register at address $FFF42040, bit 20. 2. This area is user-programmable.
Memory Maps The following table focuses on the Local I/O Devices portion of the local bus Main Memory Map. Table 1-4.
1 Board Level Hardware Description NOTES: 1-24 1. For a complete description of the register bits, refer to the MVME162 Embedded Controller Programmer’s Reference Guide or to the data sheet for the specific chip. 2. The SCC is an 8-bit device located on an MCchip private data bus. Byte access is required. 3. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits.
Memory Maps VMEbus Memory Map This section describes the mapping of local resources as viewed by VMEbus masters. Default addresses for the slave, master, and GCSR address decoders are provided by the ENV command. Refer to Appendix A. VMEbus Accesses to the Local Bus The VMEchip2 includes a user-programmable map decoder for the VMEbus to local bus interface. The map decoder allows you to program the starting and ending address and the modifiers the MVME162 responds to.
1 Board Level Hardware Description 1-26 MVME162 Embedded Controller Installation Guide
HARDWARE PREPARATION AND INSTALLATION 2 Introduction This chapter provides unpacking instructions, hardware preparation, and installation instructions for the MVME162 Embedded Controller. Hardware preparation for the MVME712 series transition modules is provided in separate manuals. Refer to the Related Documentation section in Chapter 1. Unpacking Instructions N ote If the shipping carton is damaged upon receipt, request carrier’s agent be present during unpacking and inspection of equipment.
Hardware Preparation and Installation MVME162 operates with its required and factory-installed Debug Monitor, MVME162Bug (162Bug), with these factory jumper settings.
Hardware Preparation 2 P1 27 26 2 1 49 50 24 25 J8 27 26 2 1 A32 B32 C32 J3 A1 B1 C1 49 50 24 25 27 26 2 1 49 50 J6 1 2 F2 S1 2 1 S2 2 1 P3 40 39 P4 25 13 40 39 J10 PRIMARY SIDE 40 39 J9 J20 5 6 1 27 26 2 1 A32 B32 C32 J19 3 49 50 24 25 27 26 2 1 1 2 J21 P2 27 26 2 1 A1 B1 C1 J14 J18 1 2 49 50 24 25 49 50 24 25 J17 27 26 2 1 49 50 J13 J12 4 1 14 1 2 J15 J16 25 13 J11 4 1 SERIAL PORT 1/ CONSOLE 14 49 50 49 50 24 25 2 1 2 1 2 1 SERIAL PORT 2 J22
Hardware Preparation and Installation 2 Table 2-1. Serial Interface Module Part Numbers EIA Standard Configuration Part Number Model Number EIA-232-D DTE 01-W3846B SIM05 DCE 01-W3865B SIM06 DTE 01-W3868B SIM07 DCE 01-W3867B SIM08 EIA-530 39 1 J1 40 2 SECONDARY SIDE 10922.00 9403 (2-2) Figure 2-2. Serial Interface Module, Connector Side Removal of Existing SIM 1. Each serial interface module is retained by two 4-40 x 3/16 ” Phillips-head screws in opposite corners.
Hardware Preparation Installation of New SIM 1. Observe the orientation of the connector keys on SIM connector J1 and MVME162 connector J10. Turn the SIM so that the keys line up and place it gently on connector J10, aligning the mounting holes at the SIM corners with the matching standoffs on the MVME162. 2. Gently press the top of the SIM to seat it on the connector. If the SIM does not seat with gentle pressure, recheck the orientation.
Hardware Preparation and Installation 2 Synchronous Clock Select Header (J11) for Serial Port 1/Console The MVME162 is shipped from the factory with the SERIAL PORT 1/CONSOLE header configured for asynchronous communications (i.e., jumpers removed). To select synchronous communications for the SERIAL PORT 1/CONSOLE connection, install jumpers across pins 1 and 2 and pins 3 and 4.
Hardware Preparation SRAM Battery Backup Source Select Header (J20) 2 The MVME162 is factory-configured to use VMEbus +5V Standby power as a backup power source for the SRAM (i.e., jumpers are installed across pins 1 and 3 and 2 and 4). To select the onboard battery as the backup power source, install the jumpers across pins 3 and 5 and 4 and 6. N ote For MVME162s without optional VMEbus interface (i.e., without VMEchip2 ASIC), you must select the onboard battery for the backup power source.
Hardware Preparation and Installation 2 General Purpose Readable Jumpers Header (J22) Header J22 provides eight readable jumpers. These jumpers are read as a register (at $FFF4202D) in the MCchip LCSR (local control/status register). The bit values are read as a zero when the jumper is installed and as a one when the jumper is removed. If the MVME162BUG firmware is installed, four jumpers are user-definable (pins 1-2, 3-4, 5-6, 7-8).
Installation Instructions Installation Instructions 2 The following sections discuss the installation of IndustryPacks (IPs) on the MVME162, the installation of the MVME162 into a VME chassis, and the system considerations relevant to the installation. Before installing IndustryPacks, ensure that the serial ports and all header jumpers are configured as desired. IP Installation on the MVME162 Up to four IndustryPack (IP) modules may be installed on the MVME162.
Hardware Preparation and Installation 2 MVME162 Module Installation With EPROM, IndustryPack, and SIMs installed and headers properly configured, proceed as follows to install the MVME162 in the VME chassis: 1. Turn all equipment power OFF and disconnect the power cable from the AC power source. C aution Inserting or removing modules while power is applied could result in damage to module components. ! Dangerous voltages, capable of causing death, are present in this equipment.
Installation Instructions 8. Connect the P2 Adapter Board or LCP2 Adapter Board and cable(s) to MVME162 backplane connector P2. This provides a connection point for terminals or other peripherals at the EIA-232-D serial ports, SCSI ports, and LAN Ethernet port.
Hardware Preparation and Installation programmed by the MVME162Bug firmware. This may be changed via software to any other base address. Refer to MVME162 Embedded Controller Programmer’s Reference Guide for more information. 2 If the MVME162 tries to access offboard resources in a nonexistent location and is not system controller, and if the system does not have a global bus timeout, the MVME162 waits forever for the VMEbus cycle to complete. This will cause the system to lock up.
Installation Instructions 2 712M TRANSITION MODULE PORT 2 DB25 TO MODEM J17 TXD RXD RTS CTS DTR DCD P2-C27 TXD2 TXD P2-C28 RXD2 RXD P2-C29 RTS2 RTS P2-C30 CTS2 CTS P2-C31 DTR2 DTR P2-C32 DCD2 DCD DSR P2 TXC CABLE TO TERMINAL J16 PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 RXC PIN 17 TXCO +12V PIN 24 PIN 7 1.
Hardware Preparation and Installation 2 712M TRANSITION MODULE PORT 2 TXD RXD RTS CTS DTR DCD TO MODEM J17 DB25 P2-C27 TXD2 TXD P2-C28 RXD2 RXD P2-C29 RTS2 RTS P2-C30 CTS2 CTS P2-C31 DTR2 DTR P2-C32 DCD2 DCD DSR P2 TXC CABLE TO TERMINAL J16 PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 RXC PIN 17 TXCO +12V PIN 24 PIN 7 1.
Installation Instructions 2 712M TRANSITION MODULE PORT 4 TO MODEM J19 TXD RXD RTS CTS DTR DCD DB25 P2-A25 TXD4 TXD P2-A26 RXD4 RXD P2-A27 RTS4 RTS P2-A29 CTS4 CTS P2-A30 DTR4 DTR P2-A31 DCD4 DCD DSR RTXC P2-A32 RTXC4 TRXC P2-A28 TRXC4 P2 TXC TO TERMINAL J18 CABLE PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 RXC PIN 17 TXCO PIN 24 PIN 7 +12V 1.
Hardware Preparation and Installation 2 712M TRANSITION MODULE PORT 4 TO MODEM J19 TXD RXD RTS CTS DTR DCD DB25 P2-A25 TXD4 TXD P2-A26 RXD4 RXD P2-A27 RTS4 RTS P2-A29 CTS4 CTS P2-A30 DTR4 DTR P2-A31 DCD4 DCD DSR P2-A32 RTXC4 TXC TRXC P2-A28 TRXC4 RXC RTXC P2 TO TERMINAL J18 PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 TXCO CABLE PIN 24 PIN 7 +12V 1.
Installation Instructions 2 712M TRANSITION MODULE PORT 4 TXD RXD RTS CTS DTR DCD TO MODEM J19 DB25 TXD P2-A25 TXD4 P2-A26 RXD4 RXD P2-A27 RTS4 RTS P2-A29 CTS4 CTS P2-A30 DTR4 DTR P2-A31 DCD4 DCD DSR RTXC P2-A32 RTXC4 TRXC P2-A28 TRXC4 TXC TO TERMINAL J18 CABLE PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 RXC PIN 17 TXCO P2 PIN 2 PIN 24 PIN 7 +12V 1.5K J15 MVME712M EIA-232-D CONFIGURATION (TO TERMINAL) NOTES: 1.
Hardware Preparation and Installation 2 712M TRANSITION MODULE PORT 4 TXD RXD RTS CTS DTR DCD TO MODEM J19 DB25 TXD P2-A25 TXD4 P2-A26 RXD4 RXD P2-A27 RTS4 RTS P2-A29 CTS4 CTS P2-A30 DTR4 DTR P2-A31 DCD4 DCD DSR RTXC P2-A32 TRXC P2-A28 TXC RTXC4 TO TERMINAL J18 TRXC4 RXC TXCO P2 PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24 CABLE PIN 7 +12V 1.
Installation Instructions 2 P2 CONNECTOR TXD_B TXD_A RXD_B RXD_A RTS_B RTS_A CTS_B CTS_A DTR_B DTR_A DCD_B DCD_A DSR_B MVME 162 EIA-530 DTE CONFIGURATION (TO MODEM) DSR_A TXC_B TXC_A RXC_B RXC_A TXCO_B TXCO_A TM_A LL_A RL_A SIM07 EIA-530 DTE Z85230 TXD RTS* RTS RTS_B RTS_A D CTS* CTS_B CTS_A R DTR_B DTR_A D DTR* DCD* TXC RXC RXD_B RXD_A R RXD NC 3 R DCD_B DCD_A R DSR_B DSR_A R TXC_B TXC_A 4 +5V 1 RXC_B RXC_A 2 R J12 TXCO_B TXCO_A D NC +5V D +5V D P2-A26 P2-C19 P2-A27 P2-C
Hardware Preparation and Installation Figure 2-4.
Installation Instructions 2 P2 CONNECTOR 712A/AM/12/13 TRANSITION MODULE PORT 2 DCE 1.
Hardware Preparation and Installation 2 712AM/13 TRANSITION MODULE PORT 2 DCE 1.5K DTE J9 1.
Installation Instructions (Sheet 1 of 4) 2 712A/AM/-12/-13 TRANSITION MODULE PORT 4 DCE 1.5K DTE J14 1.5K +12V DB9 TXD RXD RTS CTS DTR DCD P2-A25 TXD4 TXD P2-A26 RXD4 RXD P2-A27 RTS4 RTS P2-A29 CTS4 CTS P2-A30 DTR4 DTR P2-A31 DCD4 DCD DSR TXC P2-A32 RTXC4 RXC P2-A28 TRXC4 P2 PIN 3 PIN 2 PIN 7 PIN 8 PIN 4 PIN 1 PIN 6 NC NC CABLE MVME 712A/AM/-12/-13 PORT 4 (DTE) NOTES: 1. SERIAL PORT 4 IS HARD-WIRED DTE. USE NULL MODEM CABLE FOR DCE. 2.
Hardware Preparation and Installation 2 712A/AM/-12/-13 TRANSITION MODULE PORT 4 DCE 1.5K DTE J14 1.5K +12V DB9 TXD RXD RTS CTS DTR DCD P2-A25 TXD4 TXD P2-A26 RXD4 RXD P2-A27 RTS4 RTS P2-A29 CTS4 CTS P2-A30 DTR4 DTR P2-A31 DCD4 DCD DSR TXC P2-A32 RTXC4 RXC P2-A28 TRXC4 P2 PIN 3 PIN 2 PIN 7 PIN 8 PIN 4 PIN 1 PIN 6 NC NC CABLE MVME 712A/AM/-12/-13 PORT 4 (DTE) NOTES: 1. SERIAL PORT 4 IS HARD-WIRED DTE. USE NULL MODEM CABLE FOR DCE. 2.
Installation Instructions (Sheet 2 of 4) MVME162IG/D2 2 2-25
Hardware Preparation and Installation 2 Figure 2-5.
Installation Instructions (Sheet 3 of 4) MVME162IG/D2 2 2-27
Hardware Preparation and Installation 2 Figure 2-5.
Installation Instructions (Sheet 4 of 4) MVME162IG/D2 2 2-29
Hardware Preparation and Installation 2 2-30 MVME162 Embedded Controller Installation Guide
DEBUGGER GENERAL INFORMATION 3 Overview of M68000 Firmware The firmware for the M68000-based (68K) series of board and system level products has a common genealogy, deriving from the BUG firmware currently used on all Motorola M68000-based CPU modules. The M68000 firmware family provides a high degree of functionality and user friendliness, and yet stresses portability and ease of maintenance.
Debugger General Information When using 162Bug, you operate out of either the debugger directory or the diagnostic directory. If you are in the debugger directory, the debugger prompt "162-Bug>" is displayed and you have all of the debugger commands at your disposal. If you are in the diagnostic directory, the diagnostic prompt "162-Diag>" is displayed and you have all of the diagnostic commands at your disposal as well as all of the debugger commands.
162Bug Implementation 162Bug Implementation MVME162Bug is written largely in the "C" programming language, providing benefits of portability and maintainability. Where necessary, assembler has been used in the form of separately compiled modules containing only assembler code - no mixed language modules are used. Physically, 162Bug is contained in two of the four 28F020 Flash memories, providing 512KB (128K longwords) of storage. Optionally, the 162Bug can be loaded and executed in a single 27C040 PROM.
Debugger General Information Bit 3 J22 Pins Description Bit #0 (GPI0) 15-16 When this bit is a one (high), it instructs the debugger to use local Static RAM for its work page (i.e., variables, stack, vector tables, etc.). Bit #1 (GPI1) 13-14 When this bit is a one (high), it instructs the debugger to use the default setup/operation parameters in Flash or PROM versus the user setup/operation parameters in NVRAM. This is the same as depressing the RESET and ABORT switches at the same time.
Installation and Startup 4. 5. Jumpers on headers J11 and J12 configure serial ports 1 and 2 to drive or receive clock signals provided by the TXC and RXC signal lines. The factory configures the module for asynchronous communication, that is, installs no jumpers. Refer to Chapter 2 if your application requires configuring ports 1 and 2 for synchronous communication. If using a PROM version of the 162Bug, install the PROM device in socket U47.
Debugger General Information appropriate cables and configure the port(s) as detailed in step 6. above. After power-up, this(these) port(s) can be reconfigured by programming the MVME162 Z85230 Serial Communications Controller (SCC), or by using the 162Bug PF command. 3 9. Power up the system. 162Bug executes some self-checks and displays the debugger prompt "162-Bug>" (if 162Bug is in Board Mode).
ROMboot C aution Although streaming tape can be used to autoboot, the same power supply must be connected to the streaming tape drive, controller, and the MVME162. At power-up, the tape controller will position the streaming tape to load point where the volume ID can correctly be read and used.
Debugger General Information Network Boot Network Auto Boot is a software routine contained in the 162Bug Flash/PROM that provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device. The Network Auto Boot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing a boot media is found or the list is exhausted. If a valid bootable device is found, a boot from that device is started.
Restarting the System Reset Pressing and releasing the MVME162 front panel RESET switch initiates a system reset. COLD and WARM reset modes are available. By default, 162Bug is in COLD mode. During COLD reset, a total system initialization takes place, as if the MVME162 had just been powered up. All static variables (including disk device and controller parameters) are restored to their default states. The breakpoint table and offset registers are cleared. The target registers are invalidated.
Debugger General Information Many times it may be desirable to terminate a debugger command prior to its completion; for example, during the display of a large block of memory. Break allows you to terminate the command. 3 SYSFAIL* Assertion/Negation Upon a reset/powerup condition the debugger asserts the VMEbus SYSFAIL* line (refer to the VMEbus specification).
Terminal Input/Output Control The 162Bug initial stack completely changes all 8KB of memory at addresses $FFE0C000 through $FFE0DFFF at power up or reset. Type of Memory Present A single DRAM mezzanine Default DRAM Base Address $00000000 Default SRAM Base Address FFE00000 (onboard SRAM) A single SRAM mezzanine N/A $00000000 A DRAM mezzanine stacked with an SRAM mezzanine $00000000 $E1000000 Two DRAM mezzanines stacked $00000000 $FFE00000 (onboard SRAM) DRAM can be ECC or parity type.
Debugger General Information N ote The presence of the caret ( ^ ) before a character indicates that the Control (CTRL) key must be held down while striking the character key. 3 3-12 ^X (cancel line) The cursor is backspaced to the beginning of the line. If the terminal port is configured with the hardcopy or TTY option (refer to PF command), then a carriage return and line feed is issued along with another prompt. ^H (backspace) The cursor is moved back one position.
Disk I/O Support When observing output from any 162Bug command, the XON and XOFF characters which are in effect for the terminal port may be entered to control the output, if the XON/XOFF protocol is enabled (default). These characters are initialized to ^S and ^Q respectively by 162Bug, but you may change them with the PF command. In the initialized (default) mode, operation is as follows: ^S (wait) Console output is halted. ^Q (resume) Console output is resumed.
Debugger General Information Device Probe Function A device probe with entry into the device descriptor table is done whenever a specified device is accessed; i.e., when system calls .DSKRD, .DSKWR, .DSKCFIG, .DSKFMT, and .DSKCTRL, and debugger commands BH, BO, IOC, IOP, IOT, MAR, and MAW are used. 3 The device probe mechanism utilizes the SCSI commands "Inquiry" and "Mode Sense". If the specified controller is non-SCSI, the probe simply returns a status of "device present and unknown".
Disk I/O Support IOC (I/O Control) IOC allows you to send command packets as defined by the particular controller directly. IOC can also be used to look at the resultant device packet after using the IOP command. BO (Bootstrap Operating System) BO reads an operating system or control program from the specified device into memory, and then transfers control to it. BH (Bootstrap and Halt) BH reads an operating system or control program from a specified device into memory, and then returns control to 162Bug.
Debugger General Information To perform a disk operation, 162Bug must eventually present a particular disk controller module with a controller command packet which has been especially prepared for that type of controller module. (This is accomplished in the respective controller driver module.) A command packet for one type of controller module usually does not have the same format as a command packet for a different type of module.
Network I/O Support Disk I/O Error Codes 162Bug returns an error code if an attempted disk operation is unsuccessful. Network I/O Support 3 The Network Boot Firmware provides the capability to boot the CPU through the Flash/PROM debugger using a network (local Ethernet interface) as the boot device. The booting process is executed in two distinct phases. ❏ The first phase allows the diskless remote node to discover its network identify and the name of the file to be booted.
Debugger General Information RARP/ARP Protocol Modules The Reverse Address Resolution Protocol (RARP) basically consists of an identity-less node broadcasting a "whoami" packet onto the Ethernet, and waiting for an answer. The RARP server fills an Ethernet reply packet up with the target’s Internet Address and sends it. 3 The Address Resolution Protocol (ARP) basically provides a method of converting protocol addresses (e.g., IP addresses) to local area network addresses (e.g., Ethernet addresses).
Multiprocessor Support Multiprocessor Support The MVME162 dual-port RAM feature makes the shared RAM available to remote processors as well as to the local processor. This can be done by either of the following two methods. Either method can be enabled/disabled by the ENV command as its Remote Start Switch Method (refer to Appendix A).
Debugger General Information The Multiprocessor Address Register (MPAR), located in shared RAM location of $804 offset from the base address the debugger loads it at, contains the second of two longwords used to control communication between processors. The MPAR contents specify the address at which execution for the remote processor is to begin if the MPCR contains a G or B.
Diagnostic Facilities GCSR Method A remote processor can initiate program execution in the local MVME162 dual-port RAM by issuing a remote GO command using the VMEchip2 Global Control and Status Registers (GCSR). The remote processor places the MVME162 execution address in general purpose registers 0 and 1 (GPCSR0 and GPCSR1). The remote processor then sets bit 8 (SIG0) of the VMEchip2 LM/SIG register. This causes the MVME162 to install breakpoints and begin execution.
Debugger General Information Manufacturing Test Process During the manufacturing process for MVME162 modules, the manufacturing test parameters and testing state flags are stored in NVRAM. These strings are installed during the manufacturing process and result in the product performing manufacturing tests. None of these tests harm the product or system into which a module is installed. Entering an ASCII break on the console port from a terminal terminates these tests.
USING THE 162Bug DEBUGGER 4 Entering Debugger Command Lines 162Bug is command-driven and performs its various operations in response to user commands entered at the keyboard. When the debugger prompt (162-Bug>) appears on the terminal screen, then the debugger is ready to accept commands. As the command line is entered, it is stored in an internal buffer.
Using the 162Bug Debugger The commands are shown using a modified Backus-Naur form syntax. The metasymbols used are: 4 boldface strings A boldface string is a literal such as a command or a program name, and is to be typed just as it appears. italic strings An italic string is a "syntactic variable" and is to be replaced by one of a class of items it represents.
Entering Debugger Command Lines Expression as a Parameter An expression can be one or more numeric values separated by the arithmetic operators: plus (+), minus (-), multiplied by (*), divided by (/), logical AND (&), shift left (<<), or shift right (>>). Numeric values may be expressed in either hexadecimal, decimal, octal, or binary by immediately preceding them with the proper base identifier.
Using the 162Bug Debugger Valid expression examples: Expression 4 Result (In Hex) FF0011 FF0011 45+99 DE &45+&99 90 Notes @35+@67+@10 5C %10011110+%1001 A7 88<<4 880 shift left AA&F0 A0 logical AND The total value of the expression must be between 0 and $FFFFFFFF. Address as a Parameter Many commands use ADDR as a parameter. The syntax accepted by 162Bug is similar to the one accepted by the MC68040 one-line assembler. All control addressing modes are allowed.
Entering Debugger Command Lines Table 4-1. Debugger Address Parameter Formats Format Example Description N 140 Absolute address+contents of automatic offset register. N+Rn 130+R5 Absolute address+contents of the specified offset register (not an assembler-accepted syntax). (An) (A1) Address register indirect. (also postincrement, predecrement) (d,An) or d(An) (120,A1) 120(A1) Address register indirect with displacement (two formats accepted).
Using the 162Bug Debugger N ote In commands with RANGE specified as ADDR DEL ADDR, and with size option W or L chosen, data at the second (ending) address is acted on only if the second address is a proper boundary for a word or longword, respectively. Offset Registers 4 Eight pseudo-registers (R0 through R7) called offset registers are used to simplify the debugging of relocatable and position-independent modules.
Entering Debugger Command Lines Example: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ****** ****** A portion of the listing file of an assembled, relocatable module is shown below: 0 0 0 0 0 0 0 0 00000000 00000004 00000006 00000008 0000000A 0000000C 00000010 00000014 48E78080 4280 1018 5340 12D8 51C8FFFC 4CDF0101 4E75 * * MOVE STRING SUBROUTINE * MOVESTR MOVEM.L D0/A0,—(A7) CLR.L D0 MOVE.B (A0)+,D0 SUBQ.W #1,D0 LOOP MOVE.B (A0)+,(A1)+ MOVS DBRA D0,LOOP MOVEM.
Using the 162Bug Debugger By using one of the offset registers, the disassembled code addresses can be made to match the listing file addresses as follows: 162Bug>OF R0 R0 =00000000 00000000? 1327C. 162Bug>MD 0+R0;DI 00000+R0 48E78080 00004+R0 4280 00006+R0 1018 00008+R0 5340 0000A+R0 12D8 0000C+R0 51C8FFFC 00010+R0 4CDF0101 00014+R0 4E75 162Bug> 4 MOVEM.L CLR.L MOVE.B SUBQ.W MOVE.B DBF MOVEM.
Entering and Debugging Programs Entering and Debugging Programs There are various ways to enter a user program into system memory for execution. One way is to create the program using the Memory Modify (MM) command with the assembler/disassembler option. You enter the program one source line at a time. After each source line is entered, it is assembled and the object code is loaded to memory.
Using the 162Bug Debugger If your application enables translation through the Memory Management Units (MMUs), and if your application utilizes resources of the debugger (e.g., system calls), your application must create the necessary translation tables for the debugger to have access to its various resources. The debugger honors the enabling of the MMUs; it does not disable translation.
Preserving the Debugger Operating Environment Exception Vectors Used by 162Bug The exception vectors used by the debugger are listed below. These vectors must reside at the specified offsets in the target program’s vector table for the associated debugger facilities (breakpoints, trace mode, etc.) to operate. Table 4-2.
Using the 162Bug Debugger Example: Trace one instruction using debugger. 162Bug>RD PC =00010000 SR =2700=TR:OFF_S._7_..... USP =0000DFFC MSP =0000EFFC ISP* =0000FFFC DFC =0=F0 CACR =0=........ D0 =00000000 D1 =00000000 D2 =00000000 D4 =00000000 D5 =00000000 D6 =00000000 A0 =00000000 A1 =00000000 A2 =00000000 A4 =00000000 A5 =00000000 A6 =00000000 00010000 203C0000 0001 MOVE.L #$1,D0 162Bug>T PC =00010006 SR =2700=TR:OFF_S._7_..... USP =0000DFFC MSP =0000EFFC ISP* =0000FFFC DFC =0=F0 CACR =0=........
Preserving the Debugger Operating Environment The 162Bug initializes the target vector table with the debugger vectors listed in Table 4-2 and fills the other vector locations with the address of a generalized exception handler (refer to the 162Bug Generalized Exception Handler section in this chapter). The target program may take over as many vectors as desired by simply writing its own exception vectors into the table.
Using the 162Bug Debugger The following is an example of a routine which builds a separate vector table and then moves the VBR to point at it: * *** BUILDX - Build exception vector table **** * BUILDX MOVEC.L VBR,A0 Get copy of VBR. LEA $10000,A1 New vectors at $10000. MOVE.L $80(A0),D0 Get generalized exception vector. MOVE.W $3FC,D1 Load count (all vectors). LOOP MOVE.L D0,(A1,D1) Store generalized exception vector. SUBQ.W #4,D1 BNE.B LOOP Initialize entire vector table. MOVE.
Preserving the Debugger Operating Environment The following is an example of an exception handler which can pass an exception along to the debugger: * *** EXCEPT - Exception handler **** * EXCEPT SUBQ.L #4,A7 Save space in stack for a PC value. LINK A6,#0 Frame pointer for accessing PC space. MOVEM.L A0-A5/D0-D7,-(SP) Save registers. : : decide here if your code handles exception, if so, branch... : MOVE.L BUFVBR,A0 Pass exception to debugger; Get saved VBR. MOVE.
Using the 162Bug Debugger 162Bug>RD PC =00010000 SR =2708=TR:OFF_S._7_.N... VBR =00000000 USP =0000DFFC MSP =0000EFFC ISP* =0000FFFC SFC =0=F0 DFC =0=F0 CACR =0=........ D0 =00000001 D1 =00000001 D2 =00000000 D3 =00000000 D4 =00000000 D5 =00000002 D6 =00000000 D7 =00000000 A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000 A4 =00000000 A5 =00000000 A6 =00000000 A7 =0000FFFC 00010000 203900F0 0000 MOVE.L ($F00000).
Floating Point Support Floating Point Support The floating point unit (FPU) of the MC68040 microprocessor chip is supported in 162Bug. For MVME162Bug, the commands MD, MM, RM, and RS have been extended to allow display and modification of floating point data in registers and in memory. Floating point instructions can be assembled/disassembled with the DI option of the MD and MM commands.
Using the 162Bug Debugger Single Precision Real This format would appear in memory as: 1-bit sign field (1 binary digit) 8-bit biased exponent field (2 hex digits. Bias = $7F) 23-bit fraction field 4 (6 hex digits) A single precision number takes 4 bytes in memory. Double Precision Real This format would appear in memory as: 1-bit sign field (1 binary digit) 11-bit biased exponent field (3 hex digits.
Floating Point Support Packed Decimal Real This format would appear in memory as: 4-bit sign field (4 binary digits) 16-bit exponent field (4 hex digits) 68-bit mantissa field (17 hex digits) 4 A packed decimal number takes 12 bytes in memory. Scientific Notation This format provides a convenient way to enter and display a floating point decimal number. Internally, the number is assembled into a packed decimal number and then converted into a number of the specified data type.
Using the 162Bug Debugger The 162Bug Debugger Command Set The 162Bug debugger commands are summarized in Table 4-3. The command syntax is shown using the symbols explained earlier in this chapter. The CNFG and ENV commands are explained in Appendix A. Controllers, devices, and their LUNs are listed in Appendix B or Appendix C. All other command details are explained in the MVME162Bug Debugging Package User’s Manual. Table 4-3.
The 162Bug Debugger Command Set Table 4-3.
Using the 162Bug Debugger Table 4-3.
CONFIGURE AND ENVIRONMENT COMMANDS A Configure Board Information Block CNFG [;[I][M]] This command is used to display and configure the board information block. This block is resident within the Non-Volatile RAM (NVRAM). Refer to the MVME162 Embedded Controller User’s Manual for the actual location. The information block contains various elements detailing specific operation parameters of the hardware.
A Configure and Environment Commands Serial Port 2 Personality Artwork (PWA) Identifier = " Serial Port 2 Personality Module (PWA) Serial Number = " IndustryPack A Board Identifier = " " IndustryPack A (PWA) Serial Number = " " IndustryPack A Artwork (PWA) Identifier = " " IndustryPack B Board Identifier = " " IndustryPack B (PWA) Serial Number = " " IndustryPack B Artwork (PWA) Identifier = " " IndustryPack C Board Identifier = " " IndustryPack C (PWA) Serial Number = " " IndustryPack C Artwork (PWA) Ide
Set Environment to Bug/Operating System Set Environment to Bug/Operating System ENV [;[D]] The ENV command allows you to interactively view/configure all Bug operational parameters that are kept in Battery Backed Up RAM (BBRAM), also known as Non-Volatile RAM (NVRAM). The operational parameters are saved in NVRAM and used whenever power is lost. Any time the Bug uses a parameter from NVRAM, the NVRAM contents are first tested by checksum to insure the integrity of the NVRAM contents.
A Configure and Environment Commands The parameters to be configured are listed in the following table: Table A-1. ENV Command Parameters ENV Parameter and Options Default Meaning of Default Bug or System environment [B/S] B Bug mode Field Service Menu Enable [Y/N] N Do not display field service menu.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Auto Boot Abort Delay Default Meaning of Default 15 This is the time in seconds that the Auto Boot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the Break key. The time value is from 0 through 255 seconds.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default 5 This is the time in seconds that the Network Boot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the Break key. The time value is from 0 through 255 seconds.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Memory Search Increment Size Memory Search Delay Enable [Y/N] Memory Search Delay Address Memory Size Enable [Y/N] Default Meaning of Default 00010000 This multi-CPU feature is used to offset the location of the Bug work page. This must be a multiple of the debugger work page, modulo $10000 (64KB).
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Base Address of Dynamic Memory 00000000 Beginning address of Dynamic Memory (Parity and/or ECC type memory). It must be a multiple of the Dynamic Memory board size, starting with 0. Default is $0. Size of Parity Memory 00100000 This is the size of the Parity type dynamic RAM mezzanine, if any.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Slave Ending Address #1 000FFFFF Ending address of the local resource that is accessible by the VMEbus. Default is the end of calculated memory. Slave Address Translation Address #1 00000000 This register will allow the VMEbus address and the local address to be different.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Master Starting Address #1 02000000 Base address of the VMEbus resource that is accessible from the local bus. Default is the end of calculated local memory, unless memory is less than 16MB, then this register will always be set to 01000000. Master Ending Address #1 EFFFFFFF Ending address of the VMEbus resource that is accessible from the local bus.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Master Starting Address #3 00000000 Base address of the VMEbus resource that is accessible from the local bus. If enabled, the value is calculated as one more than the calculated size of memory. If not enabled, the default is $00000000. Master Ending Address #3 00000000 Ending address of the VMEbus resource that is accessible from the local bus.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Short I/O (VMEbus A16) Enable [Y/N] Y Yes, Enable the Short I/O Address Decoder. Short I/O (VMEbus A16) Control 01 Defines the access characteristics for the address space defined with the Short I/O address decoder. Default is $01. F-Page (VMEbus A24) Enable [Y/N] Y Yes, Enable the F-Page Address Decoder.
Set Environment to Bug/Operating System Configuring the IndustryPacks ENV asks the following series of questions to set up IndustryPacks (IP) on MVME162 modules. The MVME162 Embedded Controller Programmer’s Reference Guide describes the base addresses and the IP register settings. Refer to that manual for information on setting base addresses and register bits.
A Configure and Environment Commands IP D/C/B/A Interrupt 0 Control = 00000000? Define the interrupt control requirements for the IP modules channel 0: Bits IP Register Address 31-24 D FFFBC016 23-16 C FFFBC014 15-08 B FFFBC012 07-00 A FFFBC010 IP D/C/B/A Interrupt 1 Control = 00000000? Define the interrupt control requirements for the IP modules channel 1: A-14 Bits IP Register Address 31-24 D FFFBC017 23-16 C FFFBC015 15-08 B FFFBC013 07-00 A FFFBC011 MVME162 Embedded C
DISK/TAPE CONTROLLER DATA B Disk/Tape Controller Modules Supported The following VMEbus disk/tape controller modules are supported by the 162Bug. The default address for each controller type is First Address and the controller can be addressed by First CLUN during commands BH, BO, or IOP, or during TRAP #15 calls .DSKRD or .DSKWR.
Disk/Tape Controller Data B Disk/Tape Controller Default Configurations SCSI Common Command Set (CCS) devices are only the ones tested by Motorola Computer Group.
Disk/Tape Controller Default Configurations MVME323 -- 4 Devices Controller LUN Address 8 $FFFFA000 9 $FFFFA200 B Device LUN 0 1 2 3 Device Type ESDI Winchester hard drive ESDI Winchester hard drive ESDI Winchester hard drive ESDI Winchester hard drive MVME327A -- 9 Devices Controller LUN Address 2 $FFFFA600 3 $FFFFA700 MVME162IG/D2 Device LUN Device Type 00 10 20 30 40 50 60 SCSI Common Command Set (CCS), which may be any of these: 80 81 Local floppy drive - Fixed direct access - Remo
Disk/Tape Controller Data MVME328 -- 14 Devices B Controller LUN Address 6 $FFFF9000 7 $FFFF9800 16 $FFFF4800 17 $FFFF5800 18 $FFFF7000 19 $FFFF7800 Device LUN Device Type 00 08 10 18 20 28 30 SCSI Common Command Set (CCS), which may be any of these: - Removable flexible direct access (TEAC style) - CD-ROM - Sequential access 40 48 50 58 60 68 70 Same as above, but these will only be available if the daughter card for the second SCSI channel is present.
IOT Command Parameters for Supported Floppy Types IOT Command Parameters for Supported Floppy Types The following table lists the proper IOT command parameters for floppies used with boards such as the MVME328 and MVME162.
Disk/Tape Controller Data B B-6 MVME162 Embedded Controller Installation Guide
NETWORK CONTROLLER DATA C Network Controller Modules Supported The following VMEbus network controller modules are supported by the MVME162Bug. The default address for each type and position is showed to indicate where the controller must reside to be supported by the MVME162Bug. The controllers are accessed via the specified CLUN and DLUNs listed here.
Network Controller Data C C-2 MVME162 Embedded Controller Installation Guide
Index When using this index, keep in mind that a page number indicates only where referenced material begins. It may extend to the page or pages following the page referenced.
Index baud rates 1-15, 3-5 BBRAM (Battery Backed Up RAM) (see MK48T08 and NVRAM) 1-14 BG (bus grant) 2-10 BH (Bootstrap and Halt) 3-14 binary number 1-8 block diagram 1-9 block size, logical 3-13 blocks versus sectors 3-13 BO (Bootstrap Operating System) 3-14 Board Information Block (BIB) A-1 board level hardware description 1-1 Board Mode, 162Bug 3-4 boldface strings 4-2 BOOTP protocol module 3-18 Bootstrap and Halt (BH) 3-14 Bootstrap Operating System) 3-14 Bootstrap Protocol (BOOTP) 3-18 braces 4-2 brea
debugger general information 3-1 debugger prompt 4-1 debugger, description 3-1 decimal number 1-8 decoder, GCSR 1-25 default 162Bug controller and device parameters 3-16 default baud rate (see baud rates) 3-5 delimiter 4-2 description of 162Bug 3-1 device LUN (DLUN) B-2, C-1 device probe function 3-14 diagnostics 3-1, 3-21 direct access device B-2, B-4 directories switching 3-21 disk I/O commands, 162Bug 3-14 disk I/O error codes 3-17 disk I/O support, 162Bug 3-13 disk I/O via 162Bug commands 3-14 disk I/O
Index F facilities 3-21 FAIL LED 1-10 false 1-8 features 1-5 firmware overview 3-1 Flash (see 28F020 Flash) 3-3 Flash memory 1-14 Flash memory, programming 3-19 flexible diskette B-2 floating point instructions 4-17 floating point support 4-17 floating point unit (FPU) 4-17 floppy disk command parameters B-5 floppy diskette B-4 floppy drive B-2, B-3 four-byte 1-8 FPU (floating point unit) 4-17 front panel 1-10 front panel switches and iIndicators 1-10 functional description 1-10 fuse (F1) 2-12 fuse (F2) 2-
Interrupt Stack Pointer (ISP) 3-11 interrupts, programmable 1-19 introduction 1-1, 2-1 IOC (I/O Control) 3-15 IOI (Input/Output Inquiry) 3-14 IOP (Physical I/O to Disk) 3-14 IOT (I/O Teach) 3-14 IOT command parameters B-5 IOT command parameters for supported floppy types B-5 IP (Industry Pack) installation on the MVME162 2-9 ISP (Interrupt Stack Pointer) 3-11 italic strings 4-2 J J1 jumper 2-5 J11 jumpers 2-6, 3-5 J12 jumpers 2-6, 3-5 J20 jumpers 2-7 J21 jumper 2-7, 3-5 J22 jumpers 2-8, 3-5, 3-10 jumpers,
Index multiprocessor support 3-19 MVME162 1-1, C-1 MVME162 block diagram 1-9 MVME162 connection diagrams 2-13 MVME162 module installation 2-10 MVME162 specifications 1-6 MVME162 switches, headers, connectors, fuses, and LEDs 2-3 MVME162Bug 3-1 MVME162Bug debugging package (see 162Bug and debug monitor) 1-2, 2-2 MVME320 B-2 MVME323 B-3 MVME327A B-3 MVME328 B-4 MVME350 B-4 MVME374 C-1 MVME376 C-1 MVME712-12 1-1 MVME712-13 1-1 MVME712A 1-1 MVME712AM 1-1 MVME712B 1-1 MVME712M 1-1, 2-10 MVME712X 1-1 MVME712X co
Q QIC-02 streaming tape drive B-4 R range 4-2 RARP/ARP protocol 3-18 readable jumpers 2-8 registers used in debugging 4-6 related documentation 1-2 relative address+offset 4-6 requirements 1-5 RESET switch 1-10, 3-9 restarting the system 3-8 Reverse Address Resolution Protocol (RARP) 3-18 RFI 2-10 ROMboot 3-7 RUN LED 1-10 S SCC (Serial Communications Controller) (see Z85230) 1-15, 3-6 scientific notation 4-19 SCON LED 1-10 SCSI Common Command Set (CCS) B-2, B-4 SCSI Controller (53C710) 1-18 SCSI interface
Index switching 3-21 switching directories (see also SD command) 3-21 sync/async protocols 1-15 synchronous clock select header (J11) 2-6 syntactic variables 4-2 SYSFAIL* 3-10 system calls, TRAP #15 3-15 system considerations 2-11 system console 3-5 system controller function 3-4 system controller select header (J1) 2-5 System Fail (SYSFAIL*) 3-7 System Mode, 162Bug 3-4 system routines 4-9 T I N D E X target vector table (see using 162Bug target vector table) 4-12 temperature, high 1-7 terminal input/ou
