MVME187 RISC Single Board Computer Installation Guide MVME187IG/D4
Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Preface This manual provides a general board level hardware description, hardware preparation and installation instructions, debugger general information, and information about using the debugger.
Safety Summary Safety Depends On You The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with speciÞc warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the customer's failure to comply with these requirements.
All Motorola PWBs (printed wiring boards) are manufactured by UL-recognized manufacturers, with a ßammability rating of 94V-0. ! WARNING This equipment generates, uses, and can radiate electromagnetic energy. It may cause or be susceptible to electro-magnetic interference (EMI) if not installed and used in a cabinet with adequate EMI protection. European Notice: Board products with the CE marking comply with the EMC Directive (89/336/EEC).
Contents This Chapter Covers 1-1 About this Manual 1-1 Terminology, Conventions, and DeÞnitions Used in this Manual 1-2 Data and Address Parameter Numeric Formats 1-2 Signal Name Conventions 1-2 Assertion and Negation Conventions 1-3 Data and Address Size DeÞnitions 1-3 Big-Endian Byte Ordering 1-3 Control and Status Bit DeÞnitions 1-4 True/False Bit State DeÞnitions 1-4 Bit Value Descriptions 1-4 Related Documentation 1-5 Document Set for MVME187-0xx Board 1-5 Additional Manuals for this Board 1-6 Other Ap
MCECC Memory Controller ASIC 2-10 Functional Description 2-10 Front Panel Switches and LEDs 2-11 Data Bus Structure 2-12 Local Bus Arbitration 2-12 M88000 MPU 2-12 EPROM 2-13 Programmable EPROM Features 2-13 Static RAM 2-13 Optional SRAM Battery Backup 2-14 Onboard DRAM 2-15 Stacking Mezzanines 2-16 DRAM Programming Considerations 2-16 Battery Backed Up RAM and Clock 2-17 VMEbus Interface 2-18 I/O Interfaces 2-18 Serial Port Interface 2-18 Parallel Port Interface 2-20 Ethernet Interface 2-21 SCSI Interface
Jumper Settings 3-7 Optional Jumper Settings 3-8 General Purpose Software Readable Header J1 3-8 System Controller Header J2 3-10 Optional SRAM Backup Power Source Select Header J6 3-11 Serial Port 4 Clock Configuration Select Headers J7 and J8 3-11 Preparing the MVME187 for Installation 3-14 Preparing the System Chassis 3-15 Installing the Hardware 3-16 Installing the MVME187 in the Chassis 3-16 Transition Modules and Adapter Boards Overview 3-17 Equipment Connections 3-19 Installing Transition Modules and
Booting and Restarting 187Bug 4-5 Starting Up 187Bug 4-6 Autoboot 4-6 Autoboot Sequence 4-6 ROMboot 4-7 ROMboot Sequence 4-7 Network Boot 4-8 Network Boot Sequence 4-8 Restarting the System 4-9 Reset 4-10 Abort 4-10 Break 4-11 SYSFAIL* Assertion/Negation 4-12 MPU Clock Speed Calculation 4-12 Disk I/O Support 4-13 Disk Support Facilities 4-13 Parameter Tables 4-13 Supported Controllers 4-13 Blocks Versus Sectors 4-14 Device Probe Function 4-14 Disk I/O via 187Bug Commands 4-15 IOI (Input/Output Inquiry) 4-15
MPCR Status Codes 4-22 Multiprocessor Address Register (MPAR) 4-22 MPCR Powerup Sequence 4-22 Global Control and Status Register (GCSR) Method 4-24 Diagnostic Facilities 4-25 187Bug Diagnostic Test Groups 4-27 This Chapter Covers 5-1 Entering Debugger Command Lines 5-1 Terminal Input/Output Control 5-1 Debugger Command Syntax 5-3 Syntactic Variables 5-4 Expression as a Parameter 5-4 Address as a Parameter 5-5 Address Formats 5-6 Offset Registers 5-7 Port Numbers 5-7 Entering and Debugging Programs 5-8 Creat
Signal Adaptations E-4 Sample ConÞgurations E-4 Proper Grounding E-7
List of Figures MVME187 General Block Diagram 2-7 MVME187 Switches, Headers, Connectors, Fuses, and LEDs 3-6 Typical Internal SCSI and Serial Port Connections 3-18 Using MVME712A/AM and MVME712B 3-22 Typical Transition Module Peripheral Port Connectors 3-23
List of Tables MVME187 General SpeciÞcations 2-6 Bus Transfers 2-9 Front Panel Switches 2-11 Front Panel LEDs 2-11 Local Bus Memory Map 2-25 Local I/O Devices Memory Map 2-26 Startup Overview 3-2 J1 Bit Descriptions 3-9 Factory Settings for J1 General Purpose Readable Jumpers 3-9 Settings for J2 System Controller Header 3-10 Settings for Optional J6 SRAM Backup Power Source Select Header 3-12 Settings for J7 and J8 Serial Port 4 Clock ConÞguration Select Headers 3-13 MVME187 Preparation Procedure 3-14 Chass
1Introduction to the MVME187 Installation Guide 1 This Chapter Covers ❏ Details about this manual ❏ Terminology, conventions, and definitions used ❏ Other publications relevant to the MVME187 About this Manual This manual supports the setup, installation, and debugging of the RISC-based MVME187 Single Board Computer; a highperformance engine for VMEbus-based low- and mid-range OEM and integrated systems, embedded controllers, and other singleboard computer applications.
1 Introduction to the MVME187 Installation Guide Terminology, Conventions, and Definitions Used in this Manual Data and Address Parameter Numeric Formats Throughout this manual, a character identifying the numeric format precedes data and address parameters as follows: $ % & dollar percent ampersand speciÞes a hexadecimal character speciÞes a binary number speciÞes a decimal number For example, Ò12Ó is the decimal number twelve, and Ò$12Ó is the decimal number eighteen.
Terminology, Conventions, and Definitions Used in this Manual Assertion and Negation Conventions Assertion and negation are used to specify forcing a signal to a particular state. These terms are used independently of the voltage level (high or low) that they represent. Term Indicates Assertion and assert The signal is active or true. Negation and negate The signal is inactive or false.
1 Introduction to the MVME187 Installation Guide Control and Status Bit Definitions The terms control bit and status bit are used extensively in this document to describe certain bits in registers. Term Describes Control bit The bit can be set and cleared under software control. Status bit ❏ The bit reflects a specific condition. The status bit can be read by software to determine operational or exception conditions.
Related Documentation Related Documentation The MVME187 ships with a start-up installation guide (MVME187IG/D, the document you are presently reading) which includes installation instructions, jumper configuration information, memory maps, debugger/monitor commands, and any other information needed for start-up of the board.
1 Introduction to the MVME187 Installation Guide Motorola Publication Number SBCSCSI/D Description Single Board Computers SCSI Software UserÕs Manual Additional Manuals for this Board Also available but not included in the set: Motorola Publication Number Description MVME187IG/D MVME187 RISC Single Board Computer Installation Guide (this manual) SIMVME187/D MVME187 RISC Single Board Computer Support Information The SIMVME187 manual contains the connector interconnect signal information, parts list
Related Documentation Motorola Publication Number Description MC88100UM MC88100 RISC Microprocessor User's Manual MC88200UM MC88200 Cache/Memory Management Unit (CMMU) User's Manual MC88204 MC88204 64K-Byte Cache/Memory Management Unit (CMMU) data sheet A Non-Motorola Peripheral Controllers Publications Bundle For your convenience, we have collected user's manuals for each of the peripheral controllers used on the MVME187 from the suppliers.
1 Introduction to the MVME187 Installation Guide Part Number 1-8 Description MK48T08/18B SGS-THOMSON MK48T08 Time Clock/NVRAM Data Sheet MC68230/D MC68230 Parallel Interface Timer (PI/T) Data Sheet SBCCOMPS/L Customer Letter for Component Alternatives
Related Documentation Applicable Non-Motorola Publications The following non-Motorola publications are also available from the sources indicated. Document Title Versatile Backplane Bus: VMEbus, ANSI/IEEE Std 1014-1987 (VMEbus SpeciÞcation) (This is also Microprocessor System Bus for 1 to 4 Byte Data, IEC 821 BUS) Source The Institute of Electrical and Electronics Engineers, Inc. 345 East 47th St.
1 Introduction to the MVME187 Installation Guide 1-10
2Board Level Hardware Description 2 This Chapter Covers ❏ A general description of the MVME187 RISC Single Board Computer ❏ Features and specifications ❏ A board-level hardware overview ❏ A detailed hardware functional description, including front panel switches and indicators ❏ Memory maps General Description The MVME187 is a high functionality VMEbus RISC single board computer designed around the M88000 chip set.
Board Level Hardware Description 2 Onboard Memory Mezzanine Module The MVME187 onboard DRAM mezzanine boards are available in different sizes and with programmable parity protection or Error Checking and Correction (ECC) protection. ❏ The main board and a single mezzanine board together take one slot. ❏ Motorola software supports mixed parity and ECC memory boards on the same main board.
General Description Serial Ports 2 The serial ports support standard baud rates of 110 to 38.4K baud.
Board Level Hardware Description 2 187Bug Firmware The MVME187Bug debug monitor firmware (187Bug) is provided in two of the four EPROM sockets on the MVME187. It provides: ❏ Over 50 debug commands ❏ Up/down load commands ❏ Disk bootstrap load commands ❏ A full set of onboard diagnostics ❏ A one-line assembler/disassembler The 187Bug user interface accepts commands from the system console terminal. 187Bug can also operate in a System Mode, which includes choices from a service menu.
Features ❏ RESET and ABORT switches ❏ Four 32-bit tick timers for periodic interrupts ❏ Watchdog timer ❏ Eight software interrupts ❏ I/O 2 Ð SCSI Bus interface with DMA Ð Four serial ports with EIA-232-D buffers with DMA Ð Centronics printer port Ð Ethernet transceiver interface with DMA ❏ VMEbus interface Ð VMEbus system controller functions Ð VMEbus interface to local bus (A24/A32, D8/D16/D32 and D8/D16/D32/D64BLT) (BLT = Block Transfer) Ð Local bus to VMEbus interface (A16/A24/A32, D8/D16/D3
Board Level Hardware Description 2 Specifications Table 2-1. MVME187 General Specifications Characteristics Power requirements (with all four EPROM sockets populated and excluding external LAN transceiver) SpeciÞcations +5 Vdc (+/-5%) 3.5 A (typical), 4.5 A (maximum) (at 25 MHz, with 32MB parity DRAM) 5.0 A (typical), 6.5 A (maximum) (at 33 MHz, with 128MB ECC DRAM) +12 Vdc (+/-5%) 100 mA (maximum) (1.
Board Level Overview Board Level Overview 82596CA LAN ETHERNET M88000 53C710 SCSI 2 CD2401 SCC SERIAL IO PRINTER PORT PCCchip2 DRAM VMEchip2 EPROM MK48T08 BBRAM & CLOCK VMEbus 128KB STATIC RAM bd069 9211 Figure 2-1. MVME187 General Block Diagram Connectors The MVME187 has two 96-position DIN connectors: P1 and P2. ❏ P1 rows A, B, C, and P2 row B provide the VMEbus interconnection. ❏ P2 rows A and C provide the connection to the SCSI bus, serial ports, Ethernet, and printer.
Board Level Hardware Description 2 Transition Modules MVME712X transition modules provide configuration headers and provide industry standard connectors for the I/O devices. Refer to Figure 3-3 on page 3-22. ❏ The MVME187 supports the transition modules MVME71212, MVME712-13, MVME712M, MVME712A, MVME712AM, and MVME712B (referred to in this manual as MVME712X, unless separately specified).
Board Level Overview VMEchip2 ASIC 2 Provides the VMEbus interface. The VMEchip2 includes: ❏ Two tick timers ❏ Watchdog timer ❏ Programmable map decoders for the master and slave interfaces, and a VMEbus to/from local bus DMA controller ❏ VMEbus to/from local bus non-DMA programmed access interface ❏ VMEbus interrupter ❏ VMEbus system controller ❏ VMEbus interrupt handler ❏ VMEbus requester Table 2-2. Bus Transfers Transfer type Can be...
Board Level Hardware Description 2 MEMC040 Memory Controller ASIC The MEMC040 memory controller ASIC provides the programmable interface for the parity-protected DRAM mezzanine board. MCECC Memory Controller ASIC The MCECC memory controller ASIC provides the programmable interface for the ECC-protected DRAM mezzanine board.
Functional Description Front Panel Switches and LEDs 2 There are two switches and eight LEDs on the boardÕs front panel (refer to Table 2-3, Table 2-4, and Figure 3-1 on page 3-6). Table 2-3. Front Panel Switches Switch Name Description RESET The RESET switch resets all onboard devices and drives SYSRESET* if the board is system controller. The RESET switch may be disabled by software. ABORT When enabled by software, the ABORT switch generates an interrupt at a userprogrammable level.
Board Level Hardware Description 2 Data Bus Structure The local data bus on theMVME187 is a 32-bit synchronous bus based on the MC68040 bus, and supports burst transfers and snooping. Local Bus Arbitration The various local bus master and slave devices use the local bus to communicate. The local bus is arbitrated by priority type arbiter and the priority of the local bus masters from highest to lowest is: 1. 82596CA LAN (highest) 2. CD2401 serial (through the PCCchip2) 3. 53C710 SCSI 4. VMEbus 5.
Functional Description EPROM 2 Four 44-pin PLCC/CLCC EPROM sockets for 27C102JK or 27C202JK type EPROMs. They are: ❏ Organized in two 32-bit wide banks supporting 8-, 16-, and 32-bit read accesses ❏ Controlled by the VMEchip2 ❏ Mapped to local bus address 0 following a local bus reset Ð This allows the MC88100 to start executing code at address 0 following a reset.
Board Level Hardware Description 2 Optional SRAM Battery Backup SRAM battery backup is optionally available on the MVME187, but only as a factory build and only by special request. (Contact your local Motorola sales office for details). The battery backup function, provided by a Dallas DS1210S nonvolatile controller chip and a RAYOVAC FB1225 battery, supports primary and secondary power sources.
Functional Description ! Caution Lithium batteries incorporate inflammable materials such as lithium and organic solvents. If lithium batteries are mistreated or handled incorrectly, they may burst open and ignite, possibly resulting in injury and/or fire. 2 When dealing with lithium batteries, carefully follow the precautions listed below in order to prevent accidents. ❏ Do not short circuit. ❏ Do not disassemble, deform, or apply excessive pressure. ❏ Do not heat or incinerate.
Board Level Hardware Description Motorola software does support mixed parity and ECC memory boards on the same main board. 2 The DRAM is four-way interleaved to efficiently support cache burst cycles. Onboard DRAM mezzanines are available in these configurations: ❏ 4, 8, 16, or 32MB with parity protection ❏ 4, 8, 16, 32, 64, or 128 MB with ECC protection Stacking Mezzanines Two mezzanine boards may be stacked to provide up to 256MB of onboard RAM (ECC).
Functional Description Battery Backed Up RAM and Clock 2 The MK48T08 RAM and clock chip is a 28-pin package that provides ❏ A time-of-day clock ❏ An oscillator ❏ A crystal ❏ Power fail detection ❏ Memory write protection ❏ 8KB of RAM ❏ A battery The clock provides ❏ Seconds, minutes, hours, day, date, month, and year in BCD 24-hour format ❏ Automatic corrections for 28-, 29- (leap year), and 30-day months No interrupts are generated by the clock.
Board Level Hardware Description 2 VMEbus Interface The VMEchip2 provides: ❏ Local bus to VMEbus interface ❏ VMEbus to local bus interface ❏ Local-VMEbus DMA controller functions ❏ VMEbus system controller functions I/O Interfaces The MVME187 provides onboard I/O for many system applications.
Functional Description All four serial ports use EIA-232-D drivers and receivers located on the MVME187, and all the signal lines are routed to the I/O connector. ❏ Serial port 1 is a minimum function asynchronous port. It uses RXD, CTS, TXD, and RTS. ❏ Serial ports 2 and 3 are full function asynchronous ports. They use RXD, CTS, DCD, TXD, RTS, and DTR. ❏ Serial port 4 is a full function asynchronous or synchronous port. It can operate at synchronous bit rates up to 64 k bits per second.
Board Level Hardware Description 2 Parallel Port Interface The PCCchip2 provides an 8-bit bidirectional parallel port. This port may be used as a Centronics-compatible parallel printer port or as a general parallel I/O port. All eight bits of the port must be either inputs or outputs (no individual bit selection). In addition to the 8 bits of data, there are two control pins and five status pins.
Functional Description The PCCchip2 provides an auto-strobe feature similar to that of the MVME147 PCC. ❏ In auto-strobe mode, after a write to the Printer Data Register, the PCCchip2 automatically asserts the STROBE* pin for a selected time specified by the Printer Fast Strobe control bit. ❏ In manual mode, the Printer Strobe control bit directly controls the state of the STROBE* pin. Ethernet Interface The 82596CA implements the Ethernet transceiver interface.
Board Level Hardware Description Buffer Overruns 2 Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus. Support functions for the 82596CA are provided by the PCCchip2. Refer to the 82596CA user's guide for detailed programming information.
Functional Description Local Resources 2 The MVME187 includes many resources for the local processor. These include tick timers, software programmable hardware interrupts, watchdog timer, and local bus timeout. Programmable Tick Timers Four 32-bit programmable tick timers with 1 µs resolution are provided, two in the VMEchip2 and two in the PCCchip2. The tick timers can be programmed to generate periodic interrupts to the processor. Watchdog Timer A watchdog timer function is provided in the VMEchip2.
Board Level Hardware Description 2 Memory Maps There are two points of view for memory maps: 1. Local bus memory map Ð the mapping of all resources as viewed by local bus masters 2. VMEbus memory map Ð the mapping of onboard resources as viewed by VMEbus Masters Local Bus Memory Map The local bus memory map is split into different address spaces by the transfer type (TT) signals. The local resources respond to the normal access and interrupt acknowledge codes.
Memory Maps Table 2-5.
Board Level Hardware Description The following table focuses on the Local I/O Devices portion of the local bus Main Memory Map. 2 Table 2-6.
Memory Maps Table 2-6. Local I/O Devices Memory Map (Continued) Address Range $FFFE000B $FFFE000F $FFFE0013 $FFFE0017 $FFFE001B $FFFE001F $FFFE0020 - $FFFEFFFF Devices Accessed IACK LEVEL 2 IACK LEVEL 3 IACK LEVEL 4 IACK LEVEL 5 IACK LEVEL 6 IACK LEVEL 7 IACK LEVELS (repeated) Port Size D8 D8 D8 D8 D8 D8 -- Size 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 64KB Notes 2 2 2 2 2 2 2,6 Notes 1.
Board Level Hardware Description 2 VMEbus Memory Map This section describes the mapping of local resources as viewed by VMEbus masters. Default addresses for the slave, master, and GCSR address decoders are provided by the ENV command. Refer to Appendix A. VMEbus Accesses to the Local Bus The VMEchip2 includes a user-programmable map decoder for the VMEbus to local bus interface. The map decoder allows you to program the starting and ending address and the modifiers the MVME187 responds to.
3Hardware Preparation and Installation 3 This Chapter Covers This chapter provides instructions on: ❏ Unpacking the equipment ❏ Preparing the hardware ❏ Installing the MVME187 RISC Single Board Computer Note that hardware preparation instructions for the MVME712X transition module are provided in separate userÕs manuals for each model. Refer to the userÕs manual you received with your MVME712X.
Hardware Preparation and Installation Overview of Startup Procedure The following list identifies the things you will need to do before you can use this board, and where to find the information you need to perform each step. Be sure to read this chapter and all Caution notes, and have the related documentation with you before you begin. 3 Table 3-1. Startup Overview Stage 1 2 What you will need to do... Refer to... On page...
Overview of Startup Procedure Table 3-1. Startup Overview (Continued) Stage 4 What you will need to do... Refer to... On page... Install adapter boards and transition modules. Transition Modules and Adapter Boards Overview 3-17 Installing Transition Modules and Adapter Boards 3-20 Set jumpers on the transition module(s). Connect and install the MVME712X transition module. The userÕs manual you received with your MVME712X Connect and install the P2 adapter board. 5 Connect peripherals.
Hardware Preparation and Installation Table 3-1. Startup Overview (Continued) Stage 3 7 What you will need to do... Refer to... On page... Starting the System 3-24 Power up the system. Front Panel Switches and LEDs 2-11 Initialize the real-time clock. Initializing the Real-Time Clock 3-25 Note that the debugger prompt appears. Powering Up the System 3-25 Starting Up 187Bug 4-6 Start up the system.
Preparing the Hardware Preparing the Hardware This section covers: ❏ Modifying hardware configurations before installation ❏ Checking the 187Bug EPROMs ❏ Factory jumper settings ❏ Preparing your MVME187 ❏ Preparing the system chassis 3 Modifying Configuration before Installation To select the desired configuration and ensure proper operation of the MVME187, certain option modifications may be necessary before installation.
Hardware Preparation and Installation MVME 187 28 29 39 40 28 29 39 40 28 29 A1 B1 C1 XU4 SKT 1 XU3 SKT 1 XU2 1 7 18 17 6 7 18 17 6 7 18 17 6 7 J2 DS3 16 1 2 SCSI VME 18 17 6 DS2 39 40 DS1 XU1 RUN SCON 28 29 J1 F1 P1 5 1 J6 2 6 (OPTIONAL) 19 20 J3 A32 B32 C32 1 2 F2 S1 S2 60 59 J4 A1 B1 C1 60 59 MEZZANINE BOARD 2 1 P2 J5 2 1 A32 B32 C32 J7 3 1 3 1 J8 1380 9404 3-6 PRIMARY SIDE RESET COMPONENTS ARE REMOVED FOR CLARITY ABORT 15 LAN +12V 39 40
Preparing the Hardware Checking the 187Bug EPROMs Be sure that the two factory installed 128K x 16 187Bug EPROMs are in the proper sockets.
Hardware Preparation and Installation Optional Jumper Settings Most of the optional functions on your board can be changed through software control or bit settings in control registers. If your installation requires it, however, you may change jumper settings on the following headers: 3 ❏ Jumper pins 9 through 16 on header J1 are general purpose software readable jumpers open to your application. ❏ Header J2 enables/disables the MVME187 as system controller.
Preparing the Hardware Table 3-2. J1 Bit Descriptions Bit J1 Pins Description Bit #0 (GPI0) 1-2 When this bit is a one (high), it instructs the debugger to use local Static RAM for its work page (i.e., variables, stack, vector tables, etc.). This bit will be high when jumper is removed. Bit #1 (GPI1) 3-4 When this bit is a one (high), it instructs the debugger to use the default setup/operation parameters in ROM versus the user setup/operation parameters in NVRAM.
Hardware Preparation and Installation System Controller Header J2 The MVME187 can be VMEbus system controller. The system controller function is enabled by installing a jumper on header J2 (see Table 3-4). When the MVME187 is system controller, the SCON LED is turned on. 3 Table 3-4.
Preparing the Hardware Optional SRAM Backup Power Source Select Header J6 Header J6 is an optional header used to select the SRAM backup power source on the MVME187, if the optional battery is present. (The battery backup for SRAM is optionally available, but only as a factory build and only by special request.) ! Caution If your system is equipped with the optional battery backup, do not remove the jumpers from J6. This will disable the SRAM.
Hardware Preparation and Installation Table 3-5.
Preparing the Hardware Table 3-6.
Hardware Preparation and Installation Preparing the MVME187 for Installation Refer to the setup procedures in the manuals for your particular chassis or system for additional details concerning the installation of the MVME187 into a VME chassis. 3 Table 3-7. MVME187 Preparation Procedure Step Action 1 Install/remove jumpers on headers according to the Jumper Settings in this chapter and as required for your particular application.
Preparing the Hardware Preparing the System Chassis Now that the MVME187 module is ready for installation, prepare the system chassis and determine slot assignments (for peripherals, transition modules, etc.) as follows: Inserting or removing modules while power is applied could result in damage to module components. ! Caution ! Warning Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. Table 3-8.
Hardware Preparation and Installation Installing the Hardware This section covers 3 ❏ Installation of the MVME187 into a VME chassis ❏ Overview and installation of transition modules and adapter boards ❏ Connection of peripheral equipment such as console terminals, optional SCSI drives, and serial or parallel printers Installing the MVME187 in the Chassis Note that if the MVME187 is to be used as system controller, it must installed in the left-most card slot (slot 1), otherwise it may be installed
Installing the Hardware Transition Modules and Adapter Boards Overview The MVME187 supports the MVME712-12, MVME712-13, MVME712M, MVME712A, MVME712AM, and MVME712B transition modules (referred to in this manual as MVME712X, unless separately specified). Note 3 Other modules in the system may have to be moved to allow space for the MVME712M which has a doublewide front panel. MVME712X transition modules provide configuration headers and industry-standard connectors for internal and external I/O devices.
Hardware Preparation and Installation MVME712X TERMINATOR MVME187 3 P1 LC P2 ADAPTER J2 P2 P2 J3 J2, P2, OR J11 ENCLOSURE BOUNDARY 1859 9609 Figure 3-2.
Installing the Hardware Equipment Connections Some connection diagrams are in the Single Board Computer Programmer's Reference Guide. The MVME712X transition modules and P2 adapter boards connect peripheral equipment to the MVME187 as shown in Table 3-10. Table 3-10. Peripheral Connections Equipment Type Connect Through...
Hardware Preparation and Installation Installing Transition Modules and Adapter Boards 3 Table 3-11. Transition Module and Adapter Board Installation Overview Stage What you will need to do... Refer to... 1 Set jumpers on the transition module(s) and install SCSI terminators (if needed) on the P2 adapter board.
Installing the Hardware Table 3-12. Peripheral Connection Procedures Step Action... Refer to... 1 Connect and install any optional SCSI device cables from J3 on the P2 Adapter to internal devices and/or the MVME712B or MVME712M to external SCSI devices (typical conÞgurations shown in Figure 3-2 on page 3-18 and Figure 3-3 on page 3-22).
Hardware Preparation and Installation In order for high-baud rate serial communication between 187Bug and the terminal to work, the terminal must do some form of handshaking. If the terminal being used does not do hardware handshaking via the CTS line, then it must do XON/XOFF handshaking. If you get garbled messages and missing characters, you should check the terminal to make sure XON/XOFF handshaking is enabled.
Installing the Hardware MVME 712A/12/13 SERIAL PORT 1 TTY01 SERIAL PORT 2 To J10 on Transition Module SERIAL PORT 3 SERIAL PORT 4 MVME 712A (MVME712M similar) Optional Modem Port 3 ETHERNET CONSOLE MVME 712B MVME 712B (if used) To J2 on Adapter Board SCSI INTERFACE PRINTER Figure 3-4.
Hardware Preparation and Installation Completing the Installation Table 3-13. Installation Completion Procedure 3 Step Action... 1 Reassemble the chassis. 2 Reconnect the AC power. Starting the System After completing the preparation and installation procedures, you are ready to start up your system. Table 3-14. System Startup Overview Stage What you will need to do... Refer to... 1 Power up the system and note that the debugger prompt appears.
Installing the Hardware Powering Up the System The following table shows what takes place when you turn equipment power ON (depending on whether 187Bug is in Board Mode or in System Mode): If 187Bug is in... Board Mode 187Bug executes some self-checks and displays the debugger prompt 187-Bug> System Mode The system performs a selftest and tries to autoboot. If the conÞdence test fails, the test aborts when the Þrst fault occurs.
Hardware Preparation and Installation Table 3-15. RTC Initialization Procedure Step 3 Action Board Mode System Mode 1 Allow 187Bug to boot up normally. Stop the auto-boot sequence by pressing the key. (If the system has already started and failed a conÞdence test in system mode, you should be in the debugger menu). 2 At the 187-Bug> prompt, enter TIME to display the current date and time of day. Select (3) from the debugger menu to get the debugger prompt.
System Considerations System Considerations Backplane Power Connections The MVME187 needs to draw power from both P1 and P2 of the VMEbus backplane. P2 is also used for the upper 16 bits of data for 32-bit transfers, and for the upper 8 address lines for extended addressing mode. The MVME187 may not operate properly without its main board connected to P1 and P2 of the VMEbus backplane.
Hardware Preparation and Installation Multiple Module Cage Configuration Multiple MVME187s may be configured into a single VME card cage. In general, hardware multiprocessor features are supported. 3 GCSR Location Monitor Register Other MPUs on the VMEbus can interrupt, disable, communicate with and determine the operational status of the RISC processor(s).
System Considerations SCSI Bus Termination ❏ The MVME187 provides SCSI terminator power through a 1amp fuse (F1) located on the P2 adapter board. The fuse is socketed. If the fuse is blown, the SCSI devices may not operate or may function erratically. ❏ When the P2 adapter board is used with an MVME712M and the SCSI bus is connected to the MVME712M, the green LED (DS2) on the MVME712M front panel lights when there is SCSI terminator power.
Hardware Preparation and Installation 3 3-30
4Debugger General Information 4 This Chapter Covers ❏ An introduction to the MVME187Bug firmware package ❏ Booting and restarting 187Bug ❏ Disk input/output support capabilities ❏ Network support capabilities Introduction to MVME187Bug This section covers: ❏ Overview of M88000 firmware ❏ Description of 187Bug ❏ Comparison with M68000-based firmware ❏ 187Bug implementation ❏ Memory requirements Overview of M88000 Firmware The firmware for the M88000-based (88K) series of board and system
Debugger General Information Description of 187Bug The 187Bug package is a powerful evaluation and debugging tool for systems built around the MVME187 RISC-based microcomputers.
Introduction to MVME187Bug Debugger or Diagnostic Directories When using 187Bug, you operate out of either the debugger directory or the diagnostic directory. If you are in... With the prompt... The debugger directory 187-Bug> All of the debugger commands The diagnostic directory 187-Diag> All of the diagnostic commands as well as all of the debugger commands You have available... 4 You may switch between directories by using the Switch Directories (SD) command.
Debugger General Information Comparison with M68000-Based Firmware If you have used one or more of Motorola's other debugging packages, you will find the RISC 187Bug very similar, after making due allowances for the architectural differences between the M68000 and M88000 CPU architectures. These differences are primarily reflected as follows: 4 ❏ Instruction mnemonics and addressing modes of the assembler/disassembler differ somewhat in 187Bug.
Booting and Restarting 187Bug Memory Requirements The program portion of 187Bug is approximately 512KB of code, consisting of download, debugger, and diagnostic packages and contained entirely in EPROM. The EPROM sockets on the MVME187 are mapped starting at location $FF800000. 4 187Bug requires a minimum of 64KB of contiguous read/write memory to operate. The ENV command controls where this block of memory is located.
Debugger General Information Starting Up 187Bug 1. Verify that the MVME187 is properly installed and operating as described in Table 3-1 on page 3-2. 2. Power up the system. 187Bug executes some self-checks and displays the debugger prompt 187-Bug> (if 187Bug is in Board Mode). However, if the ENV command (Appendix A) has put 187Bug in System Mode, the system performs a selftest and tries to autoboot. Refer to the ENV and MENU commands listed in Table 5-1.
Booting and Restarting 187Bug 4. Following this message there is a delay to allow you an opportunity to abort the Autoboot process if you wish. To gain control without Autoboot, you can press the BREAK key or the software ABORT or RESET switches. 5. Then the actual I/O begins: the program pointed to within the volume ID of the media specified is loaded into RAM and control passed to it. Autoboot is controlled by parameters contained in the ENV command.
Debugger General Information For a user's ROMboot module to gain control through the ROMboot linkage, four requirements must be met: 4 Requirement... Optionally, with the ENV command... Power must have just been applied. Change this to respond to any reset. Your routine must be located within the MVME187 ROM memory map. Change this to any other portion of the onboard memory, or even offboard VMEbus memory. The ASCII string ÒBOOTÓ must be located within the speciÞed memory range.
Booting and Restarting 187Bug 3. At powerup, Network Boot is enabled, and providing the drive and controller numbers encountered are valid, the following message is displayed on the system console: "Network Boot in progress... To abort hit " Following this message there is a delay to allow you to abort the Network Boot process if you wish. To gain control without Network Boot, you can press the BREAK key or the software ABORT or RESET switches. 4.
Debugger General Information Reset Pressing and releasing the MVME187 front panel RESET switch initiates a system reset. Reset must be used if the processor ever halts, or if the 187Bug environment is ever lost (vector table is destroyed, stack corrupted, etc.). 4 ❏ COLD and WARM reset modes are available. ❏ By default, 187Bug is in COLD mode. During COLD reset: 1. A total system initialization takes place, as if the MVME187 had just been powered up. 2.
Booting and Restarting 187Bug Whenever abort is invoked while running target code (a user program), a ÒsnapshotÓ of the processor state is captured and stored in the target registers. For this reason, abort is most appropriate when terminating a user program that is being debugged. The target IP, register contents, etc., help to pinpoint the malfunction. 4 Abort Sequence Pressing and releasing the ABORT switch does the following: 1.
Debugger General Information Break Sequence 1. Removes any breakpoints in your code and keeps the breakpoint table intact. 2. Takes a snapshot of the machine state if the function was entered using SYSCALL. This machine state is then accessible to you for diagnostic purposes. 4 SYSFAIL* Assertion/Negation Upon a reset/powerup condition the debugger asserts the VMEbus SYSFAIL* line (refer to the VMEbus specification).
Disk I/O Support Disk I/O Support 187Bug can initiate disk input/output by communicating with intelligent disk controller modules over the VMEbus.
Debugger General Information Blocks Versus Sectors The logical block defines the unit of information for disk devices. A disk is viewed by 187Bug as a storage area divided into logical blocks. By default, the logical block size is set to 256 bytes for every block device in the system. The block size can be changed on a per device basis with the IOT command. 4 The sector defines the unit of information for the media itself, as viewed by the controller.
Disk I/O Support Disk I/O via 187Bug Commands These following 187Bug commands are provided for disk I/O. Detailed instructions for their use are found in the Debugging Package for Motorola 88K RISC CPUs User's Manual. When a command is issued to a particular controller LUN and device LUN, these LUNs are remembered by 187Bug so that the next disk command defaults to use the same controller and device.
Debugger General Information BH (Bootstrap and Halt) BH reads an operating system or control program from a specified device into memory, and then returns control to 187Bug. It is used as a debugging tool. 4 Disk I/O via 187Bug System Calls All operations that actually access the disk are done directly or indirectly by 187Bug TRAP #496 system calls. (The command-level disk operations provide a convenient way of using these system calls without writing and executing a program.
Disk I/O Support A command packet for one type of controller module usually does not have the same format as a command packet for a different type of module. The system call facilities which do disk I/O accept a generalized (controller-independent) packet format as an argument, and translate it into a controller-specific packet, which is then sent to the specified device.
Debugger General Information There are three ways to change the parameter tables: When you invoke one of these commands... Change status is... Command BO or BH The conÞguration area of the disk is read and the parameters corresponding to that device are rewritten according to the parameter information contained in the conÞguration area. Temporary The default parameter information is written back into the tables.
Network I/O Support Network I/O Support The Network Boot Firmware provides the capability to boot the CPU through the ROM debugger using a network (local Ethernet interface) as the boot device. The booting process is executed in two distinct phases. 4 ❏ The first phase allows the diskless remote node to discover its network identify and the name of the file to be booted. ❏ The second phase has the diskless remote node reading the boot file across the network into its memory.
Debugger General Information RARP/ARP Protocol Modules The Reverse Address Resolution Protocol (RARP) basically consists of an identity-less node broadcasting a "whoami" packet onto the Ethernet, and waiting for an answer. The RARP server fills an Ethernet reply packet up with the target's Internet Address and sends it. 4 The Address Resolution Protocol (ARP) basically provides a method of converting protocol addresses (e.g., IP addresses) to local area network addresses (e.g., Ethernet addresses).
Multiprocessor Support Network I/O Error Codes 187Bug returns an error code if an attempted network operation is unsuccessful. Multiprocessor Support 4 The MVME187 dual-port RAM feature makes the shared RAM available to remote processors as well as to the local processor.
Debugger General Information MPCR Status Codes The status codes stored in the MPCR are of two types: 4 ❏ Status returned (from 187Bug) ❏ Command set by the bus master (job requested by some processor) The status codes that may be returned from 187Bug are: HEX ASCII ASCII 0 R E (HEX 00) (HEX 52) (HEX 45) ---- Wait. Initialization not yet complete. Ready. The Þrmware monitor is watching for a change. Code pointed to by the MPAR is executing.
Multiprocessor Support 3. As the initialization proceeds, the execution path comes to the "prompt" routine. Before sending the prompt, this routine places an R in the MPCR to indicate that initialization is complete. Then the prompt is sent. Ð If no terminal is connected to the port, the MPCR is still polled to see whether an external processor requires control to be passed to the dual-port RAM.
Debugger General Information Global Control and Status Register (GCSR) Method A remote processor can initiate program execution in the local MVME187 dual-port RAM by issuing a remote GO command using the VMEchip2 Global Control and Status Registers (GCSR). 1. The remote processor places the MVME187 execution address in general purpose registers 0 and 1 (GPCSR0 and GPCSR1). 4 2. The remote processor then sets bit 8 (SIG0) of the VMEchip2 LM/SIG register. 3.
Diagnostic Facilities Diagnostic Facilities Included in the 187Bug package is a complete set of hardware diagnostics intended for testing and troubleshooting of the MVME187. These diagnostics are completely described in the MVME187Bug Debugging Package User's Manual. ❏ In order to use the diagnostics, you must switch directories to the diagnostic directory. ❏ If you are in the debugger directory, you can switch to the diagnostic directory by entering the debugger command Switch Directories (SD).
Debugger General Information Table 4-1. Diagnostic Monitor Commands/Prefixes Command/ PreÞx 4 Description NV Non-Verbose Mode SD Switch Directories SE Stop on Error Mode ST Selftest ZE Clear (Zero) Error Counters ZP Zero Pass Count Table 4-2.
Diagnostic Facilities 187Bug Diagnostic Test Groups Refer to the MVME187Bug Debugging Package User's Manual for complete descriptions of the diagnostic routines available and instructions on how to invoke them. Note that some diagnostics depend on restart defaults that are set up only in a particular restart mode. Refer to the documentation on a particular diagnostic for the correct mode. Table 4-3.
Debugger General Information 4 4-28
5 Using the 187Bug Debugger 5 This Chapter Covers ❏ Entering debugger command lines ❏ Entering and debugging programs ❏ Calling system utilities from user programs ❏ Preserving the debugger operating environment ❏ Floating point support ❏ The 187Bug debugger command set Entering Debugger Command Lines 187Bug is command-driven and performs its various operations in response to user commands entered at the keyboard.
Using the 187Bug Debugger Note 5 The presence of the upward caret ( ^ ) before a character indicates that the Control (CTRL) key must be held down while striking the character key. ^X ^H Delete key ^D (cancel line) (backspace) (delete) The cursor is backspaced to the beginning of the line. The cursor is moved back one position. Performs the same function as ^H. (redisplay) ^A (repeat) The entire command line as entered so far is redisplayed on the following line. Repeats the previous line.
Entering Debugger Command Lines Ò.RETURNÓ. Debugger Command Syntax In general, a debugger command is made up of the following parts: ❏ The command identifier (i.e., MD or md for the Memory Display command). Note that either upper- or lowercase is allowed. ❏ A port number if the command is set up to work with more than one port. ❏ At least one intervening space before the first argument. ❏ Any required arguments, as specified by the command.
Using the 187Bug Debugger Syntactic Variables The syntactic variables shown below are encountered in the command descriptions on the following pages. In addition, other syntactic variables may be used and are defined in the particular command description in which they occur. del exp addr count range 5 text Delimiter; either a comma or a space. Expression (described in detail in a following section). Address (described in detail in a following section). Count; the syntax is the same as for exp.
Entering Debugger Command Lines A numeric value may also be expressed as a string literal of up to four characters. The string literal must begin and end with the single quote mark ('). The numeric value is interpreted as the concatenation of the ASCII values of the characters. This value is right-justified, as any other numeric value would be.
Using the 187Bug Debugger Address Formats Addresses are entered as a hexadecimal number, e.g., 20000 would correspond to address $00020000. The address, or starting address of a range, can be qualified by a suffix of the form ^S, ^s, ^U, or ^u where S or s defines Supervisor address space, and U or u defines user address space. The default, when the qualifier is not specified, is Supervisor.
Entering Debugger Command Lines Offset Registers Eight pseudo-registers (Z0 through Z7) called offset registers are used to simplify the debugging of relocatable and positionindependent modules. The listing files in these types of programs usually start at an address (normally 0) that is not the one at which they are loaded, so it is harder to correlate addresses in the listing with addresses in the loaded program.
Using the 187Bug Debugger Note These logical port numbers (0 and 1) are shown in the pinouts of the MVME187 as ÒSERIAL PORT 1" and ÒSERIAL PORT 2", respectively. Physically, they are all part of connector P2.
Calling System Utilities from User Programs Alternately, the program may have been previously created using the 187Bug MM command as outlined above and stored to the host using the Dump (DU) command. A communication link must exist between the host system and the MVME187 port 1. (Hardware configuration details are provided in Connecting Peripherals on page 3-20.) The file is downloaded from the host to MVME187 memory by the Load (LO) command.
Using the 187Bug Debugger Preserving the Debugger Operating Environment This section explains how to avoid contaminating the operating environment of the debugger. Topics covered include: 5 ❏ 187Bug Vector Table and workspace ❏ Hardware functions ❏ Exception vectors used by 187Bug ❏ CPU/MPU registers 187Bug uses certain of the MVME187 onboard resources and may also use offboard system memory to contain temporary variables, exception vectors, etc.
Floating Point Support Hardware Functions The only hardware resources used by the debugger are the EIA232-D ports, which are initialized to interface to the debug terminal and a host. If these ports are reprogrammed, the terminal characteristics must be modified to suit, or the ports should be restored to the debugger-set characteristics prior to reinvoking the debugger.
Using the 187Bug Debugger Valid data types that can be used when modifying a floating point data register or a floating point memory location: Integer Data Types 12 Byte 1234 Half-Word 12345678 Word 5 Floating Point Data Types 1_FF_7FFFFF Single Precision Real Format 1_7FF_FFFFFFFFFFFFF Double Precision Real Format -3.12345678901234501_E+123 ScientiÞc Notation Format (decimal) When entering data in single or double precision format, the following rules must be observed: 1.
Floating Point Support Single Precision Real This format would appear in memory as: 1-bit sign Þeld (1 binary digit) 8-bit biased exponent Þeld (2 hex digits. Bias = $7F) 23-bit fraction Þeld (6 hex digits) A single precision number takes 4 bytes in memory. 5 Double Precision Real This format would appear in memory as: 1-bit sign Þeld (1 binary digit) 11-bit biased exponent Þeld (3 hex digits. Bias = $3FF) 52-bit fraction Þeld (13 hex digits) A double precision number takes 8 bytes in memory.
Using the 187Bug Debugger Scientific Notation This format provides a convenient way to enter and display a floating point decimal number. Internally, the number is assembled into a packed decimal number and then converted into a number of the specified data type. Entering data in this format requires the following fields: 5 An optional sign bit (+ or -). One decimal digit followed by a decimal point. Up to 17 decimal digits (at least one must be entered).
The 187Bug Debugger Command Set The 187Bug Debugger Command Set The 187Bug debugger commands are summarized in Table 5-1. The command syntax is shown using the symbols explained earlier in this chapter. The CNFG and ENV commands are explained in Appendix A. Controllers, devices, and their LUNs are listed in Appendix B or Appendix C. All other command details are explained in the MVME187Bug Debugging Package User's Manual. 5 Table 5-1.
Using the 187Bug Debugger Table 5-1.
The 187Bug Debugger Command Set Table 5-1.
Using the 187Bug Debugger Table 5-1.
AConfigure and Environment Commands A This Appendix Covers ❏ Configuring the board information block ❏ Setting the environment to Bug/Operating System ❏ Environment command parameters Configuring the Board Information Block CNFG [;[I][M]] This command is used to display and configure the board information block. This block is resident within the Non-Volatile RAM (NVRAM). Refer to the MVME187 RISC Single Board Computer User's Manual for the actual location.
A Configure and Environment Commands Example: Display the current contents of the board information block.
Setting Environment to Bug/Operating System Once modification and update are complete, you can now display the current contents as described earlier. Setting Environment to Bug/Operating System ENV [;[D]] The ENV command allows you to interactively view and configure all Bug operational parameters that are kept in Battery Backed Up RAM (BBRAM), also known as Non-Volatile RAM (NVRAM). The operational parameters are saved in NVRAM and used whenever power is lost.
A Configure and Environment Commands The parameters to be configured are listed in the following table: Table A-1. ENV Command Parameters ENV Parameter and Options Default Bug or System environment [B/S] S System Mode Field Service Menu Enable [Y/N] Y Display Þeld service menu.
Setting Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Auto Boot Abort Delay Auto Boot Default String [NULL for an empty string] Default Meaning of Default 15 This is the time in seconds that the Auto Boot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the Break key. The time value is from 0 through 255 seconds.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Network Auto Boot Controller LUN 00 LUN of a network controller module currently supported by the Bug. Default is 00. Network Auto Boot Device LUN 00 LUN of a network device currently supported by the Bug. Default is 00. Network Auto Boot Abort Delay 5 This is the time in seconds that the Network Boot sequence will delay before starting the boot.
Setting Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Network Auto Boot ConÞguration Parameters Pointer (NVRAM) 00000000 This is the address where the network interface conÞguration parameters are to be saved in NVRAM; these parameters are the necessary parameters to perform an unattended network boot.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Memory Search Ending Address 02000000 Top limit of the Bug's search for a work page. If a contiguous block of memory, 64KB in size, is not found in the range speciÞed by Memory Search Starting Address and Memory Search Ending Address parameters, then the bug will place its work page in the onboard static RAM on the MVME187.
Setting Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Base Address of Local Memory 00000000 Beginning address of Local Memory. It must be a multiple of the Local Memory board size, starting with 0. The Bug will set up hardware address decoders so that Local Memory resides as one contiguous block at this address. Default is $0.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Slave Address Translation Select #1 Slave Control #1 Slave Enable #2 [Y/N] Default Meaning of Default 00000000 This register deÞnes which bits of the Translation Address are signiÞcant. A logical one "1" indicates signiÞcant address bits, logical zero "0" is nonsigniÞcant. The non-signiÞcant bits will come from the VMEbus address that accesses the local resource.
Setting Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Master Enable #1 [Y/N] Default Y Meaning of Default Yes, Setup and enable the Master Address Decoder #1. Master Starting Address #1 02000000 Base address of the VMEbus resource that is accessible from the local bus. Default is the end of calculated local memory. Master Ending Address #1 EFFFFFFF Ending address of the VMEbus resource that is accessible from the local bus.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Master Enable #4 [Y/N] Default Meaning of Default N Do not set up and enable the Master Address Decoder #4. Master Starting Address #4 00000000 Base address of the VMEbus resource that is accessible from the local bus. This will be the local bus address. Default is $0. Master Ending Address #4 00000000 Ending address of the VMEbus resource that is accessible from the local bus.
Setting Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default F-Page (VMEbus A24) Enable [Y/N] Y Yes, Enable the F-Page Address Decoder. F-Page (VMEbus A24) Control 02 Works the same as Slave Control #1. Default is $02. ROM Speed Bank A Code ROM Speed Bank B Code 05 05 Used to set up the ROM speed. Default is $05 = 165 ns (25 MHz MVME187) or $04=145 ns (33 MHz MVME187).
A Configure and Environment Commands A-14
BDisk/Tape Controller Data B Disk/Tape Controller Modules Supported The following VMEbus disk/tape controller modules are supported by the 187Bug. The default address for each controller type is First Address and the controller can be addressed by First CLUN during commands BH, BO, or IOP, or during TRAP #496 calls .DSKRD or .DSKWR.
Disk/Tape Controller Data B Disk/Tape Controller Default Configurations Note SCSI Common Command Set (CCS) devices are only the ones tested by Motorola Computer Group.
Disk/Tape Controller Default Configurations MVME327A -- 9 Devices Controller LUN 2 Address $FFFFA600 3 $FFFFA700 Device LUN 00 10 20 30 40 50 60 80 81 B Device Type SCSI Common Command Set (CCS), which may be any of these: - Fixed direct access - Removable ßexible direct access (TEAC style) - CD-ROM - Sequential access Local ßoppy drive Local ßoppy drive MVME328 -- 14 Devices Controller LUN 6 Address $FFFF9000 7 $FFFF9800 16 $FFFF4800 17 $FFFF5800 18 $FFFF7000 19 $FFFF7800 Device LUN 00 0
Disk/Tape Controller Data MVME350 -- 1 Device B Controller LUN 4 5 Address $FFFF5000 $FFFF5100 Device LUN Device Type 0 QIC-02 streaming tape drive IOT Command Parameters for Supported Floppy Types The following table lists the proper IOT command parameters for floppies used with boards such as the MVME328, MVME167, and MVME187.
IOT Command Parameters for Supported Floppy Types IOT Parameter Single/Equal_in_all Track Zero Density Slow/Fast Data Rate DSDD5 PCXT8 S E S Floppy Types and Formats PCXT9 PCXT9_3 PCAT E PS2 SHD E E E E S S S Other Characteristics F F F Number of Physical 0A00 0280 02D0 05A0 0960 0B40 1680 Sectors Number of Logical 09F8 0500 05A0 0B40 12C0 1680 2D00 Blocks (100 in size) Number of Bytes in 653312 327680 368460 737280 1228800 1474560 2949120 Decimal Media Size/Density 5.25/DD 5.25/DD 5.
Disk/Tape Controller Data B B-6
CNetwork Controller Data C Network Controller Modules Supported The VMEbus network controller modules supported by MVME187Bug are shown in Table C-1. The default address for each type and position is shown to indicate where the controller must reside to be supported by MVME187Bug. The CLUNs and DLUNs are used in conjunction with the following debugger commands and debugger system calls: Debugger Commands Debugger System Calls NBH .NETRD NBO .NETWR NIOC .NETFOPN NIOP .NETFRD NIOT .
Network Controller Data Table C-1.
DTroubleshooting the MVME187: Solving Startup Problems D ❏ Try these simple troubleshooting steps before calling for help or sending your CPU board back for repair. ❏ Some of the procedures will return the board to the factory debugger environment. (The board was tested under these conditions before it left the factory.) ❏ Selftest may not run in all user-customized environments. Table D-1. Troubleshooting Steps Condition I. Nothing works, no display on the terminal. Possible Problem A.
Troubleshooting the MVME187: Solving Startup Problems Table D-1. Troubleshooting Steps (Continued) Possible Problem II. There is a A. The display on the keyboard may terminal, but be connected input from the incorrectly. keyboard has no B. Board effect. jumpers may be conÞgured incorrectly. C. You may have invoked ßow control by pressing a HOLD or PAUSE key, or by typing ^S Also, a HOLD LED may be lit on the keyboard. Condition D D-2 Try This: Recheck the keyboard connections and power.
Table D-1. Troubleshooting Steps (Continued) Possible Problem III. Debug A. Debugger prompt EPROM may be missing. 187-Bug> does not appear B. The board at powerup, and may need to be reset. the board does not auto boot. Condition Try This: 1. Disconnect all power from your system. 2. Check that the proper debugger EPROM is installed per this manual. 3. Reconnect power. ! Caution D Performing the next step will change some parameters that may affect your system operation. 4.
Troubleshooting the MVME187: Solving Startup Problems Table D-1. Troubleshooting Steps (Continued) Condition D IV. Debug prompt 187-Bug> appears at powerup, but the board does not auto boot. Possible Try This: Problem A. The initial 1. Start the onboard calendar clock and timer. Type debugger in environment set mmddyyhhmm parameters may where the characters indicate the month, day, be set wrong. year, hour, and minute. The date and time will be displayed. B.
Table D-1. Troubleshooting Steps (Continued) Condition Possible Problem Try This: 6. You may need to use the cnfg command (see Appendix A) to change clock speed and/or Ethernet Address, and then later return to env and step 3. 7. Run selftest by typing in st The tests take as much as 10 minutes, depending on RAM size. They are complete when the prompt returns. (The onboard selftest is a valuable tool in isolating defects.) 8. The system may indicate that it has passed all the selftests.
Troubleshooting the MVME187: Solving Startup Problems D D-6
EEIA-232-D Interconnections E Introduction The EIA-232-D standard is the most common terminal/computer and terminal/modem interface, and yet it is not fully understood. This may be because not all the lines are clearly defined, and many users do not see the need to follow the standard in their applications. Often designers think only of their own equipment, but the state of the art is computer-to-computer or computer-tomodem operation. A system should easily connect to any other system.
EIA-232-D Interconnections Table E-1. EIA-232-D Interconnections E Pin Signal Signal Name and Description Number Mnemonic 1 CHASSIS GROUND. Not always used. See section Proper Grounding. 2 TxD TRANSMIT DATA. Data to be transmitted; input to the modem from the terminal. 3 RxD RECEIVE DATA. Data which is demodulated from the receive line; output from the modem to the terminal. 4 RTS REQUEST TO SEND. Input to the modem from the terminal when required to transmit a message.
Levels of Implementation Table E-1. EIA-232-D Interconnections (Continued) Pin Signal Signal Name and Description Number Mnemonic 22 RI RING INDICATOR. Output from the modem to the terminal; indicates to the terminal that an incoming call is present. The terminal causes the modem to answer the phone by carrying DTR true while RI is active. 23 Not used. 24 TxC TRANSMIT CLOCK (DTE). Input to modem from terminal; same function as TxC on pin 15. 25 BSY BUSY. Input to modem from terminal.
EIA-232-D Interconnections Signal Adaptations One set of handshaking signals frequently implemented are RTS and CTS. CTS is used in many systems to inhibit transmission until the signal is high. In the modem application, RTS is turned around and returned as CTS after 150 microseconds. RTS is programmable in some systems to work with the older type 202 modem (half duplex). CTS is used in some systems to provide flow control to avoid buffer overflow. This is not possible if modems are used.
Levels of Implementation SERIAL PORT 1488 RXD TXD 3 1489A TXD RXD 2 39kΩ -12V RTS NC 1 CONNECTOR TO TERMINAL +12V LS08 470Ω CTS 470Ω 470Ω CTS 5 DSR OPTIONAL HARDWARE TRANSPARENT MODE DCD DCD SIG GND 6 8 7 TXC RXC LS08 +12V CHASSIS GND LOGIC GND SIG GND 470Ω 7 NC DTR 1488 SERIAL PORT TXD TXD 1 20 2 1489A RXD 3 RXD 39kΩ -12V 1488 RTS RTS 4 CONNECTOR TO MODEM OR HOST SYSTEM 470Ω +12V 1489A CTS CTS 39kΩ -12V +12V 1489A DCD TXC 5 470Ω DCD 6 39kΩ -12V RXC cb181 9210 Figu
EIA-232-D Interconnections Figure E-2 shows a way of wiring an EIA-232-D connector to enable a computer to connect to a basic terminal with only three lines. This is feasible because most terminals have DTR and RTS signals that are ON, and which can be used to pull up the CTS, DCD, and DSR signals. Two of these connectors wired back-to-back can be used. In this implementation, however, diagnostic messages that might otherwise be generated do not occur because all the handshaking is bypassed.
Levels of Implementation Proper Grounding Another subject to consider is the use of ground pins. There are two pins labeled GND. Pin 7 is the SIGNAL GROUND and must be connected to the distant device to complete the circuit. Pin 1 is the CHASSIS GROUND, but it must be used with care. The chassis is connected to the power ground through the green wire in the power cord and must be connected to the chassis to be in compliance with the electrical code.
EIA-232-D Interconnections E E-8
Index Symbols #496 system calls 4-16 +12V LED 2-11 Numerics 100 ns SRAMs 2-13 187Bug debugger command set 5-15 firmware in EPROMs 2-4 implementation 4-4 see also debug monitor and MVME187Bug stack 4-5 vector table and workspace 5-10 27C102JK type EPROM 2-13 44-pin PLCC/CLCC EPROM 2-13 5-1/4 DS/DD 96 TPI floppy drive B-2 53C710 (SCSI Controller) 2-22 82596CA 2-12, 2-21 see also Ethernet and LAN 96-position DIN connectors 2-7 A abort 4-10 ABORT switch 2-11 adapter board and transition module installation 3
Index BOOTP address determination and bootfile selection 4-20 protocol module 4-20 Bootstrap and Halt (BH) 4-16 Operating System (BO) 4-15 Protocol (BOOTP) 4-20 braces 5-3 break 4-11 BREAK key 4-11 breakpoint and tracing capabilities 4-2 breakpoint during execution of the user program 5-2 bug operational parameters A-3 byte definition 1-3 ordering 1-3 C I N D E X C programming language 4-4 cable(s) 3-20 calling system utilities from user programs 5-9 card slot selection 3-15 CCS (SCSI Common Command Set
D Dallas DS1210S 2-14 data and address parameter numeric format 1-2 size definitions 1-3 data bus structure 2-12 data circuit-terminating equipment (DCE) E-1 data terminal equipment (DTE) E-1 DCE (data circuit-terminating equipment) E-1 debug monitor 3-14 see also 187Bug and MVME187Bug debug port 5-7 debugger 3-9 commands 5-15 directories 4-3 general information 4-1 prompt 5-1 setup/operation parameters stored in ROM 3-9 decimal number 1-2 default 187Bug controller and device parameters 4-17 baud rate 3-21
Index environmental parameters 3-25 EPROM(s) 2-13, 2-25, 3-7, 3-14, 4-4, 5-10 socket installation 3-7 socket orientation 3-7 user-programmed 3-7 ESDI Winchester hard drive B-2 Ethernet C-1 address, when to change D-5 interface 2-21 LAN (+12vdc) fuse 3-28 see also 82596CA and LAN station address 2-21 transceiver interface 2-3 evaluation of an expression 5-5 Examine and/or change environmental parameters 3-25 exception vectors used by 187Bug 5-11 exponent field 5-12 expression 5-4 expression as a parameter 5
sample configurations E-4 internal SCSI connections 3-18 serial port connections 3-18 Internet Protocol (IP) 4-19 Internet User Datagram Protocol (UDP) 4-20 interrupt(s) 2-23 IOC (I/O Control) 4-15 IOI (Input/Output Inquiry) 4-15 IOP (Physical I/O to Disk) 4-15 IOT command parameters B-4 command parameters for supported floppy types B-4 IOT (I/O teach) isolating defects D-5 italic strings 5-3 J J1 3-8, 3-9 J2 3-8, 3-10 J6 3-11, 3-12 J7 3-11, 3-13 J8 3-11, 3-13 jumpers 3-8 K keyboard control 4-3 L LAN (lo
Index I N D E X move files between machines on different networks 4-20 MPAR (Multiprocessor Access Register) 4-22 MPCR (Multiprocessor Control Register) method 4-21 status codes 4-22 MPU clock speed calculation 4-12 MPU register CR20 5-11 multiple module cage configuration 3-28 Multiprocessor Address Register (MPAR) 4-22 Multiprocessor Control Register (MPCR) 4-21 method 4-21 multiprocessor support 4-21 MVME187 2-1, C-1 block diagram 2-7 specifications 2-6 MVME187Bug debugging package see also 187Bug and
parallel port interface 2-20 parameter tables 4-13, 4-18 parity mezzanines 2-2 parity modules 2-2 patching programs 4-2 PCCchip2 ASIC 2-9 peripheral connection procedures 3-21 PLCC (EPROM) 2-13 port 0 or 00 5-7 port 1 or 01 5-7 port number(s) 5-3, 5-7 power sources 2-14 preserving the debugger operating environment 5-10 primary and secondary power source support 2-14 priority 82596CA LAN (highest) 2-12 of local bus masters 2-12 type arbiter 2-12 programmable EPROM features 2-13 programmable tick timers 2-23
Index SCSI commands Inquiry 4-14 Mode Sense 4-14 sector size 4-14 selftest error 4-12 sequential access device B-2, B-3 Serial Controller Chip (SCC) see also CD2401 serial port 1 5-8 serial port 2 5-8 serial port 4 clock configuration select headers J7 and J8 3-11 serial port interface 2-18 serial ports 2-3 Set Environment to Bug/Operating System (ENV) A-3 settings for J1 general purpose readable jumpers 3-9 J2 system controller header 3-10 J6 SRAM optional backup power select header 3-12 J7 and J8 serial
T terminal input/output control 4-13, 5-1 terminal(s) E-1 TFTP protocol module 4-20 tick timers 2-23 timeout 2-23 tracing capabilities 4-2 transfer type (TT) 2-24 transition boards supported by MVME187 2-8 transition module installation 3-20 translation table 5-10 translation through the Memory Management Units (MMUs) 5-10 TRAP #496 4-16, 5-9 calls, and default controller addresses B-1 function ".
