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CPCI-6020 CompactPCI Single Board

Computer

Installation and Use

6806800A51C

February 2008

Summary of content (168 pages)

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CPCI-6020 CompactPCI Single Board Computer Installation and Use 6806800A51C February 2008
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© Copyright 2008, 2007 Motorola All rights reserved. Trademarks Motorola® and the stylized M logo are trademarks registered in the U.S. Patent and Trademark Office. PowerPC® is a registered trademark of International Business Machines and is used by Motorola Inc. under license from IBM Corporation. CompactPCI® is a registered trademark of PCI Industrial Computer Manufacturers Group.
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Contents About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Safety Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1 Introduction . . . . . . . . . . . . .
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Contents 2.12.3 Understanding Hot Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.4 Recognize Different Injector/Ejector Lever Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.5 Verify Slot Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.6 Preserve EMI Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.
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Contents 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.3.1.7 Synchronous Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.3.1.8 USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PCI Bus B Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.4.1 PMC Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 5 6.5 6.6 107 107 108 108 108 110 110 114 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM500 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM500 Module Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 7.4 7.5 7.6 7.7 7.8 7.9 8 131 131 132 133 135 136 138 140 141 143 143 143 146 146 147 147 148 148 149 149 150 CNFG and ENV Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.1 8.2 8.3 8.4 A Preparing the Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Serial Ports 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 8 CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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List of Tables Table 1-1 Table 1-2 Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 3-20 Table 3-21 Table 3-22 Table 3-23 Table 3-24 Table 3-25 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 5-1 Table 5-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 7-7 Table 7-8 Table 7-9 Table 7-10 Table 7-11 Table 7-12 Table 7-13 Table 7-14 Table A-1 Table A-2 Table A-3 10 RAM500 SDRAM Memory Size Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM500 Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM500 Bottom Side Connector (P1) Pin Assignments . . . . . . .
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List of Figures Figure 2-1 Figure 2-2 Figure 2-3 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Header Locations and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Injector/Ejector Lever Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Start Up Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 12 CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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About this Manual Overview of Contents This manual provides the information required to install and configure an CPCI-6020 Single Board Computer. Moreover, this manual provides specific preparation and installation information and data applicable to the board. The CPCI-6020 was previously offered as the MCP820 Single Board Computer. The CPCI-6020 is a high-performance CompactPCI single board computer featuring the MPC7410 with Alti-Vec™ technology for algorithmic intensive computational capabilities.
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About this Manual Appendix A, Related Documentation provides listings for Motorola publications, manufacturer’s documents and related industry specification for this product.
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About this Manual Abbreviation Description PIM PMC Interface Module PIO Parallel Input Output PIRQx PCI Interrupts PMC Peripheral Mezzanine Card PRP PowerPC Reference Platform PrPMC Processor PMC RISC Reduced Instruction Set Computer RoHS Restriction of Hazardous Substances SIM Serial Interface Module SMC System Memory Controller SPD Serial Presence Detect TA Terminal Attach UART Universal Asynchronous Receiver-Transmitter USB Universal Serial Bus VPD Vital Product Data Conv
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About this Manual Notation Description . Omission of information from example/command that is not necessary at the time being . . .. Ranges, for example: 0..4 means one of the integers 0,1,2,3, and 4 (used in registers) | Logical OR Indicates a hazardous situation which, if not avoided, could result in death or serious injury Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message No danger encountered.
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About this Manual Comments and Suggestions We welcome and appreciate your comments on our documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to: z Motorola, Inc. Embedded Communications Computing 2900 South Diablo Way, Suite 190 Tempe, Arizona 85282 z reader-comments@ecc.mot.com In all your correspondence, please list your name, position, and company.
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About this Manual 18 CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Safety Notes This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.
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Safety Notes Board products are tested in a representative system to show compliance with the above mentioned requirements. A proper installation in a compliant system will maintain the required performance. Use only shielded cables when connecting peripherals to assure that appropriate radio frequency emissions compliance is maintained.
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Safety Notes Operation Damage of Module Surface High humidity and condensation on the product surface causes short circuits. Do not operate the product outside the specified environmental limits. Make sure the product is completely dry and there is no moisture on any surface before applying power. Overheating and Damage of the Product Operating the product without forced air cooling may lead to overheating and thus damage of the product.
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Safety Notes Before touching the module or electronic components, make sure that you are working in an ESD-safe environment. Damage of Module and Additional Devices Incorrect installation of additional devices or modules may damage the product or the additional devices or modules. Before installing or removing an additional device or module, read the respective documentation. Board Damage Inserting or removing modules that are not HA capable with power applied may result in damage to module components.
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Safety Notes Preserve EMI Compliance To preserve compliance with applicable standards and regulations for electromagnetic interference (EMI), during operation all front and rear openings on the chassis or board face plates must be filled with an appropriate card or covered with a filler panel. If the EMI barrier is open, devices may cause or be susceptible to excessive interference.
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Safety Notes 24 CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Sicherheitshinweise Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind.
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Sicherheitshinweise Das Produkt arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung. Bei unsachgemäßem Einbau und anderem als in diesem Handbuch beschriebenen Betrieb können Störungen im Hochfrequenzbereich auftreten. Wird das Produkt in einem Wohngebiet betrieben, so kann dies mit grosser Wahrscheinlichkeit zu starken Störungen führen, welche dann auf Kosten des Produktanwenders beseitigt werden müssen.
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Sicherheitshinweise Betrieb Beschädigung des Produktes Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Produktes können zu Kurzschlüssen führen. Betreiben Sie das Produkt nur innerhalb der angegebenen Grenzwerte für die relative Luftfeuchtigkeit und Temperatur. Stellen Sie vor dem Einschalten des Stroms sicher, dass sich auf dem Produkt kein Kondensat befindet.
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Sicherheitshinweise Installation Schwere Verletzungen oder Tod Dieses System wird mit gefährlichen Spannungen betrieben, die schwere Verletzungen oder Tod verursachen können. Gehen Sie deshalb extrem vorsichtig vor, wenn Sie mit dem System oder seinen Komponenten umgehen, es testen oder anpassen. Beschädigung des Produktes und von Zusatzmodulen Fehlerhafte Installation von Zusatzmodulen, kann zur Beschädigung des Produktes und der Zusatzmodule führen.
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Sicherheitshinweise Motorola Embedded Communications Computing (ECC) und unsere Zulieferer unternehmen größte Anstrengungen um sicherzustellen, dass sich Pins und Stecker von Boards vor dem Verlassung der Produktionsstätte in einwandfreiem Zustand befinden. Verbogene Pins, verursacht durch fehlerhafte Installation oder durch Installation von Boards mit beschädigten Steckern kann die durch ECC gewährte Garantie für Boards und Backplanes erlöschen lassen.
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Sicherheitshinweise 30 CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Introduction 1.1 1 Features The following table summarizes the features of the CPCI-6020 single-board computers. Table 1-1 Features Feature Description Processor Single MPC7410 Processor Core Frequency up to 500 MHz for MPC7410 Bus Clock Frequency of 100 MHz Address and data bus parity L2 Cache 2 MB back side L2 Cache using pipeline burst-mode SRAMS Data bus parity Flash Xport Channel 0 (Bank A): 32 MB on-board using one 256 megabit device.
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Introduction Standard Compliances Table 1-1 Features (continued) Feature Description RTC/NVRAM 32 KB NVRAM/RTC/WDT provided by M48T37V Connected to Harrier A Xport 2 configured as 8-bit port Watchdog Timers Two independent programmable timers in each Harrier One programmable timer in M48T37V Peripheral Support USB host/hub interface 10BaseT/100BaseTX Ethernet interface IDE Interface for IDE flash and external IDE drive support Two 16550-compatible async serial ports (Harrier UART0/UART1) Two sync/a
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Ordering Information Introduction Table 1-2 Board Standard Compliances (continued) Standard Description CISPR 22 EMC requirements (legal) on system level (predefined Motorola system) CISPR 24 EN 55022 EN 55024 FCC Part 15 Industry Canada ICES-003 VCCI Japan AS/NZS CISPR 22 EN 300 386 NEBS Standard GR-1089 CORE NEBS Standard GR-63-CORE Environmental Requirements ETSI EN 300 019 series Directive 2002/95/EC 1.
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Introduction 1.3.2 Board Accessories Board Accessories This table lists the available memory modules and Rear Transition Module available for the CPCI-6020.
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Hardware Preparation and Installation 2.1 2 Overview This chapter provides startup and safety instructions related to this product, hardware preparation instructions, including: default jumper settings; system considerations, and installation instructions for the baseboard; as well as the PMC, memory mezzanines, and transition module associated with this board. A fully implemented CPCI-6020 consists of the baseboard plus: 2.2 z A single-wide PCI mezzanine card (PMC) for added versatility.
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Hardware Preparation and Installation Overview of Start-up Procedure Shipment Inspection To inspect the shipment, perform the following steps: 1. Verify that you have received all items of your shipment. 2. Check for damage and report any damage or differences to customer service. 3. Remove the desiccant bag shipped together with the board and dispose of it according to your country’s legislation. The product is thoroughly inspected before shipment.
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Equipment Required Hardware Preparation and Installation Table 2-1 Startup Overview (continued) Task Page Initialize the system clock. Chapter 5, Firmware Examine and/or change environmental parameters. Chapter 8, CNFG and ENV Commands Program the board as needed for your applications. CPCI-6020 CompactPCI Single Board Computer Programmer’s Reference Guide Harrier Application Specific Integrated Circuit (ASIC) Programmer’s Reference Guide 2.
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Hardware Preparation and Installation Environmental Requirements You must make sure that the board, when operated in your particular system configuration, meets the environmental requirements specified below. Operating temperatures refer to the temperature of the air circulating around the board and not to the component temperature.
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Power Requirements 2.5.2 Hardware Preparation and Installation Power Requirements The CPCI-6020 module draws +3.3VDC, +5VDC, VIO, +12VDC and -12VDC, with a voltage variation of -/+ 5% from the standard value, from the CompactPCI backplane connector J1. Typical power consumption of only the CPCI-6020 is approximately 15 W at +5VDC and 9 W at + 3.3VDC. Table 2-3 Baseboard and RTM Power Requirements Board ID CPCI-6020-500 CPCI-6020-MCPTM-01 +3.3 V +5 V +12 V 2.6 A typ 2.8 A typ. 15 mA typ. 3.
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Hardware Preparation and Installation CPCI-6020 Baseboard Preparation The CPCI-6020 also provides configuration modification via software control by setting bits in control registers after installing the module in a system. The CPCI-6020 control registers are described in the CPCI-6020 CompactPCI Single Board Computer Programmer’s Reference Guide, and the Harrier Application Specific Integrated Circuit (ASIC) Programmer’s Reference Guide. 2.
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Jumper Settings Hardware Preparation and Installation z Remote switch (J19) z Jumpers J7 and J25 are only for factory use Figure 2-1 Header Locations and Jumper Settings J18 J19 J17 U18 U19 J21 J20 1 U31 3 J24 J22 2.8 Jumper Settings The following sections describe the on-board jumpers and their configurations for the CPCI6020. For jumper locations, see Figure 2-1. 2.8.
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Hardware Preparation and Installation Harrier Power Up Configuration Header To enable Flash Bank A, place a jumper across pins 1 and 2 of header J24. To enable Flash Bank B, place a jumper across pins 2 and 3 of header J24. J24 Jumper On 1-2 Flash Bank A Enabled (32 MB, soldered) 2-3 Flash Bank B Enabled (1 MB, sockets) Factory Configuration 2.8.
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Enable/Disable Lockdown of One or More Flash Blocks for Bank A Hardware Preparation and Installation When using the +12 V and -12 V power disable (J18 jumper is installed), +12 V and -12 V power is not provided to on-board CPCI-6020 electronics or to the rear transition module. This may affect operation of any modules installed, such as: a PMC on the CPCI-6020 or a PIM or SIM on the rear transition module.
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Hardware Preparation and Installation PMC Module Installation Should it be necessary to install a PMC mezzanine on the baseboard, refer to PMC Module Installation in this chapter for a description of that installation procedure. Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life. Before touching the module or electronic components, make sure that you are working in an ESD-safe environment. 2.
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PMC Module Installation Hardware Preparation and Installation 3. Carefully remove the CPCI-6020 from the CompactPCI card slot and place it on a clean and adequately protected working surface with connectors J1 through J5 facing you. Product Damage Avoid touching areas of integrated circuitry; static discharge can damage these circuits. Before touching the board or electronic components, make sure you are working in an ESD-safe environment. 4. Remove the PCI filler from the front panel. 5.
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Hardware Preparation and Installation 2.11 CompactFlash Memory Card Installation CompactFlash Memory Card Installation Procedure The CompactFlash memory card mounts on the CPCI-6020 baseboard. To upgrade or install a CompactFlash memory card, refer to the next figure and proceed as follows: 1. Attach an ESD strap to your wrist. Attach the other end of the strap to the chassis (for proper grounding). The ESD strap must be secured to your wrist and to chassis ground throughout the procedure. 2.
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Before You Install or Remove a Board Hardware Preparation and Installation 4. Slide the CompactFlash memory card into the J15 connector and make sure that pin 1 of the card aligns with pin 1 of J15. Insert CompactFlash 5. If you are installing RAM500 memory cards or a PMC module on this board, follow the installation instructions in Chapter 6, RAM500 Memory Expansion Module, on page 117 and PMC Module Installation on page 44.
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Hardware Preparation and Installation 2.12.1 Watch for Bent Pins or Other Damage Watch for Bent Pins or Other Damage Product Damage Bent pins or loose components can cause damage to the board, the backplane or other system components. Carefully inspect your board and the backplane for both pin and component integrity before installation. ECC and our suppliers take significant steps to ensure there are no bent pins on the backplane or connector damage to the boards prior to leaving our factory.
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Recognize Different Injector/Ejector Lever Types Hardware Preparation and Installation The CPCI-6020 does not support a hot swap LED. You may need to manually shut down applications or operating systems running on the board prior to board removal. Data Loss Powering down or removing a board before the operating system or other software running on the board has been properly shut down may cause corruption of data or file systems.
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Hardware Preparation and Installation 2.12.5 Verify Slot Usage Verify Slot Usage Product Damage Prevent possible damage to module components by verifying the proper slot usage for your configuration. Check the icons and colored card rails for slot purpose prior to installing a module. In most cases, connector keying will prevent insertion of a board into an incompatible slot. However, as an extra precaution, you should be familiar with the glyphs and colored card rails used to indicate slot purpose.
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Installing and Removing a Module 2.13 Hardware Preparation and Installation Installing and Removing a Module This section describes a recommended procedure for installing and removing a board module in a chassis. Before you install your module, please read all cautions, warnings and instructions presented in this section and the guidelines explained in Before You Install or Remove a Board on page 47. Installation Procedure Hot swap compliant modules may be installed while the system is powered on.
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Hardware Preparation and Installation Installing and Removing a Module Refer to the following illustration and perform these steps when installing modules. Note that this illustration is for general reference only and may not accurately depict the connectors and handles on the board you are installing. Stage 2 (Detail) Stage 1 J5 P5 J5 P5 J4 P4 J4 P4 J3 P3 J3 P3 J2 P2 J2 P2 J1 P1 J1 P1 Stage 2 Stage 3 1.
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Installing and Removing a Module Hardware Preparation and Installation Before you remove your module, please read all cautions, warnings and instructions presented in this section and the guidelines explained in Before You Install or Remove a Board on page 47. Hot swap compliant modules may be removed while the system is powered on. If a module is not hot swap compliant, you should remove power to the slot or system before removing the module. See Understanding Hot Swap on page 48 for more information.
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Hardware Preparation and Installation Startup and Operation If your module is hot swap compliant and you are running fully functional hot swapaware software, unlatching this ejector lever will start the shutdown process on the board. 4. Carefully pull the module from the chassis. 2.14 Startup and Operation This section describes startup information used with the CPCI-6020 family of single board computers in a system configuration.
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System Considerations Hardware Preparation and Installation The following flowchart shows the basic initialization process that takes place during system startup. Refer to a detailed initialization list in Chapter 5, Firmware, on page 107. Figure 2-3 Start Up Flow Diagram Startup System Initialization Console Detection Run Self Tests (if enabled) Auto Boot (if enabled) Operating System 2.15 System Considerations The CPCI-6020 is designed to operate as a CompactPCI system slot board.
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Hardware Preparation and Installation System Considerations A default baud rate of 9600 is used for serial ports on CPCI-6020 boards. After power-up, the baud rate can be changed using the PPCBug PF (Port Format) command via the command line interface. Whatever the baud rate, some type of hardware handshaking; either XON/OFF or via the RTS/CTS line is desirable if the system supports it.
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Controls, LEDs, and Connectors 3.1 3 Overview This chapter summarizes the controls, LEDs, and pin assignments for the CPCI-6020 baseboard. Controls, LEDs, and pin assignments for the CPCI-6020-MCPTM-01 transition module and RAM500 memory modules can be found in Chapter 7, Transition Module Preparation and Installation and Chapter 6, RAM500 Memory Expansion Module respectively. 3.
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Controls, LEDs, and Connectors 3.3 Front Panel Connectors and LEDs Front Panel Connectors and LEDs The CPCI-6020 front panel provides access to recessed Abort and Reset push-button switches, Board Fail, and CPU Bus Activity LEDs, an RJ-45 Ethernet connector, an RJ-45 serial port connector, two USB connectors and the PMC front panel. This section describes the baseboard connectors and LEDs.
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Front Panel Asynchronous Serial Port Controls, LEDs, and Connectors Table 3-1 Ethernet Connector Pin Assignments (continued) 3.3.2 Pin Signal 6 RD- 7 AC Terminated 8 AC Terminated Front Panel Asynchronous Serial Port An RJ-45 receptacle is located on the front panel of the CPCI-6020 to provide the interface to the COM1 serial port. This port is configured as DCE. The pin assignments for this connector is as follows: Table 3-2 COM1 Pin Assignments 3.3.
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Controls, LEDs, and Connectors ABORT# Switch Table 3-4 USB Port 0 (continued) 3.3.4 Pin Name Pin Number 3 USB0DATA_P 4 GND ABORT# Switch The ABORT# switch is recessed to reduce the likelihood of accidental activation. The ABORT# signal is connected to the Harrier Abort Switch (ABTSW_L) input and generates an MPIC internal interrupt. This signal is debounced in the Harrier ASIC. 3.3.5 RESET# Switch The RESET# switch is recessed to reduce the likelihood of accidental activation.
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CompactPCI Bus Connectors Controls, LEDs, and Connectors Pin D15 of J1 is used in peripheral slots for the BD_SEL# signal supporting hot swap. In the system slot, this pin is defined as GND. The CPCI-6020 interprets this pin as BD_SEL_L. In a non-High Availablility (HA) chassis, this signal is GND (always asserted) and hence this usage is backwardly compatible. Table 3-6 J1 CompactPCI Connector Pin Row A Row B Row C Row D Row E Pin 25 +5 V REQ64_L ENUM_L +3.
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Controls, LEDs, and Connectors CompactPCI Bus Connectors Table 3-7 J2 CompactPCI Connector (continued) Pin Row A Row B Row C Row D Row E Pin 21 No Connect (CLK6) GND No Connect (RSV) No Connect (RSV) No Connect (RSV) 21 20 No Connect CLK5 GND No Connect GND No Connect (RSV) 20 GND GND No Connect No Connect No Connect 19 (RSV) (RSV) (RSV) 19 (RSV) 18 No Connect BRSVP2A18 No Connect BRSVP2B18 No Connect BRSVP2C18 GND No Connect BRSVP2E18 18 17 No Connect BRSVP2A17 GN
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CompactPCI User I/O Connector 3.4.2 Controls, LEDs, and Connectors CompactPCI User I/O Connector Connector J3 is a 110 pin AMP Z-pack 2 mm hard metric type B connector. This connector routes the I/O signals for the PMC I/O, serial port and USB ports.
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Controls, LEDs, and Connectors 3.4.3 CompactPCI User I/O Connector CompactPCI User I/O Connector Connector J4 is a 110 pin AMP Z-pack 2 mm hard metric type B connector. This connector routes the PCI bus of Harrier A to hot swap controller bridge board. The pin assignments for J4 on the processor board are shown in Table 3-10 (outer row F is assigned and used as ground pins but is not shown in the table).
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CompactPCI User I/O Connector 3.4.4 Controls, LEDs, and Connectors CompactPCI User I/O Connector Connector J5 is a 110 pin AMP Z-pack 2 mm hard metric type B connector. This connector routes the I/O signals for the two COM ports, the IDE secondary port, the keyboard, the mouse, the two USB ports and the two ethernet ports.
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Controls, LEDs, and Connectors CompactPCI User I/O Connector Table 3-12 J5 Signal Descriptions (continued) Signal Description DA (2:0) Drive register and data port address lines. DCDn Data carrier detected DD (15:0) Data lines DIOR_L I/O read DIOW_L I/O write DIR_L Controls the direction of the floppy head reader.
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Memory Mezzanine Connectors Controls, LEDs, and Connectors Table 3-12 J5 Signal Descriptions (continued) Signal Description TR0_L Track 0 indicator TXDn Serial transmit data UDATAn- Low signal of differential data for USB channel UDATAn+ High signal of differential data for USB channel Universal Serial Bus (USB 0 & 1), USB levels 3.4.5 UVCCn Fused power for USB channel. WDATA_L Write data WGATE_L Enables the head write circuitry WPROT_L Indicates the disk is write protected.
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Controls, LEDs, and Connectors PCI Mezzanine Card (PMC) Connectors Table 3-13 J8 and J27 Memory Mezzanine Connector (continued) 3.4.6 Pin Pin Name Pin Name Pin Pin Pin Name Pin Name Pin 39 DQ30 DQ31 40 111 A00 CS_C0_L 112 41 GND * GND * 42 113 CS_E0_L GND* 114 43 DQ32 DQ33 44 115 CS_C1_L CS_E1_L 116 45 DQ34 DQ35 46 117 WE_L RAS_L 118 47 DQ36 DQ37 48 119 GND * GND * 120 49 DQ38 DQ39 50 121 CAS_L +3.3 V 122 51 +3.3 V +3.3 V 52 123 +3.
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PCI Mezzanine Card (PMC) Connectors Controls, LEDs, and Connectors Table 3-14 PMC Connector J11 Pin Assignments (continued) Pin Signal Signal Pin 23 AD25 GND 24 25 GND C/BE3# 26 27 AD22 AD21 28 29 AD19 +5 V 30 31 VIO AD17 32 33 FRAME# GND 34 35 GND IRDY# 36 37 DEVSEL# +5 V 38 39 GND LOCK# 40 41 SDONE# SBO# 42 43 PAR GND 44 45 VIO AD15 46 47 AD12 AD11 48 49 AD09 +5 V 50 51 GND C/BE0# 52 53 AD06 AD05 54 55 AD04 GND 56 57 VIO AD03 58
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Controls, LEDs, and Connectors PCI Mezzanine Card (PMC) Connectors Table 3-15 J12 PMC Connector J12 Pin Assignments (continued) Pin Signal Signal Pin 21 GND AD26 22 23 AD24 +3.3 V 24 25 IDSEL AD23 26 27 +3.3 V AD20 28 29 AD18 GND 30 31 AD16 C/BE2# 32 33 GND IDSELB 34 35 TRDY# +3.3 V 36 37 GND STOP# 38 39 PERR# GND 40 41 +3.3 V SERR# 42 43 C/BE1# GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 +3.3 V 50 51 AD07 REQB_L 52 53 +3.
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PCI Mezzanine Card (PMC) Connectors Controls, LEDs, and Connectors Table 3-16 PMC Connector J13 Pin Assignments (continued) Pin Signal Signal Pin 19 AD57 GND 20 21 VIO AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND A D48 34 35 AD47 AD46 36 37 AD45 GND 38 39 VIO AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 G
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Controls, LEDs, and Connectors Lock Down Flash Enable Jumper Table 3-17 PMC Connector J14 Pin Assignments (continued) 3.4.
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PMC 66 Mhz Disable Jumper 3.4.8 Controls, LEDs, and Connectors PMC 66 Mhz Disable Jumper A 0.1 inch, 2-pin header (J21) located on the CPCI-6020 disables 66 MHz operation on PCI Bus B if jumpered. When a jumper is installed between pins 1 and 2, the PCI Bus B operates at 33MHz, regardless of the PMC’s capability. This jumper setting prevents the secondary Ethernet controller from being disabled if a 66 MHz capable PMC is installed.
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Controls, LEDs, and Connectors 3.4.11 Harrier Power Up Configuration Harrier Power Up Configuration An 8-pin header on the CPCI-6020 provides the means to change some of the Harrier powerup configuration settings.
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Mictor Debug Connector Controls, LEDs, and Connectors Table 3-24 J25 RISCWatch Header Pin Assignments (continued) 3.4.14 Pin Signal Signal Pin 9 CPUTMS No Connect 10 11 SRESET_L No Connect 12 13 CPURST_L VOID 14 15 CKSTPO_L GND 16 Mictor Debug Connector A 190-pin Mictor connector provides access to the processor bus (MPU Bus) and some bridge/memory controller signals. It can be used for debugging purposes. The pin assignments are listed in the following table.
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Controls, LEDs, and Connectors Mictor Debug Connector Table 3-25 J28 Debug Connector (continued) 76 Pin Signal Signal Pin 39 PD0 PD1 40 41 PD2 PD3 42 43 PD4 PD5 44 45 PD6 PD7 46 47 PD8 PD9 48 49 PD10 PD11 50 51 PD12 PD13 52 53 PD14 PD15 54 55 PD16 PD17 56 57 PD18 PD19 58 59 PA20 PD21 60 61 PD22 PD23 62 63 PD24 PD25 64 65 PD26 PD27 66 67 PD28 PD29 68 69 PD30 PD31 70 71 PD32 PD33 72 73 PD34 PD35 74 75 PD36 PD37 76 +5 V CPCI-6
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Mictor Debug Connector Controls, LEDs, and Connectors Table 3-25 J28 Debug Connector (continued) Pin Signal Signal Pin 77 PD38 PD39 78 79 PD40 PD41 80 81 PD42 PD43 82 83 PD44 PD45 84 85 PD46 PD47 86 87 PD48 PD49 88 89 PA50 PD51 90 91 PD52 PD53 92 93 PD54 PD55 94 95 PD56 PD57 96 97 PD58 PD59 98 99 PD60 PD61 100 101 PD62 PD63 102 103 PDPAR0 PDPAR1 104 105 PDPAR2 PDPAR3 106 107 PDPAR4 PDPAR5 108 109 PDPAR6 PDPAR7 110 111 Reserved Reser
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Controls, LEDs, and Connectors Mictor Debug Connector Table 3-25 J28 Debug Connector (continued) 78 Pin Signal Signal Pin 115 TT0 TSIZ0 116 117 TT1 TSIZ1 118 119 TT2 TSIZ2 120 121 TT3 Reserved 122 123 TT4 Reserved 124 125 CI_L Reserved 126 Reserved 128 +3.
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Mictor Debug Connector Controls, LEDs, and Connectors Table 3-25 J28 Debug Connector (continued) Pin Signal Signal Pin 153 CPUREQ1_L INT0_L 154 155 CPUGNT1_L MCHK0_L 156 157 WDT1TO_L SMI_L 158 159 WDT2TO_L CKSTPI_L 160 161 L2BR_L CKSTPO_L 162 163 L2BG_L HALTED 164 165 L2CLAIM_L TLBISYNC_L 166 167 Reserved TBEN 168 169 Reserved 171 Reserved 173 Reserved 170 Reserved 172 SRESET_L Reserved 174 175 HRESET_L NAPRUN 176 177 SRST1_L QREQ_L 178 179 SRESET0_
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Controls, LEDs, and Connectors 80 Mictor Debug Connector CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Functional Description 4.1 4 Overview The CPCI-6020 is a CompactPCI system slot controller based on the PowerPlus III architecture and includes support for the Motorola High Availability (HA) architecture (such as the CPX8216). It consists of the MPC7410 processor and L2 backside cache, dual Harrier System Memory Controller /PCI Host Bridge ASICs, 32 MB plus1 MB of flash memory, and 128 MB to 2 GB of ECC-protected SDRAM on mezzanines.
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Functional Description 4.2 Block Diagram Block Diagram The following figure is a block diagram of the CPCI-6020 architecture.
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Local PCI Bus Resources 4.3 Functional Description Local PCI Bus Resources As stated earlier in this chapter, the CPCI-6020 features two host bridges (provided by Harrier A and B ASICs), which allow for two independent PCI Bus hierarchies. The resources of these two buses are described in the following subsections. 4.3.1 PCI Bus A Resources The Harrier A ASIC serves as the bridge from the processor bus (marked PowerPC Bus on the block diagram) to local PCI Bus A.
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Functional Description PCI Bus A Resources The 82551IT interfaces to an AT93C46 serial EEPROM device which provides power up configuration information for the 82551IT. This is a 1 KB device organized as 64 16-bit words. Refer to the corresponding VPD information in Appendix A, Related Documentation for the contents of this device. 4.3.1.
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PCI Bus B Resources Functional Description The clock input to the Z85230 PCLK pin is a 10 MHz clock. The two ports will support data transfers up to 2.5 Mbs/sec. The Z85230 supplies an interrupt vector during a pseudo interrupt acknowledge cycle. The vector is modified based upon the interrupt source within the Z85230. All modem control lines from the ESCC are multiplexed/de-multiplexed through J3 by the P2MX function due to I/O pin limitations. 4.3.1.
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Functional Description Secondary Ethernet Channel The Harrier PCI I/O buffers operate at +3.3 V output levels and are +5 V tolerant allowing the PCI interface to operate at either voltage level. VIO is connected to +3.3 V on the planned standard product, but may be connected to +5 V by means of a build option. If VIO is connected to +5 V then 66 MHz PCI operation is prohibited and disabled by means of a build option.
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Processor Bus Resources 4.5 Functional Description Processor Bus Resources Devices resident on the processor bus of the CPCI-6020 are a single processor, two Harriers (denoted Harrier A and Harrier B) and a Mictor debug connector. The bus is the standard 60x interface running at 100 MHz. Processor address and data bus parity generation and checking is supported in conjunction with the Harrier ASICs. The MPX Bus extension, which the MCP7410 is capable of, is not supported. The MCP7410 processor uses a +2.
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Functional Description Dual Harrier Assignments z Single channel DMA controller z Message passing unit supporting I2O and generic functions z Two internal 16550-type UARTs z Two I2C Bus master interfaces z MPIC compliant interrupt controller z Four Xport channels for interfacing to flash or other external registers/devices Refer to the Harrier Application Specific Integrated Circuit (ASIC) Programmer’s Reference Guide (ASICHRA1/PG) for additional information and programming details. 4.6.
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Harrier Power-Up Configuration Functional Description Table 4-2 Harrier Power-Up Configuration Settings (continued) Harrier XAD Bus Signal Select Option Power Up Default XAD Jumpers 1111 [23:20] XAD[19] Resistor 0 Register Bit(s) Meaning of Power-Up Default State XCSR.GCSR.PUST [3:0] Generic Power Up Status Bits State of bit can be inferred: Set PCI Configuration register CLAS to present class code for “bridge device”. (Software readable header) XCSR.
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Functional Description Debug Connector Except where noted, Harrier A and Harrier B have the same default power-up setting. 4.6.3 Debug Connector One 190-pin Mictor connector with center row of power and ground pins is used to provide access to the processor bus and some miscellaneous signals. When the CPCI-6020 is populated with an MPC7410 processor this bus is not tolerant of +3.3 V or +5 V signals. Boards attached to this connector should not drive or pull signals up to intolerable levels. 4.6.
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Harrier B Memory Bus 4.7.2 Functional Description Harrier B Memory Bus Harrier B memory bus is also routed to a RAM500 compatible connector and has capabilities and characteristics identical to the Harrier A memory bus. The ECC protected memory banks on this memory bus appear as Banks C and E to Harrier B. 4.7.3 RAM500 Memory Mezzanine Each RAM500 mezzanine carries nine SDRAM parts in a x8 configuration, a buffer for certain control signals and a single +3.3 V, 256 x 8, SPD serial ROM.
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Functional Description 4.8.1 Harrier A, Channel 0 - Onboard Bank A Flash Harrier A, Channel 0 - Onboard Bank A Flash The CPCI-6020 contains one bank of flash memory soldered onboard. Bank A consists of a single Intel Strata Flash P30 16-bit flash, providing 32 MB of memory. The following table defines the flash type and size. The device support spage-read mode operations with an 4-word page size. Flash Bank A is not ECC protected. Table 4-4 Bank A Flash Options 4.8.
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Other Harrier Resources 4.9 Functional Description Other Harrier Resources The following subsections discussion other resources that are available through the Harrier ASIC. 4.9.1 I2C Bus Resources - Serial EEPROM The CPCI-6020 contains two 8 KB Serial EEPROM devices onboard and provisions for four 256-byte Serial EEPROM devices on memory mezzanines.
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Functional Description Other Board Resources asserted. The output of Harrier A Watchdog Timer 1 is routed to a Harrier A MPIC interrupt. The output of Harrier A Watchdog Timer 2 may be optionally routed by means of a build option to a Harrier A MPIC interrupt or to provide a board hard reset. The standard CPCI-6020 product will be built to provide hard reset. The output of Harrier B Watchdog Timer 1 and 2 are routed to a Harrier B MPIC interrupt.
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Onboard Power Supplies 4.10.3 Functional Description Onboard Power Supplies The CPCI-6020 requires +5 V, +3.3 V, +1.8 V and +/-12 V (optional) input voltages. The processor core voltage and +2.5 V for the Harrier core are generated on board from the +5 V input by switching regulators. The processor core voltage regulator has a variable output which is set using feedback resistors. In addition to the Harrier core voltage, the +2.
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Functional Description Board Reset Logic There is an optional build configuration for reset from the RISCWatch JTAG interface. In Option 2, the RISCWatch CPURST_L will reset the Harrier ASIC in addition to the processor. This option may be used in cases where the state of the Harrier logic must be guaranteed when a RISCWatch CPURST_L is issued.
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Soft Reset Functional Description Table 4-6 Reset Sources and Devices Affected (continued) Processo r Harrier ASIC PCI Devices ISA Devices Local CompactPCI Bus Software Hard Reset (Harrier RSTOUT, PBC Port 92) ¸ ¸ ¸ ¸ ¸ Software Hard Reset (Harrier RSTOUT, PBC Port 92) ¸ ¸ ¸ ¸ ¸ Software Hard Reset (Harrier RSTOUT, PBC Port 92) ¸ ¸ ¸ ¸ ¸ Software Hard Reset (Harrier RSTOUT, PBC Port 92) ¸ ¸ ¸ ¸ ¸ Device Affected CompactPCI Reset (21154 Bridge Control Register) Processor RISCW
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Functional Description 4.10.8 On-Board LEDs On-Board LEDs The CPCI-6020 provides two LEDs visible on the front panel for status of CPU and Board Fail (BDFL). z The green CPU LED is lit when the DBB# signal of processor bus is active (hardware controlled). z The yellow FAIL LED is lit when the Harrier BDFL bit in the Miscellaneous Control and Status register is active (software controlled).
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Local CompactPCI Bus Interface Functional Description The PCI Bus routed to the J4 connector provides the communication path to the local bridge card. There are also four signals in the J3 connector which comprise the communication with the remote bridge card. When the CPCI-6020 is in control of the local CompactPCI Bus, these signals allow the HSC on the remote bridge card to force the CPCI-6020 to quiesce the local CompactPCI Bus and tri-state its 21154.
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Functional Description EIDE Interface The HLTY# signal is driven true (low) to the CompactPCI bus J1 pin B4 when the +5.0VDC, +3.3VDC, +12VDC, and -12VDC and the J18 jumper is not installed. When the J18 jumper is installed, only +5.0VDC and +3.3VDC are included in the HLTY# status and input power supplies are all within tolerance. This can be used as a status indicator. 4.
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Asynchronous Serial Ports 4.17 Functional Description Asynchronous Serial Ports The CPCI-6020 provides two 16550 compatible asynchronous serial interfaces, COM1 and COM2. The COM1 port signals are wired to the front panel RJ-45 connector and it may optionally be wired to the backplane via J5 instead. The COM2 port is wired to the J5 connector only. COM1 is routed to an RJ-45 connector located at the rear panel of the CPCI-6020-MCPTM-01. COM2 can be accessed by a planar 9-pin header on transition module.
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Functional Description I/O Signal Multiplexing (IOMUX) 6020. MXSYNC# is used by the CPCI-6020-MCPTM-01 to synchronize with the CPCI-6020 module. MXDO is the time-multiplexed output line from the CPCI-6020 and MXDI is the timemultiplexed line from the CPCI-6020-MCPTM-01. A 16-to-1 multiplexing scheme is used with 10 MHz bit rate.
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Serial Interface Modules (SIM) Functional Description MXSYNC# is clocked out using the falling edge of MXCLK and MDXO is clocked out with the rising edge of the MXCLK. MXDI is sampled at the rising edge of MXCLK (the CPCI-6020 MTB synchronizes MXDI with MXCLK’s rising edge). The timing relationships among MXCLK, MXSYNC#, MXDO and MXDI are illustrated by the following figure: Figure 4-4 P2MX Signal Timings Time Slot 15 Time Slot 0 Time Slot 1 Time Slot 2 Time Slot 3 MMXCLK MMXSYNC# 4.
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Functional Description PMC Interface Module Form Factor depends entirely upon which, if any, PMC is installed in the CPCI-6020 PMC site. To accommodate the pluggable nature of a PMC, a custom form factor pluggable I/O module is presented here. A physical representation of the CPCI-6020-MCPTM-01 and a I/O module sample is shown below.
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PMC Interface Connector 4.23 Functional Description PMC Interface Connector The mapping used by the CPCI-6020 of the PMC I/O connectors onto the CompactPCI user I/O connectors is reversed by the CPCI-6020-MCPTM-01. This allows the designer of a PMC to create a PIM without knowledge of how the CPCI-6020 maps signals through the backplane. There is nothing to tie the PIM to the CPCI-6020 platform and in this sense the module is universal. 4.
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Functional Description 106 Mouse and Keyboard Port CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Firmware 5.1 5 PPCBug Overview The PPCBug firmware is the layer of software just above the hardware. The firmware provides the proper initialization for the devices on the CPCI-6020 baseboard upon power-up or reset. The examples in this chapter show PPCBug as the prompt; for the CPCI-6020 baseboard the actual debugger prompt will be displayed as MCP820Bug>. This chapter describes the basics of PPCBug and its architecture.
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Firmware Memory Requirements When using PPCBug, you operate out of either the debugger directory or the diagnostic directory.
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MPU, Hardware and Firmware Initialization Firmware 3. Clears all segment registers of the MPU. 4. Clears all block address translation registers of the MPU. 5. Initializes the MPU-bus-to-PCI-bus bridge device. 6. Initializes the PCI-bus-to-ISA-bus bridge device. 7. Calculates the external bus clock speed of the MPU. 8. Delays for 750 milliseconds. 9. Determines the CPU board type. 10. Sizes the local read/write memory (i.e., DRAM). 11. Initializes the read/write memory controller. 12.
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Firmware Using PPCBug 33. Executes the configured boot routine, either ROMboot, Autoboot or Network Autoboot. 34. Executes the user interface (displays the PPC-Bug> or PPC-Diag> prompt). 5.6 Using PPCBug PPCBug is command-driven. It performs its various operations in response to commands entered at the keyboard. When the PPC-Bug prompt appears on the screen, the debugger is ready to accept debugger commands.
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Debugger Commands Firmware The later is accomplished by entering HE, followed by a space, followed by the test category description (e.g., UART), followed by a carriage return.
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Firmware Debugger Commands Table 5-1 Debugger Commands (continued) 112 Command Description HE Help on Command(s) IBM Indirect Block Move IDLE Idle Master MPU IOC I/O Control for Disk IOI I/O Inquiry IOP I/O Physical to Disk IOT I/O "Teach" for Configuring Disk Controller IRD Idle MPU Register Display IRM Idle MPU Register Modify IRS Idle MPU Register Set LO Load S-Records from Host M "Alias" for "MM" Command MA Macro Define/Display MAE Macro Edit MAL Enable Macro Expansion
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Debugger Commands Firmware Table 5-1 Debugger Commands (continued) Command Description NOPF Port Detach NORB No ROM Boot NOSYM Detach Symbol Table NPING Network Ping OF Offset Registers Display/Modify PA Printer Attach PBOOT Bootstrap Operating System PCIDOM PCI Domain Control PCIIOI PCI Slot Status Display PEEPROM Read/Write/Verify the HSC/Bridge's EEPROM PF Port Format PFLASH Program FLASH Memory PS Put RTC Into Power Save Mode for Storage PWROFF Power Off PCI Slot/Power Sup
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Firmware Diagnostic Tests Table 5-1 Debugger Commands (continued) Command Description WL Write Loop Data Loss Although a command that allows erasing and reprogramming of flash memory is available, note that reprogramming any portion of the CPCI-6020 baseboard’s flash memory (Bank B) will erase everything currently contained in the baseboard flash, including the PPCBug debugger. Use caution when reprogramming or erasing flash memory.
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Diagnostic Tests Firmware Test sets marked with an asterisk (*) are not available on the CPCI-6020, unless SCSI or video PMCs are installed.
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Firmware 116 Diagnostic Tests CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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RAM500 Memory Expansion Module 6.1 6 Overview The RAM500 memory expansion module is used on the CPCI-6020 as its on-board memory capability. No on-board memory exists on the CPCI-6020; therefore, the CPCI-6020 will not function properly without at least one RAM500 memory module installed. Each expansion module is a single bank of SDRAM with up to 512 MB of available ECC memory.
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RAM500 Memory Expansion Module RAM500 Module Installation The RAM500 memory expansion module is connected to the host board with a 140-pin AMP 0.6mm Free Height plug connector. If the expansion module is designed to accommodate another RAM500 module, the bottom expansion module will have two 140-pin AMP connectors installed: one on the bottom side of the module, and one on the top side of the module. The RAM500 memory expansion module draws +3.3 V through this connector.
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Features RAM500 Memory Expansion Module 5. With standoffs installed in the three mounting holes on the RAM500 module, align the standoffs and the P1 connector on the module with the three holes on the J7 or J28 connector on the CPCI-6020 host board and press the two connectors together until they are firmly seated in place. 6.
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RAM500 Memory Expansion Module 6.4.2 Host Clock Logic Host Clock Logic The host board provides four SDRAM clocks to the memory expansion connector. The frequency of the RAM500 CLKS is the same as the host board. 6.4.3 Serial Presence Detect (SPD) Data This register is partially described for the RAM500 within the CPCI-6020 Single Board Computer Programmer’s Reference Guide. The register is accessed through the I2C interface of the Harrier ASIC on the host board (CPCI-6020).
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Bottom Side Memory Expansion Connector (P1) RAM500 Memory Expansion Module Table 6-3 RAM500 Bottom Side Connector (P1) Pin Assignments (continued) Pin Signal Signal Pin 13 DQ08 DQ09 14 15 DQ10 DQ11 16 17 DQ12 DQ13 18 19 DQ14 DQ15 20 21 GND* GND* 22 23 DQ16 DQ17 24 25 DQ18 DQ19 26 27 DQ20 DQ21 28 29 DQ22 DQ23 30 31 +3.3 V +3.
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RAM500 Memory Expansion Module Bottom Side Memory Expansion Connector (P1) Table 6-3 RAM500 Bottom Side Connector (P1) Pin Assignments (continued) Pin Signal Signal Pin 83 CKD00 CKD01 84 85 CKD02 CKD03 86 87 CKD04 CKD05 88 89 +3.3 V +3.3 V 90 91 CKD06 CKD07 92 93 BA1 BA0 94 95 A12 A11 96 97 A10 A09 98 99 GND* GND* 100 101 A08 A07 102 103 A06 A05 104 105 A04 A03 106 107 A02 A01 108 109 +3.3 V +3.
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Top Side Memory Expansion Connector (J1) 6.5.2 RAM500 Memory Expansion Module Top Side Memory Expansion Connector (J1) The top side memory expansion connector is a 140-pin AMP 0.6 mm Free Height receptacle. This receptacle includes common ground contacts that mate with standard AMP plug assemblies or AMP GIGA assemblies with ground plates. A single memory module will have one bank of SDRAM for a maximum of 256 MB of memory.
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RAM500 Memory Expansion Module Top Side Memory Expansion Connector (J1) Table 6-4 RAM500 Top Side Connector (J1) Pin Assignments (continued) Pin Signal Signal Pin 59 DQ46 DQ47 60 61 GND* GND* 62 63 DQ48 DQ49 64 65 DQ50 DQ51 66 67 DQ52 DQ53 68 69 +3.3 V +3.3 V 70 71 DQ54 DQ55 72 73 DQ56 DQ57 74 75 DQ58 DQ59 76 77 DQ60 DQ61 78 79 GND* GND* 80 81 DQ62 DQ63 82 83 CKD00 CKD01 84 85 CKD02 CKD03 86 87 CKD04 CKD05 88 89 +3.3 V +3.
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RAM500 Programming Issues RAM500 Memory Expansion Module Table 6-4 RAM500 Top Side Connector (J1) Pin Assignments (continued) Pin Signal 131 133 GND Signal Pin GND 132 SDRAMCLK3 134 135 +3.3 V 136 137 SDRAMCLK4 138 GND* 140 139 GND* *Common GND pins mate to GIGA assemblies with ground plates. 6.6 RAM500 Programming Issues The RAM500 contains no user programmable registers other than the Serial Presence Detect (SPD) Data.
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RAM500 Memory Expansion Module 126 RAM500 Programming Issues CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Transition Module Preparation and Installation 7.1 7 Overview This chapter provides hardware preparation and installation instructions, as well as pin assignment information for the CPCI-6020-MCPTM-01 transition module. The CPCI-6020MCPTM-01 is an optional module that is used in conjunction with the CPCI-6020 series of Single Board Computers.
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Transition Module Preparation and Installation General Description CPCI-6020-MCPTM-01 supports one single-wide (74 mm wide by 69 mm long) PMC Interface Module (PIM). PMC I/O pins 1 through 64 of the PMC interface are routed from the CPCI-6020 J3 and J5 connectors. For a detailed description of the PMC Interface Module see PMC Interface Module (PIM) on page 100. Besides these, CPCI-6020-MCPTM-01 supports two synchronous Serial Interface Modules (SIMs).
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Component Layout 7.2.1 Transition Module Preparation and Installation Component Layout The next figure shows the layout of the CPC-6020-MCPTM-01 major components.
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Transition Module Preparation and Installation 7.2.2 Rear Panel Connectors Rear Panel Connectors The next figure shows the location of all connectors and the PMC cutout of the CPCI-6020MCPTM-01.
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Unpacking and Inspecting the RTM 7.3 Transition Module Preparation and Installation Unpacking and Inspecting the RTM Read all notices and cautions prior to unpacking the product. Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten their life. Before touching the AMC or electronic components, make sure that you are working in an ESD-safe environment. Shipment Inspection To inspect the shipment, perform the following steps: 1.
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Transition Module Preparation and Installation Serial Ports 3 and 4 These asynchronous serial ports (COM1 and COM2) are configured permanently as data circuit-terminating equipment (DTE). A terminal for COM1 may be connected to either the processor board or the transition module, but not both. 7.4.2 Serial Ports 3 and 4 The two synchronous serial ports, COM3 and COM4, are implemented with the Z85230 ESCC on the CPCI-6020.
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Serial Interface Module Circuitry Transition Module Preparation and Installation Headers J17 and J16 are used to configure serial ports 3 and 4 respectively, in tandem with the proper SIM selection. With a jumper across pins 1 and 2 on either header, the port is configured as DTE. With a jumper across pins 2 and 3, the port is configured as DCE. It is important to note that the jumper setting of the port must match the configuration of the corresponding SIM module.
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Transition Module Preparation and Installation Serial Interface Module Circuitry The EIA-232-D SIMs employ MC145406 ICs as line transmitters to convert the TTL output signals from the CPCI-6020 module to EIA-232-D voltage levels. As line receivers, the MC145406 ICs convert the EIA-232-D input signals to TTL voltage levels which are sent to the CPCI-6020. For all port interfaces, the SIMs support the transmitter signal element timing as either input or output signals.
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Port Configuration 7.4.4 Transition Module Preparation and Installation Port Configuration The following interface configuration diagrams describe the interface between the CPCI-6020 and CPCI-6020-MCPTM-01.
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Transition Module Preparation and Installation Figure 7-6 Installing the SIMs EIA-232-D DTE Ports 3 and 4 Configuration COM3 COM4 Z85230 SCC TXD TXD RTS# RTS# RXD RXD CTS# CTS# DCD# DCD# ETXC 3 2 TRXC TXC# 1 RTXC J3/MX J17, J16 RXC Z8536 CIO DTR DTR# LL LLB# RL RLB# DSR# DSR# RI# RI# TM# TM# GND# CPCI-6020 7.
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Installing the SIMs Transition Module Preparation and Installation Procedure You must set the jumpers and install the SIMs prior to installing the CPCI-6020-MCPTM-01 transition module in the system chassis. 1. Align the SIM so that P1 on the SIM align with the appropriate SIM connector (J12 for COM3 and J13 for COM4) on the transition module. Note the position of the alignment key on P1. Refer to the following figure. 2.
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Transition Module Preparation and Installation Installing the PIM 3. Gently press the top of the SIM to seat it on the transition module SIM connector. If the SIM does not seat with gentle pressure, recheck the alignment of the connectors. Do not force the SIM onto the transition module. 4. Secure the SIM to the transition module standoffs with the two Phillips-head screws provided. Do not over tighten the screws. 7.
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Installing the PIM Transition Module Preparation and Installation 6. Slide the face plate (front bezel) of the PIM module into the front panel opening from behind and place the PIM module on top of the transition module, aligned with the appropriate two PIM connectors (P0 and P4). The two connectors on the underside of the PIM module should then connect smoothly with the corresponding connectors on the transition module (J10 and J14). Refer to the following figure for proper screw/board alignment.
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Transition Module Preparation and Installation 7.7 Installing and Removing the Transition Module Installing and Removing the Transition Module Personal Injury or Death Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing and adjusting. Product Damage Avoid touching areas of integrated circuitry; static discharge can damage these circuits.
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Connectors and Cables Transition Module Preparation and Installation Removal Procedure Although the CPCI-6020 Single Board Computer can be removed and inserted while power is applied, the CPCI-6020-MCPTM-01 transition module is not hot swap capable. Inserting or removing the transition module while the CPU board is active may affect the normal operation of the CPU board.
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Transition Module Preparation and Installation Connectors and Cables Table 7-2 Rear Transition Module Connectors/Headers (continued) Type Number Description Serial Port 4 J17 3-pin header for selection of DTE or DCE interface Floppy Power J18 Stand-alone 4-pin power header for floppy PLD JTAG J19 8-pin programming header COM1 Port J20 3-pin header sets serial port 1 from PIM or CPCI-6020 Speaker Header J21 For onboard speaker access.
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Connector Pin Assignments 7.9 Transition Module Preparation and Installation Connector Pin Assignments The following tables summarize the pin assignments of RTM connectors that are specific to the CPCI-6020 modules configured for use with the CPCI-6020-MCPTM-01 transition module. 7.9.1 CompactPCI Connectors Connector J3 is a 95-pin AMP Z-pack 2 mm hard metric type B connector.
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Transition Module Preparation and Installation PMC I/O Module Connector Table 7-4 PMC I/O Module - Host I/O Connector Pin Assignments (continued) Pin Signal Signal Pin 21 +5 V IN2_RI 22 23 Reserved Reserved 24 25 Reserved +3.3 V 26 27 Reserved Reserved 28 29 GND Reserved 30 31 Reserved Reserved 32 33 Reserved GND 34 35 Reserved Reserved 36 37 +5 V Reserved 38 39 Reserved Reserved 40 41 Reserved +3.
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PMC I/O Module Connector Transition Module Preparation and Installation Table 7-5 PMC I/O Module - PMC I/O Connector Pin Assignments (continued) Pin Signal Signal Pin 15 PMC IO15 PMC IO16 16 17 PMC IO17 PMC IO18 18 19 PMC IO19 PMC IO20 20 21 PMC IO21 PMC IO22 22 23 PMC IO23 PMC IO24 24 25 PMC IO25 PMC IO26 26 27 PMC IO27 PMC IO28 28 29 PMC IO29 PMC IO30 30 31 PMC IO31 PMC IO32 32 33 PMC IO33 PMC IO34 34 35 PMC IO35 PMC IO36 36 37 PMC IO37 PMC IO38 38 39
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Transition Module Preparation and Installation 7.9.3 10BaseT/100BaseTx Connectors 10BaseT/100BaseTx Connectors Two 10BaseT/100BaseTx RJ-45 connectors are located on the rear panel of the CPCI-6020MCPTM-01 to support Ethernet I/O from the CPCI-6020. One channel is always routed from the CPCI-6020, the other is a custom-build option. Enabling this option requires that the proper zero ohm resistors be installed on the CPCI-6020.
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COM2 Header 7.9.5 Transition Module Preparation and Installation COM2 Header One 9-pin planar header is located on the CPCI-6020-MCPTM-01 to provide the interface to the COM2 serial port. This port can be configured as either DCE or DTE. The pin assignments for this header are as follows: Table 7-8 COM2 Header Pin Assignments 7.9.
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Transition Module Preparation and Installation Floppy Port Header Table 7-9 EIDE Header Pin Assignments (continued) 7.9.7 Pin Signal Signal Pin 39 No Connect GND 40 Floppy Port Header The CPCI-6020-MCPTM-01 provides a 34-pin header to interface to a floppy disk drive. The pin assignments and signal mnemonics for this connector are listed below. Table 7-10 Floppy Header Pin Assignments 7.9.
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Keyboard/Mouse Connector Transition Module Preparation and Installation Table 7-11 +5Vdc Power Connector (continued) 7.9.9 Pin Signal 4 No Connect Keyboard/Mouse Connector The keyboard/mouse interface is provided by a 6-pin circular DIN connector. To use the keyboard function only, a keyboard may be connected directly to this connector. To use both the keyboard and the mouse functions, use the Y-adapter cable provided with the CPCI-6020MCPTM-01. Refer to the following table for pin assignments.
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Transition Module Preparation and Installation Speaker Output Header Table 7-13 Sync/Async Serial Connector Pin Assignments (continued) 7.9.
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CNFG and ENV Commands 8.1 8 Overview You can use the factory-installed debug monitor, PPCBug, to modify certain parameters contained in the board's Non-Volatile RAM (NVRAM), also known as Battery Backed-up RAM (BBRAM). z The Board Information Block in NVRAM contains various elements concerning operating parameters of the hardware. Use the PPCBug command CNFG to change those parameters. z Use the PPCBug command ENV to change configured PPCBug parameters in NVRAM.
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CNFG and ENV Commands ENV - Set Environment The value or identifier to the right of the equal sign is displayed as left-justified character (ASCII) strings padded with space characters, and quotes (“) are displayed to indicate the size of the string. Values that are not in quotes are considered data strings, and data strings are rightjustified. The data strings are padded with zeroes if the length is not met.
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Configuring the PPCBug Parameters CNFG and ENV Commands Field Service Menu Enable [Y/N] = N? Y Display the field service menu. N Do not display the field service menu. (Default) Probe System for Supported I/O Controllers [Y/N] = Y? Y Accesses will be made to the appropriate system busses (e.g., VMEbus, local MPU Bus) to determine the presence of supported controllers. (Default) N Accesses will not be made to the VMEbus to determine the presence of supported controllers.
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CNFG and ENV Commands Configuring the PPCBug Parameters If the board has a secondary SCSI controller, this number is the secondary SCSI ID or address. For the CPCI-6020, all PCI add-on SCSI controllers/adapters supported by PPCBug are set to the SCSI ID value entered here. NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N? Y Give boot priority to devices defined in the fw-boot-path global environment variable (GEV). N Do not give boot priority to devices listed in the fw-boot-path GEV.
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Configuring the PPCBug Parameters CNFG and ENV Commands This is the listing of boot devices displayed if the Autoboot Scan option is enabled. If you modify the list, follow the format shown above (uppercase letters, using forward slash as separator). Auto Boot Controller LUN = 00? Refer to the PPCBug Firmware Package User's Manual for a listing of disk/tape controller modules currently supported by PPCBug.
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CNFG and ENV Commands Configuring the PPCBug Parameters The last location tested when PPCBug searches for a ROMboot module. (Default = $FFFFFFFC) Network Auto Boot Enable [Y/N] = N? Y The Network Auto Boot (NETboot) function is enabled. N The NETboot function is disabled. (Default) Network Auto Boot at power-up only [Y/N] = N? Y NETboot is attempted at power-up reset only. N NETboot is attempted at any reset.
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Configuring the PPCBug Parameters CNFG and ENV Commands The address where the network interface configuration parameters are to be saved/retained in NVRAM; these parameters are the necessary parameters to perform an unattended network boot. A typical offset might be $1000, but this value is application-specific. (Default = $00001000) Data Loss If you use the NIOT debugger command, these parameters need to be saved somewhere in the offset range $00001000 through $000016F7.
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CNFG and ENV Commands Configuring the PPCBug Parameters Stop Auto Boot after selftest failure [Y/N] = N? Y If selftest fails do not autoboot. N Selftest results do not affect autoboot process. Memory Size Enable [Y/N] = Y? Y Memory will be sized for Self Test diagnostics. N Memory will not be sized for Self Test diagnostics. Memory Size Starting Address = 00000000? The default Starting Address is $00000000.
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Configuring the PPCBug Parameters CNFG and ENV Commands PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A050900 Initializes the PIRQx (PCI Interrupts) route control registers in the IBC (PCI/ISA Bus bridge controller). The ENV parameter is a 32-bit value that is divided by 4 to yield the values for route control registers PIRQ0/1/2/3. The default is determined by system type.
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CNFG and ENV Commands Configuring the PPCBug Parameters The Firmware Command Buffer contents contain the BUG commands which are executed upon firmware startup. BUG commands you will place into the command buffer should be typed just as you enter the commands from the command line. The string NULL on a new line terminates the command line entries. All BUG commands except for the following may be used within the command buffer: DU, ECHO, LO, TA, VE.
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A Related Documentation A.1 A Embedded Communications Computing Documents The Motorola publications listed below are referenced in this manual, or apply to systems that use this product. You can obtain electronic copies of Embedded Communications Computing publications by: z Contacting your local Motorola sales office, or z Visiting Motorola Embedded Communications Computing Groups’s World Wide Web literature site, http://www.motorola.com/computer/literature.
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Related Documentation Related Specifications Table A-2 Manufacturers’ Documents (continued) Document Title and Source Publication Number or Search Term MPC7410 RISC Microprocessor User’s Manual MPC7410UM/D PowerPC Microprocessor Family: The Programming Environments PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture (CHRP), Version 1.0 MPCFPE/AD TB338/D OR IBM Microelectronics MPRPPCFPE-01 /http://www.ibm.com/ A.3 Atmel Corporation http://www.atmel.
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Related Specifications Related Documentation Table A-3 Related Specifications (continued) Document Title and Source Publication Number or Search Term IEEE - PCI Mezzanine Card Specification (PMC) P1386.1 Draft 2.0 IEEE Standard for Local Area Networks: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications IEEE 802.3 PCI Special Interest Group (PCI SIG) http://www.pcisig.
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Related Documentation 164 Related Specifications CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Index Symbols +5Vdc power connector (CPCI-6020-MCPTM-01) 148 A accessing PPCBug 110 B Board Information Block (BIB), changing 152 Board Information Block, PPCBug 151 bridges (21154) as interface 83 bridges, description 81 buffers, primary/secondary bus 83 buses, (PCI) described 83 C checksum, affects on PPCBug 108 CNFG, use 151 COM1 connector (CPCI-6020-MCPTM-01) 146 COM2 header (CPCI-6020-MCPTM-01) 147 command list, PPCBug 110 CompactPCI interface connectors 60 CompactPCI bus remote expansion 83 Compac
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Secondary SCSI Identified 153 Serial Startup Code LF Enable 159 Serial Startup Code Master Enable 159 Stop Auto Boot after selftest failure 158 Watchdog prior status ignored at Autoboot 157 Watchdog reset at board reset 157 Watchdog shutdown at board reset 157 environmental requirements 32, 35, 131 ESD precautions 47 Ethernet channel, primary 83 Ethernet connector (CPCI-6020-MCPTM-01) 146 F features (CPCI-6020) 31 firmware PPCBug commands 111 PPCBug components 107 PPCBug diagnostic test groups 115 PPCBug d
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R COM3/COM4 132 RAM500 as memory requirement for CPCI-6020 117 bottom side connector (P1) 120 bottom side connector pin outs (P1] 120 description 117 installation 118 memory block size 117 memory connector described 118 memory expansion connector 123 RAM500 bottom side connector (P1) 120 RAM500 connectors, description 120 rear panel I/O 37 reprogram flash, risk 114 S SD command 114 SDRAM management of 117 RAM500 as memory module 117 serial ports 84 COM1/COM2 131 167 SIM circuitry described 133 installa
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CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)