DSP56000 24-BIT DIGITAL SIGNAL PROCESSOR FAMILY MANUAL Motorola, Inc.
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Order this document by DSP56KFAMUM/AD MOTOROLA SEMICONDUCTOR TECHNICAL DATA DSP56K Family Addendum to 24-bit Digital Signal Processor Family Manual This document, containing changes, additional features, further explanations, and clarifications, is a supplement to the original document: DSP56KFAMUM/AD Family Manual DSP56K Family 24-bit Digital Signal Processors Change the following: Page 11-4, Section 11.2.1 - Delete “4. NeXTTM under Mach”.
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TABLE OF CONTENTS Paragraph Number Title Page Number SECTION 1 DSP56K FAMILY INTRODUCTION 1.1 1.2 1.3 1.4 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3 ORIGIN OF DIGITAL SIGNAL PROCESSING . . . . . . . . . . . . . . . . . . . . . . . .1-3 SUMMARY OF DSP56K FAMILY FEATURES . . . . . . . . . . . . . . . . . . . . . . . .1-9 MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents (Continued) Paragraph Number 3.5 3.6 Title Page Number DATA ALU PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19 DATA ALU SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19 SECTION 4 ADDRESS GENERATION UNIT 4.1 4.2 4.3 4.4 ADDRESS GENERATION UNIT AND ADDRESSING MODES . . . . . . . . . . .4-3 AGU ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents (Continued) Paragraph Number 7.4 7.5 7.6 Title Page Number RESET PROCESSING STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-33 WAIT PROCESSING STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-36 STOP PROCESSING STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-37 SECTION 8 PORT A 8.1 8.2 PORT A OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents (Continued) Paragraph Number 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 Title SECTION 11 ADDITIONAL SUPPORT Page Number USER SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3 MOTOROLA DSP PRODUCT SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . .11-4 DSP56KADSx APPLICATION DEVELOPMENT SYSTEM . . . . . . . . . . . . .11-6 Dr. BuB ELECTRONIC BULLETIN BOARD . . . . . . . . . . . . . . . . . . . . . . .
LIST of FIGURES Figure Number Title Page Number 1-1 1-2 1-3 Analog Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 DSP Hardware Origins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 2-1 DSP56K Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures (Continued) Figure Number Title Page Number 4-14 4-15 Bit-Reverse Address Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Address Modifier Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 Program Address Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP56K Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures (Continued) Figure Number Title Page Number 7-13 7-14 7-15 7-16 7-17 7-18 7-19 Interrupting an REP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupting Sequential REP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simultaneous Wait Instruction and Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .
LIST of TABLES Table Number Title Page Number 1-1 Benchmark Summary in Instruction Cycles . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 3-1 Limited Data Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 4-1 4-2 4-3 Address Register Indirect Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Address Modifier Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables (Continued) Table Number Title Page Number A-10 Bit Manipulation Timing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 Jump Instruction Timing Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12 RTI/RTS Timing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13 Addressing Mode Timing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14 Memory Access Timing Summary . . . . . . . . . .
List of Tables (Continued) Table Number xii Title LIST of TABLES Page Number MOTOROLA
SECTION 1 DSP56K FAMILY INTRODUCTION MOTOROLA DSP56K FAMILY INTRODUCTION 1-1
SECTION CONTENTS SECTION 1.1 INTRODUCTION ........................................................................ 3 SECTION 1.2 ORIGIN OF DIGITAL SIGNAL PROCESSING .......................... 3 SECTION 1.2 SUMMARY OF DSP56K FAMILY FEATURES .......................... 9 SECTION 1.3 MANUAL ORGANIZATION ........................................................
INTRODUCTION 1.1 INTRODUCTION The DSP56K Family is Motorola’s series of 24-bit general purpose Digital Signal Processors (DSPs*). The family architecture features a central processing module that is common to the various family members, such as the DSP56002 and the DSP56004. Note: The DSP56000 and the DSP56001 are not based on the central processing module architecture and should not be used with this manual. They will continue to be described in the DSP56000/DSP56001 User’s Manual (DSP56000UM/AD Rev. 2).
ORIGIN OF DIGITAL SIGNAL PROCESSING ANALOG FILTER Rf Cf x(t) x(t) INPUT FROM SENSOR - y(t) Ri + y(t) OUTPUT TO ACTUATOR t Rf 1 y(t ) --------- = – ------ -----------------------------R i 1 + jwR f C f x(t) FREQUENCY CHARACTERISTICS GAIN IDEAL FILTER f fc FREQUENCY Figure 1-1 Analog Signal Processing The equivalent circuit using a DSP is shown in Figure 1-2. This application requires an analog-to-digital (A/D) converter and digital-to-analog (D/A) converter in addition to the DSP.
ORIGIN OF DIGITAL SIGNAL PROCESSING • • • • • • • • Fewer components Stable, deterministic performance Wide range of applications High noise immunity and power-supply rejection LOW-PASS SAMPLER AND ANTIALIASING ANALOG-TO-DIGITAL FILTER CONVERTER Self-test can be built in No filter adjustments Filters with much closer tolerances Adaptive filters easily implemented DSP OPERATION DIGITAL-TO-ANALOG RECONSTRUCTION CONVERTER LOW-PASS FILTER FIR FILTER N ∑ c(k ) × (n – k ) A/D x(t) x(n) D/A k=0
ORIGIN OF DIGITAL SIGNAL PROCESSING The DSP56K family is not designed for a particular application but is designed to execute commonly used DSP benchmarks in a minimum time for a single-multiplier architecture. For example, a cascaded, 2nd-order, four-coefficient infinite impulse response (IIR) biquad section has four multiplies for each section. For that algorithm, the theoretical minimum number of operations for a single-multiplier architecture is four per section.
ORIGIN OF DIGITAL SIGNAL PROCESSING Digital Filtering Finite Impulse Response (FIR) Infinite Impulse Response (IIR) Matched Filters (Correlators) Hilbert Transforms Windowing Adaptive Filters/Equalizers Signal Processing Compression (e.g., Linear Predictive Coding of Speech Signals) Expansion Averaging Energy Calculations Homomorphic Processing Mu-law/A-law to/from Linear Data Conversion Data Processing Encryption/Scrambling Encoding (e.g., Trellis Coding) Decoding (e.g.
ORIGIN OF DIGITAL SIGNAL PROCESSING Image Processing Pattern Recognition Optical Character Recognition Image Restoration Image Compression Image Enhancement Robot Vision Graphics 3-D Rendering Computer-Aided Engineering (CAE) Desktop Publishing Animation Instrumentation Spectral Analysis Waveform Generation Transient Analysis Data Acquisition Speech Processing Speech Synthesizer Speech Recognizer Voice Mail Vocoder Speaker Authentication Speaker Verification Audio Signal Processing Digital AM/FM Radio Digi
SUMMARY OF DSP56K FAMILY FEATURES architecture matches the shape of the MAC operation. The two operands, C() and X(), are directed to a multiply operation, and the result is summed. This process is built into the chip by using two separate memories (X and Y) to feed a single-cycle MAC. The entire process must occur under program control to direct the correct operands to the multiplier and save the accumulator as needed.
SUMMARY OF DSP56K FAMILY FEATURES • Precision — The data paths are 24 bits wide, providing 144 dB of dynamic range; intermediate results held in the 56-bit accumulators can range over 336 dB. • Parallelism — Each on-chip execution unit (AGU, program control unit, data ALU), memory, and peripheral operates independently and in parallel with the other units through a sophisticated bus system.
MANUAL ORGANIZATION • DSP56001 Compatibility — All members of the DSP56K family are downward compatible with the DSP56001, and also have added flexibility, speed, and functionality. • Low Power — As a CMOS part, the DSP56000/DSP56001 is inherently very low power and the STOP and WAIT instructions further reduce power requirements. 1.
MANUAL ORGANIZATION Section 7 – Processing States This section describes the five processing states (normal, exception, reset, wait, and stop). Section 8 – Port A This section describes the external memory port, its control register, and control signals. Section 9 – PLL Clock Oscillator This section describes the PLL and its functions Section 10 – On-Chip Emulator (OnCE) This section describes the OnCE circuitry and its functions.
SECTION 2 DSP56K CENTRAL ARCHITECTURE OVERVIEW MOTOROLA DSP56K CENTRAL ARCHITECTURE OVERVIEW 2-1
SECTION CONTENTS SECTION 2.1 DSP56K CENTRAL ARCHITECTURE OVERVIEW ..................3 SECTION 2.2 DATA BUSES .............................................................................3 SECTION 2.3 ADDRESS BUSES .....................................................................4 SECTION 2.4 DATA ALU ..................................................................................5 SECTION 2.5 ADDRESS GENERATION UNIT ................................................5 SECTION 2.6 PROGRAM CONTROL UNIT ..
DSP56K CENTRAL ARCHITECTURE OVERVIEW 2.1 DSP56K CENTRAL ARCHITECTURE OVERVIEW The DSP56K family of processors is built on a standard central processing module. In the expansion area around the central processing module, the chip can support various configurations of memory and peripheral modules which may change from family member to family member. This section introduces the architecture and the major components of the central processing module.
ADDRESS BUSES EXPANSION AREA Y MEMORY RAM/ROM EXPANSION EXTERNAL ADDRESS BUS SWITCH BUS CONTROL PORT A YAB XAB PAB ADDRESS GENERATION UNIT ADDRESS PERIPHERAL PINS 24-Bit 56K Module X MEMORY RAM/ROM EXPANSION CONTROL PROGRAM RAM/ROM EXPANSION PERIPHERAL MODULES YDB XDB PDB EXTERNAL DATA BUS SWITCH DATA INTERNAL DATA BUS SWITCH GDB PLL CLOCK GENERATOR PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLER PROGRAM ADDRESS GENERATOR DATA ALU 24X24+56→56-BIT MAC TWO 56-BIT ACCUMULATORS On
DATA ALU ory spaces are addressed over a single 16-bit unidirectional address bus driven by a three-input multiplexer that can select the XAB, the YAB, or the PAB. Only one external memory access can be made in an instruction cycle. There is no speed penalty if only one external memory space is accessed in an instruction cycle. However, if two or three external memory spaces are accessed in a single instruction, there will be a one or two instruction cycle execution delay, respectively.
MEMORY EXPANSION PORT (PORT A) rectly addressable registers: the program counter (PC), loop address (LA), loop counter (LC), status register (SR), operating mode register (OMR), and stack pointer (SP). The 16-bit PC can address 65,536 locations in program memory space. There are four mode and interrupt control pins that provide input to the program interrupt controller.
SECTION 3 DATA ARITHMETIC LOGIC UNIT MOTOROLA DATA ARITHMETIC LOGIC UNIT 3-1
SECTION CONTENTS SECTION 3.1 DATA ARITHMETIC LOGIC UNIT ............................................. 3 SECTION 3.2 OVERVIEW AND DATA ALU ARCHITECTURE ....................... 3 3.2.1 Data ALU Input Registers (X1, X0, Y1, Y0) ........................................ 5 3.2.2 MAC and Logic Unit ............................................................................ 6 3.2.3 Data ALU A and B Accumulators ........................................................ 7 3.2.4 Accumulator Shifter ..................
DATA ARITHMETIC LOGIC UNIT 3.1 DATA ARITHMETIC LOGIC UNIT This section describes the operation of the Data ALU registers and hardware. It discusses data representation, rounding, and saturation arithmetic used within the Data ALU, and concludes with a discussion of the programming model. 3.2 OVERVIEW AND DATA ALU ARCHITECTURE As described in Section 2, The DSP56K family central processing module is composed of three execution units that operate in parallel.
OVERVIEW AND DATA ALU ARCHITECTURE EXPANSION AREA Y MEMORY RAM/ROM EXPANSION EXTERNAL ADDRESS BUS SWITCH BUS CONTROL PORT A YAB XAB PAB ADDRESS GENERATION UNIT ADDRESS PERIPHERAL PINS 24 Bit 56K Module X MEMORY RAM/ROM EXPANSION CONTROL PROGRAM RAM/ROM EXPANSION PERIPHERAL MODULES YDB XDB PDB EXTERNAL DATA BUS SWITCH DATA INTERNAL DATA BUS SWITCH GDB PLL CLOCK GENERATOR PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLER PROGRAM ADDRESS GENERATOR DATA ALU 24X24+56→56-BIT MAC TWO 56
OVERVIEW AND DATA ALU ARCHITECTURE 3.2.1 Data ALU Input Registers (X1, X0, Y1, Y0) X1, X0, Y1, and Y0 are four 24-bit, general-purpose data registers. They can be treated as four independent, 24-bit registers or as two 48-bit registers called X and Y, developed by concatenating X1:X0 and Y1:Y0, respectively. X1 is the most significant word in X and Y1 is the most significant word in Y. The registers serve as input buffer registers between the XDB or YDB and the MAC unit.
OVERVIEW AND DATA ALU ARCHITECTURE register contents. The registers may also be read back out to the appropriate data bus to implement memory-delay operations and save/restore operations for interrupt service routines. 3.2.2 MAC and Logic Unit The MAC and logic unit shown in Figure 3-3 conduct the main arithmetic processing and perform all calculations on data operands in the DSP.
OVERVIEW AND DATA ALU ARCHITECTURE 24 BITS 48 BITS 56 BITS X0,X1, X0,X1, X0,X1, Y0, OR Y1 Y0, OR Y1 Y0, OR Y1 24-BITx24-BIT FRACTIONAL MULTIPLIER S H I F T E R 56 - BIT ARITHMETIC AND LOGIC UNIT R24 + – CONVERGENT - ROUNDING FORCING FUNCTION SCALING MODE BITS CONDITION CODE GENERATOR ACCUMULATOR A ACCUMULATOR B Figure 3-3 MAC Unit 3.2.3 Data ALU A and B Accumulators The Data ALU features two general-purpose, 56-bit accumulators, A and B.
OVERVIEW AND DATA ALU ARCHITECTURE DATA ALU ACCUMULATOR REGISTERS Accumulator B Accumulator A * 55 A2 7 0 23 EXT 0 A1 A0 0 23 MSP * 0 LSP 55 B2 7 0 23 EXT 0 B1 B0 0 23 MSP 0 LSP *Read as sign extension bits, written as don’t care. Figure 3-4 DATA ALU Accumulator Registers significant product (LSP) is stored in A0 or B0 as shown in Figure 3-4. Overflow occurs when a source operand requires more bits for accurate representation than are available in the destination.
OVERVIEW AND DATA ALU ARCHITECTURE shifting and limiting are not performed. 3.2.4 Accumulator Shifter The accumulator shifter (see Figure 3-3) is an asynchronous parallel shifter with a 56-bit input and a 56-bit output that is implemented immediately before the MAC accumulator input. The source accumulator shifting operations are as follows: • • • • No Shift (Unmodified) 1-Bit Left Shift (Arithmetic or Logical) ASL, LSL, ROL 1-Bit Right Shift (Arithmetic or Logical) ASR, LSR, ROR Force to zero 3.2.
DATA REPRESENTATION AND ROUNDING WITHOUT LIMITING* 55 0 0...0 100...........00 7 WITH LIMITING* 0 23 00............00 0 23 55 A = +1.0 0 0 0. . . 0 1 0 0 . . . . . . . . . . . 0 0 7 0 23 23 0 0 23 A = +1.0 0 MOVE A, X0 MOVE A1, X0 100...........00 00............00 X0 = -1.0 011...........11 |ERROR| = 2.0 23 0 X0 = +0.9999999 |ERROR| = .0000001 * Limiting automatically occurs when the 56 - bit operands A or B (not A2, A1, A0, B2, B1, or B0) are read.
DATA REPRESENTATION AND ROUNDING Table 3-1 Limited Data Values Destination Memory Reference Source Operand Accumulator Sign Limited Value (Hexadecimal) XDB YDB Type of Access X X:A X:B + - 7FFFFF 800000 — — One 24 bit Y Y:A Y:B + - — — 7FFFFF 800000 One 24 bit X and Y X:A Y:A X:A Y:B X:B Y:A X:B Y:B L:AB L:BA + + + - 7FFFFF 800000 7FFFFF 800000 7FFFFF 800000 7FFFFF 800000 7FFFFF 800000 7FFFFF 800000 Two 24 bit L (X:Y) L:A L:B + - 7FFFFF 800000 FFFFFF 000000 One 48 bit 7 shows
DATA REPRESENTATION AND ROUNDING or 1 - 2-47. These limitations apply to all data stored in memory and to data stored in the Data ALU input buffer registers. The extension registers associated with the accumulators allow word growth so that the most positive number that can be used is approximately 256 and the most negative number is approximately -256. When the accumulator extension registers are in use, the data contained in the accumulators cannot be stored exactly in memory or other registers.
DATA REPRESENTATION AND ROUNDING A1 or B1(see Figure 3-8). N BITS TWOS COMPLEMENT INTEGER S TWOS COMPLEMENT FRACTIONAL S • • –2(N–1) TO –1 TO [+2(N–1) –1] [+1–2–(N–1)] N BITS FRACTIONAL = INTEGER EXCEPT FOR X AND ÷ Figure 3-8 Integer/Fractional Number Comparison A comparison between integer and fractional number representation is shown in Figure 3-8. The number representation for integers is between ± 2(N-1); whereas, the fractional representation is limited to numbers between ±1.
DATA REPRESENTATION AND ROUNDING SIGNED MULTIPLICATION N x N - 2N – 1 BITS INTEGER S FRACTIONAL S S S SIGNED MULTIPLIER S S MSP .. . LSP 2N — 1 PRODUCT SIGN EXTENSION SIGNED MULTIPLIER • S• MSP .. . LSP 0 2N — 1 PRODUCT 2N BITS ZERO FILL 2N BITS Figure 3-9 Integer/Fractional Multiplication Comparison and rounds down any value below one-half. The question arises as to which way onehalf should be rounded.
DATA REPRESENTATION AND ROUNDING CASE I: IF A0 < $800000 (1/2), THEN ROUND DOWN (ADD NOTHING) BEFORE ROUNDING AFTER ROUNDING 0 A2 A1 A0 XX . . XX XXX . . . XXX0100 011XXX . . . . XXX 55 48 47 24 23 0 A2 A1 A0* XX . . XX XXX . . . XXX0100 000 . . . . . . . . 000 55 48 47 24 23 0 CASE II: IF A0 > $800000 (1/2), THEN ROUND UP (ADD 1 TO A1) AFTER ROUNDING BEFORE ROUNDING 1 A2 A1 A0 XX . . XX XXX . . . XXX0100 1110XX . . . . XXX 55 48 47 24 23 0 A2 A1 A0* XX . . XX XXX . . . XXX0101 000 . . . . . . . .
DOUBLE PRECISION MULTIPLY MODE 3.4 DOUBLE PRECISION MULTIPLY MODE The Data ALU double precision multiply operation multiplies two 48-bit operands with a 96-bit result. The processor enters the dedicated Double Precision Multiply Mode when the user sets bit 14 (DM) of the Status Register (bit 6 of the MR register). The mode is disabled by clearing the DM bit. For information on the DM bit, see Section 5.4.2.13 Double Precision Multiply Mode (Bit 14).
DOUBLE PRECISION MULTIPLY MODE one instruction cycle. The ANDI instruction clears the DM mode bit, but, due to the instruction execution pipeline, the Data ALU leaves the mode after one instruction cycle. The double precision multiply algorithm uses the Y0 register at all stages. If the use of the Data ALU is required in an interrupt service routine, Y0 should be saved together with other Data ALU registers to be used, and should be restored before leaving the interrupt routine.
DOUBLE PRECISION MULTIPLY MODE cision values and accumulated using regular MAC instructions. Note that the maximum number of single times double MAC operations in this algorithm are limited to 255 since overflow may occur (the A2 register is just eight bits long). If a longer sequence is required, it should be split into sub-sequences each with no more than 255 MAC operations.
DATA ALU PROGRAMMING MODEL 3.5 DATA ALU PROGRAMMING MODEL The Data ALU features 24-bit input/output data registers that can be concatenated to accommodate 48-bit data and two 56-bit accumulators, which are segmented into three 24bit pieces that can be transferred over the buses. Figure 3-14 illustrates how the registers in the programming model are grouped.
DATA ALU SUMMARY 3 - 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA
SECTION 4 ADDRESS GENERATION UNIT MOTOROLA ADDRESS GENERATION UNIT 4-1
SECTION CONTENTS SECTION 4.1 ADDRESS GENERATION UNIT AND ADDRESSING MODES ....3 SECTION 4.2 AGU ARCHITECTURE ..................................................................3 4.2.1 Address Register Files (Rn) ................................................................3 4.2.2 Offset Register Files (Nn) ....................................................................4 4.2.3 Modifier Register Files (Mn) ................................................................5 4.2.4 Address ALU ............
ADDRESS GENERATION UNIT AND ADDRESSING MODES 4.1 ADDRESS GENERATION UNIT AND ADDRESSING MODES This section contains three major subsections. The first subsection describes the hardware architecture of the address generation unit (AGU), the second subsection describes the programming model, and the third subsection describes the addressing modes, explaining how the Rn, Nn, and Mn registers work together to form a memory address. 4.
AGU ARCHITECTURE EXPANSION AREA Y MEMORY RAM/ROM EXPANSION EXTERNAL ADDRESS BUS SWITCH BUS CONTROL PORT A YAB XAB PAB ADDRESS GENERATION UNIT ADDRESS PERIPHERAL PINS 24-Bit 56K Module X MEMORY RAM/ROM EXPANSION CONTROL PROGRAM RAM/ROM EXPANSION PERIPHERAL MODULES YDB XDB PDB EXTERNAL DATA BUS SWITCH DATA INTERNAL DATA BUS SWITCH GDB PLL CLOCK GENERATOR PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLER PROGRAM ADDRESS GENERATOR DATA ALU 24X24+56→56-BIT MAC TWO 56-BIT ACCUMULATORS
AGU ARCHITECTURE LOW ADDRESS ALU HIGH ADDRESS ALU XAB YAB PAB TRIPLE MULTIPLEXER N0 M0 N1 M1 N2 M2 N3 M3 ADDRESS ALU R0 R4 R1 R5 R2 R6 R3 R7 ADDRESS ALU M4 N4 M5 N5 M6 N6 M7 N7 GLOBAL DATA BUS 16 bits 24 bits Figure 4-2 AGU Block Diagram GDB. When read by the GDB, the contents of a register are placed in the two least significant bytes, and the most significant byte on the GDB is zero extended.
PROGRAMMING MODEL selected address register. A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value, M or minus M, where M-1 is stored in the respective modifier register. A third full adder (called a reverse-carry adder) can add 1) plus one, 2) minus one, 3) the offset N (stored in the respective offset register), or 4) minus N to the selected address register with the carry propagating in the reverse direction — i.e.
PROGRAMMING MODEL 23 16 15 * * * * * * * * 0 23 R7 16 15 0 N7 * N6 * N5 * N4 * N3 * N2 * N1 * N0 *OFFSET REGISTERS R6 R5 R4 R3 R2 R1 R0 ADDRESS REGISTERS 23 16 15 0 M7 * M6 * M5 * M4 * M3 * M2 * M1 * M0 *MODIFIER REGISTERS UPPER FILE LOWER FILE * Written as don’t care; read as zero Figure 4-3 AGU Programming Model 4.3.1 Address Register Files (R0 - R3 and R4 - R7) The eight 16-bit address registers, R0 - R7, can contain addresses or general-purpose data.
ADDRESSING Table 4-1 Address Register Indirect Summary Address Register Indirect Uses Mn Modifier Operand Reference S C D A P X Y L XY Assembler Syntax No Update No X X X X X (Rn) Postincrement by 1 Yes X X X X X (Rn)+ Postdecrement by 1 Yes X X X X X (Rn)– Postincrement by Offset Nn Yes X X X X X (Rn)+Nn NOTE: S C D A P X Y L XY = System Stack Reference = Program Control Unit Register Reference = Data ALU Register Reference = Address ALU Register Reference = P
ADDRESSING the AGU and are described in the following paragraphs. 4.4.1 Address Register Indirect Modes When an address register is used to point to a memory location, the addressing mode is called “address register indirect” (see Table 4-1). The term indirect is used because the register contents are not the operand itself, but rather the address of the operand. These addressing modes specify that an operand is in memory and specify the effective address of that operand.
ADDRESSING EXAMPLE: MOVE A1,X: (R0) BEFORE EXECUTION A2 A1 A0 55 48 47 0 7 AFTER EXECUTION 1 2 0 23 A2 24 23 3 4 5 6 0 7 8 9 0 23 A B C D 0 A1 A0 55 48 47 0 7 1 2 0 23 24 23 3 4 5 6 0 7 8 0 23 9 A X MEMORY 0 X X X X X 15 R0 $1000 0 $ 2 3 4 5 6 7 0 15 15 R0 0 XXXX 15 M0 X 23 $1000 N0 D 0 X MEMORY 23 $1000 B C 15 N0 0 $FFFF 0 $1000 0 XXXX 15 M0 0 $FFFF Assembler Syntax: (Rn) Memory Spaces: P:, X:, Y:, XY:, L: Additional Instruction Execution Time (Clock
ADDRESSING EXAMPLE: MOVE B0,Y: (R1)+ BEFORE EXECUTION B2 B1 B0 55 48 47 A 7 AFTER EXECUTION F 6 0 23 B2 24 23 5 4 3 2 1 F 0 23 E D C B B1 0 55 48 47 A 0 A 7 F 6 0 23 B0 24 23 5 4 3 2 Y MEMORY 23 0 1 F E 0 23 D C B A 0 Y MEMORY 0 23 0 $2501 X X X X X X $2501 X X X X X X X $2500 X X X X X X $2500 $ F E D C B A 15 R1 0 $2500 15 N1 0 XXXX 15 M1 15 R1 15 N1 0 $FFFF 0 $2501 0 XXXX 15 M1 0 $FFFF Assembler Syntax: (Rn)+ Memory Spaces: P:, X:, Y:, XY:,
ADDRESSING EXAMPLE: MOVE Y0,Y: (R3)- AFTER EXECUTION BEFORE EXECUTION Y1 Y0 47 1 2 23 Y1 24 23 3 1 2 3 4 0 23 5 6 4 5 0 47 6 0 1 2 23 Y0 24 23 3 1 2 Y MEMORY 23 X X X X X X $4735 $4734 X X X X X X $4734 15 4 5 X X 6 X 5 0 6 0 5 X 0 15 0 0 XXXX 15 M3 6 X $4734 N3 $FFFF 4 X 15 R3 XXXX 15 M3 4 0 0 $4735 N3 6 23 $4735 15 5 Y MEMORY 0 R3 0 3 4 0 23 0 $FFFF Assembler Syntax: (Rn)– Memory Spaces: P:, X:, Y:, XY:, L: Additional Instruction Execu
ADDRESSING EXAMPLE: MOVE X1,X: (R2)+N2 AFTER EXECUTION BEFORE EXECUTION X1 X0 47 A 5 23 X1 24 23 B 4 C 6 0 0 23 0 0 0 0 0 47 1 0 A 5 23 X0 24 23 B 4 C 0 0 0 0 1 0 X MEMORY X MEMORY 23 0 6 0 0 23 23 0 0 $3204 X X X X X X $3204 X X $3200 X X X X X X $3200 $ A 5 B 4 C 6 15 R2 0 $3200 15 0 15 M2 X 0 15 0 0 $0004 15 M2 X $3204 N2 $FFFF X 15 R2 $0004 N2 X 0 $FFFF Assembler Syntax: (Rn)+Nn Memory Spaces: P:, X:, Y:, XY:, L: Additional Instructi
ADDRESSING EXAMPLE: MOVE X:(R4)–N4,A0 AFTER EXECUTION BEFORE EXECUTION A2 A1 A0 55 48 47 0 7 F 7 4 0 23 A2 24 23 1 0 5 0 A 3 0 23 F A 6 B 0 0 A1 A0 55 48 47 0 7 F 7 0 23 24 23 4 1 0 5 X MEMORY $7703 0 $ 5 0 5 0 5 0 X X X X X 15 R4 X $7703 5 0 0 $ 5 0 5 0 5 0 X X X X 0 0 $0003 N4 15 0 M4 X $7703 15 0 $FFFF X 15 R4 $0003 15 M4 0 0 0 15 5 23 $7706 $7706 N4 0 X MEMORY 23 $7706 0 A 5 0 23 0 $FFFF Assembler Syntax: (Rn)–Nn Memory Spaces: P:, X
ADDRESSING EXAMPLE: MOVE Y1,X: (R6+N6) AFTER EXECUTION BEFORE EXECUTION Y1 Y0 47 Y1 24 23 6 2 1 23 0 0 9 B A 0 23 4 C 2 0 47 2 0 6 2 23 Y0 24 23 1 0 0 A 4 C 2 2 0 X MEMORY X MEMORY 23 0 9 B 0 23 23 0 0 $6004 X X X X X X $6004 $ 6 2 1 0 0 9 $6000 X X X X X X $6000 X X 15 R6 0 + $0004 N6 15 M6 R6 0 X X 15 $6000 15 X 0 $6000 15 0 0 $0004 N6 $FFFF 15 M6 X 0 $FFFF Assembler Syntax: (Rn+Nn) Memory Spaces: P:, X:, Y:, L: Additional Instruction E
ADDRESSING EXAMPLE: MOVE X: –(R5),B1 AFTER EXECUTION BEFORE EXECUTION B2 B1 B0 55 48 47 3 7 B B 0 23 B2 24 23 6 2 D 0 4 A 0 23 0 5 5 4 C 0 0 B1 B0 55 48 47 3 7 B 1 0 23 24 23 2 3 4 5 X MEMORY 23 $3007 $3006 0 6 A 5 0 23 5 4 C 0 0 X MEMORY 0 23 0 $ A B C D E F $3007 $ A B C D E F $ 1 2 3 4 5 6 $3006 $ 1 2 3 4 5 6 15 R5 15 0 XXXX N5 15 0 $FFFF 0 $3006 15 0 15 M5 R5 XXXX N5 15 0 $3007 M5 0 $FFFF Assembler Syntax: –Rn Memory Spaces: P:, X:, Y:, L: Additi
ADDRESSING difference between these two data representations. Addresses are normally considered unsigned, and data is normally considered signed. 4.4.2.2 Modulo Modifier When the value in the modifier register falls into one of two ranges (Mn=$0001 to $7FFF or Mn= $8001 to $BFFF with the reserved gaps noted in the table), address modification is performed using modulo arithmetic (see Table 4-2).
ADDRESSING Table 4-2 Address Modifier Summary MMMM 0000 Reverse Carry (Bit Reverse) 0001 Modulo 2 0002 Modulo 3 : : 7FFE Modulo 32767 7FFF Modulo 32768 8000 Reserved 8001 Multiple Wrap-Around Modulo 2 8002 Reserved 8003 Multiple Wrap-Around Modulo 4 : 8007 : 800F : 801F : 803F : 807F : 80FF : 81FF : 83FF Reserved Multiple Wrap-Around Modulo 8 Reserved Multiple Wrap-Around Modulo 24 Reserved Multiple Wrap-Around Modulo 25 Reserved Multiple Wrap-Around Modulo 26 Reserved Multiple Wrap-Ar
ADDRESSING UPPER BOUNDARY ADDRESS POINTER CIRCULAR BUFFER M = MODULUS LOWER BOUNDARY Figure 4-11 Circular Buffer (base address), it will wrap around through the base address plus M–1 (upper boundary). If an offset (Nn) is used in the address calculations, the 16-bit absolute value, |Nn|, must be less than or equal to M for proper modulo addressing in this range.
ADDRESSING 2k M (Rn) ± Nn MOD M WHERE Nn = 2k (i.e., P = 1) 2k M Figure 4-12 Linear Addressing with a Modulo Modifier as 0, 32, 64, 96, 128, 160, etc. For this example, L is arbitrarily chosen to be 2, making the lower boundary 64. The upper boundary of the buffer is then 84 (the lower boundary plus 20 (M–1)). The Mn register is loaded with the value 20 (M–1). The offset register is arbitrarily chosen to be 15 (Nn≤M).
ADDRESSING EXAMPLE: MOVE X0,X:(R2)+N LET: M2 00.....0010100 MODULUS=21 N2 00.....0001111 OFFSET=15 R2 00.....1001011 POINTER=75 (90) + N2 (84) (75) XD BUS R2 (69) 21 X0 0..010 00000 (64) k=5 Figure 4-13 Modulo Modifier Example The MOVE instruction in Figure 4-13 takes the contents of the X0 register and moves it to a location in the X memory pointed to by (R2), and then (R2) is updated modulo 21.
ADDRESSING For example, to create a circular buffer of 32 stages, M is chosen as 32 and the lower address boundary must have its 5 least significant bits equal to zero (2k = 32, thus k = 5). The Mn register is loaded with the value $801F. The lower boundary may be chosen as 0, 32, 64, 96, 128, 160, etc. The upper boundary of the buffer is then the lower boundary plus 31.
ADDRESSING 3. Set Rn between the lower boundary and upper boundary in the buffer memory. The lower boundary is L x (2k), where L is an arbitrary whole number. This boundary gives a 16-bit binary number “xx . . . xx00 . . . 00”, where xx . . . xx=L and 00 . . . 00 equals k zeros. The upper boundary is L x (2k)+ ((2k)–1). This boundary gives a 16-bit binary number “xx . . . xx11 . . . 11”, where xx . . . xx=L and 11 . . . 11 equals k ones. 4. Use the (Rn)+ Nn addressing mode.
ADDRESSING The term bit reverse with respect to reverse-carry arithmetic is descriptive. The lower boundary that must be used for the bit-reverse address scheme to work is L x (2k). In the previous example shown in Table 4-3, L=3 and k=10. The first address used is the lower boundary (3072); the calculation of the next address is shown in Figure 4-14. The k LSBs of the current contents of Rn (3,072) are swapped: EACH UPDATE, (Rn)+Nn, IS EQUIVALENT TO: L 1.
ADDRESSING 4.4.2.4 Address-Modifier-Type Encoding Summary There are three address modifier types: • Linear Addressing • Reverse-Carry Addressing • Modulo Addressing Bit-reverse addressing is useful for 2k-point FFT addressing. Modulo addressing is useful for creating circular buffers for FIFOs (queues), delay lines, and sample buffers up to 32,768 words long. The linear addressing is useful for general-purpose addressing.
ADDRESSING LINEAR ADDRESS MODIFIER 90 M0 = 255 = 11111111 FOR LINEAR ADDRESSING WITH R0 85 ORIGINAL REGISTERS: N0 = 5, R0 = 75 = 0100 1011 POSTINCREMENT BY OFFSET N0: R0 = 80 = 0101 0000 POSTINCREMENT BY OFFSET N0: R0 = 85 = 0101 0101 POSTINCREMENT BY OFFSET N0: R0 = 90 = 0101 1010 80 R0 75 UPPER BOUNDARY 83 MODULO ADDRESS MODIFIER 80 M0 = 19 = 0001 0011 FOR MODULO 20 ADDRESSING WITH R0 ORIGINAL REGISTERS: N0 = 5, R0 = 75 = 0100 1011 POSTINCREMENT BY OFFSET N0: R0 = 80 = 0101 0000 POSTI
SECTION 5 PROGRAM CONTROL UNIT MOTOROLA PROGRAM CONTROL UNIT 5-1
SECTION CONTENTS SECTION 5.1 PROGRAM CONTROL UNIT .................................................... 3 SECTION 5.2 OVERVIEW ................................................................................ 3 SECTION 5.3 PROGRAM CONTROL UNIT (PCU) ARCHITECTURE ............ 5 5.3.1 Program Decode Controller ................................................................ 5 5.3.2 Program Address Generator (PAG) ................................................... 5 5.3.3 Program Interrupt Controller .........
PROGRAM CONTROL UNIT 5.1 PROGRAM CONTROL UNIT This section describes the hardware of the program control unit (PCU) and concludes with a description of the programming model. The instruction pipeline description is also included since understanding the pipeline is particularly important in understanding the DSP56K family of processors. 5.2 OVERVIEW The program control unit is one of the three execution units in the central processing module (see Figure 5-2).
OVERVIEW EXPANSION AREA Y MEMORY RAM/ROM EXPANSION EXTERNAL ADDRESS BUS SWITCH BUS CONTROL PORT A YAB XAB PAB ADDRESS GENERATION UNIT ADDRESS PERIPHERAL PINS 24-Bit 56K Mod- X MEMORY RAM/ROM EXPANSION CONTROL PROGRAM RAM/ROM EXPANSION PERIPHERAL MODULES YDB XDB PDB EXTERNAL DATA BUS SWITCH DATA INTERNAL DATA BUS SWITCH GDB PLL CLOCK GENERATOR PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLER PROGRAM ADDRESS GENERATOR DATA ALU 24X24+56→56-BIT MAC TWO 56-BIT ACCUMULATORS OnCE™ Pr
PROGRAM CONTROL UNIT (PCU) ARCHITECTURE The program control unit implements a three-stage (prefetch, decode, execute) pipeline and controls the five processing states of the DSP: normal, exception, reset, wait, and stop. 5.3 PROGRAM CONTROL UNIT (PCU) ARCHITECTURE The PCU consists of three hardware blocks: the program decode controller (PDC), the program address generator (PAG), and the program interrupt controller (PIC). 5.3.
PROGRAM CONTROL UNIT (PCU) ARCHITECTURE interruptible since they are fetched only once. A single-instruction DO loop can be used in place of a REP instruction if interrupts must be allowed. 5.3.3 Program Interrupt Controller The PIC receives all interrupt requests, arbitrates among them, and generates the interrupt vector address. Interrupts have a flexible priority structure with levels that can range from zero to three. Levels 0 (lowest level), 1, and 2 are maskable.
PROGRAM CONTROL UNIT (PCU) ARCHITECTURE EXAMPLE PROGRAM SEGMENT Instruction 1 Instruction 2 Instruction 3 MACR CLR MAC X0,Y1,A A X0,Y1,A X:(R0)+,X0 X0,X:(R0)+ X:(R0)+,X0 Y:(R4)+,Y1 A,Y:(R4)Y:(R4)+,Y1 SEQUENCE OF OPERATIONS PARALLEL PROCESSING OF INSTRUCTIONS SERIAL EXECUTION OF INSTRUCTIONS Instruction Cycle 3 Instruction Cycle Instruction Cycle 5 Instruction Cycle 1 Instruction Cycle 2 INSTRUCTION FETCH LOGIC 1 INSTRUCTION FETCH LOGIC 2 INSTRUCTION FETCH LOGIC 3 INSTRUCTION FETCH LOGIC 4 IN
PROGRAMMING MODEL PROGRAM CONTROL UNIT 23 16 15 0 23 16 15 * * LOOP ADDRESS REGISTER (LA) 23 16 15 LOOP COUNTER (LC) 0 23 16 15 * * PROGRAM COUNTER (PC) 31 0 SSH 87 MR 0 23 SSL * * STATUS REGISTER (SR) 16 15 8 7 CCR 6 SD 5 * 4 3 2 1 0 MC YD DE MB MA OPERATING MODE REGISTER (OMR) 0 23 1 6 5 * * 0 STACK POINTER (SP) READ AS ZERO, SHOULD BE WRITTEN WITH ZERO FOR FUTURE COMPATIBILITY 15 SYSTEM STACK Figure 5-4 Program Control Unit Programming Model ation, move the content
PROGRAMMING MODEL MR 15 14 13 LF DM T 12 * CCR 11 10 S1 S0 9 8 7 6 5 4 3 2 1 0 I1 I0 S L E U N Z V C CARRY OVERFLOW ZERO NEGATIVE UNNORMALIZED EXTENSION LIMIT SCALING INTERRUPT MASK SCALING MODE RESERVED TRACE MODE DOUBLE PRECISION MULTIPLY MODE LOOP FLAG All bits are cleared after hardware reset except bits 8 and 9 which are set to ones.
PROGRAMMING MODEL The CCR is a special purpose control register that defines the current user state of the processor. The CCR bits are affected by data arithmetic logic unit (ALU) operations, parallel move operations, and by instructions that directly reference the CCR (ORI and ANDI). The CCR bits are not affected by parallel move operations unless data limiting occurs when reading the A or B accumulators. During processor reset, all CCR bits are cleared. 5.4.2.
PROGRAMMING MODEL 5.4.2.6 Extension (Bit 5) The extension (E) bit is cleared if all the bits of the integer portion of the 56-bit result are all ones or all zeros; otherwise, this bit is set. The integer portion, defined by the scaling mode and the E bit, is computed as follows: S1 S0 Scaling Mode Integer Portion 0 0 No Scaling Bits 55,54........48,47 0 1 Scale Down Bits 55,54........49,48 1 0 Scale Up Bits 55,54........
PROGRAMMING MODEL If S1=0 and S0=0 (no scaling) then S = (A46 XOR A45) OR (B46 XOR B45) If S1=0 and S0=1 (scale down) then S = (A47 XOR A46) OR (B47 XOR B46) If S1=1 and S0=0 (scale up) then S = (A45 XOR A44) OR (B45 XOR B44) If S1=1 and S0=1 (reserved) then the S flag is undefined. where Ai and Bi means bit i in accumulator A or B. 5.4.2.
PROGRAMMING MODEL tor (MAC). The scaling modes are shown in the following table: S1 S0 Rounding Bit 0 0 23 No Scaling 0 1 24 Scale Down (1-Bit Arithmetic Right Shift) 1 0 22 Scale Up (1-Bit Arithmetic Left Shift) 1 1 — Reserved for Future Expansion Scaling Mode The scaling mode affects data read from the A or B accumulator registers out to the XDB and YDB. Different scaling modes can occur with the same program code to allow dynamic scaling.
PROGRAMMING MODEL 23 8 * 7 6 5 4 3 * SD * MC YD 2 1 0 DE MB MA OPERATING MODE A, B DATA ROM ENABLE INTERNAL Y MEMORY DISABLE OPERATING MODE C RESERVED STOP DELAY RESERVED RESERVED Figure 5-6 OMR Format tions. The DSP56K software simulator accurately shows how the MPY, MAC, and other Data ALU instructions operate while the processor is in the double precision multiply mode. 5.4.2.14 Loop Flag (Bit 15) The loop flag (LF) bit is set when a program loop is in progress.
PROGRAMMING MODEL SSL, each 16 bits wide. The SSH stores the PC contents, and the SSL stores the SR contents for subroutine calls, long interrupts, and program looping. The SS will also store the LA and LC registers. The SS is in stack memory space; its address is always inherent and implied by the current instruction. The contents of the PC and SR are pushed on the top location of the SS when a subroutine call or long interrupt occurs.
PROGRAMMING MODEL these bits are cleared (SP=0), indicating that the SS is empty. Data is pushed onto the SS by incrementing the SP, then writing data to the location to which the SP points. An item is pulled off the stack by copying it from that location and then by decrementing the SP. 5.4.5.2 Stack Error Flag (Bit 4) The stack error flag indicates that a stack error has occurred, and the transition of the stack error flag from zero to one causes a priority level-3 stack error exception.
PROGRAMMING MODEL data (MOVEP) when SSL is specified as a source or destination). 5.4.5.3 Underflow Flag (Bit 5) The underflow flag is set when a stack underflow occurs. The underflow flag is a “sticky bit” when the stack error flag is set. That is, when the stack error flag is set, the underflow flag will not change state. The combination of “underflow=1” and “stack error=0” is an illegal combination and will not occur unless it is forced by the user.
PROGRAMMING MODEL DATA ARITHMETIC LOGIC UNIT INPUT REGISTERS X 47 0 Y 47 23 0 Y0 Y1 X0 X1 0 23 0 23 0 23 0 ACCUMULATOR REGISTERS A 55 # 23 8 7 0 23 0 23 0 B 55 # 0 B0 B1 B2 23 0 A0 A1 A2 8 7 0 23 0 23 0 ADDRESS GENERATION UNIT 23 16 15 * * * * * * * * 0 23 16 15 R7 0 R6 R5 R4 R3 R2 R1 R0 POINTER REGISTERS 23 16 15 N7 * * * * * * * * 0 M7 * * * * * * * * N6 N5 N4 N3 N2 N1 N0 OFFSET REGISTERS UPPER FILE M6 M5 M4 M3 M2 M1 LOWER FILE M0 MODIFIER REGISTERS PROG
SECTION 6 INSTRUCTION SET INTRODUCTION Fetch F1 Decode Execute Instruction Cycle: 1 MOTOROLA F2 D1 F3 D2 E1 F3e D3 E2 F4 F5 F6 D3e D4 D5 E3 E3e E4 . . . . . . . . . 2 3 4 5 . . .
SECTION CONTENTS SECTION 6.1 INSTRUCTION SET INTRODUCTION ...................................... 3 SECTION 6.2 SYNTAX ..................................................................................... 3 SECTION 6.3 INSTRUCTION FORMATS ........................................................ 3 6.3.1 Operand Sizes .................................................................................... 5 6.3.2 Data Organization in Registers ........................................................... 6 6.3.2.
INSTRUCTION SET INTRODUCTION 6.1 INSTRUCTION SET INTRODUCTION The programming model shown in Figure 6-1 suggests that the DSP56K central processing module architecture can be viewed as three functional units which operate in parallel: data arithmetic logic unit (data ALU), address generation unit (AGU), and program control unit (PCU). The instruction set keeps each of these units busy throughout each instruction cycle, achieving maximal speed and maintaining minimal program size.
INSTRUCTION FORMATS DATA ARITHMETIC LOGIC UNIT INPUT REGISTERS X 47 0 Y 47 23 0 Y0 Y1 X0 X1 0 23 0 23 0 23 0 ACCUMULATOR REGISTERS A 55 # 23 8 7 0 23 0 23 0 B 55 # 0 B0 B1 B2 23 0 A0 A1 A2 8 7 0 23 0 23 0 ADDRESS GENERATION UNIT 23 16 15 * * * * * * * * 0 23 16 15 R7 0 R6 R5 R4 R3 R2 R1 R0 POINTER REGISTERS 23 16 15 N7 * * * * * * * * 0 M7 * * * * * * * * N6 N5 N4 N3 N2 N1 N0 OFFSET REGISTERS UPPER FILE M6 M5 M4 M3 M2 M1 LOWER FILE M0 MODIFIER REGISTERS PR
INSTRUCTION FORMATS shown in Figure 6-2. Most instructions specify data movement on the XDB, YDB, and data ALU operations in the same operation word. The DSP56K performs each of these operations in parallel. 23 87 0 OPCODE DATA BUS MOVEMENT XXXX XX X X OPTIONAL EFFECTIVE ADDRESS EXTENSION Figure 6-2 General Format of an Instruction Operation Word The data bus movement field provides the operand reference type.
INSTRUCTION FORMATS 7 0 BYTE 15 0 SHORT WORD 23 0 WORD 47 0 LONG WORD 55 0 ACCUMULATOR Figure 6-3 Operand Sizes 6.3.2 Data Organization in Registers The ten data ALU registers support 8- or 24-bit data operands. Instructions also support 48- or 56-bit data operands by concatenating groups of specific data ALU registers. The eight address registers in the AGU support 16-bit address or data operands.
INSTRUCTION FORMATS 23 87 0 BUS REGISTER A2, B2 USED AS A DESTINATION LSB OF WORD NOT USED 23 87 A2 NOT USED REGISTER A2, B2 USED AS A SOURCE 23 87 SIGN EXTENSION OF A2 0 REGISTER A2, B2 0 CONTENTS OF A2 BUS Figure 6-4 Reading and Writing the ALU Extension Registers 23 0 BUS ADDRESS ALU REGISTERS AS A DESTINATION NOT USED LSB OF WORD 15 0 ADDRESS ALU REGISTERS ADDRESS ALU REGISTERS AS A SOURCE 23 16 15 ZERO FILL 0 BUS Figure 6-5 Reading and Writing the Address ALU Registers 6.3.
INSTRUCTION FORMATS address modifier registers, M0–M7. 23 87 0 BUS MR, CCR, OMR, AND SP AS A DESTINATION NOT USED LSB MR, CCR, OMR, AND SP A2 MR, CCR, OMR, AND SP AS A SOURCE 23 87 0 ZERO FILL BUS (a) 16 Bit 23 0 BUS LC, LA, SR, SSH, AND SSL AS A DESTINATION LSB OF WORD NOT USED 15 0 LC, LA, SR, SSH, AND SSL AS A SOURCE LC, LA, SR, SSH, AND SSL 23 16 15 ZERO FILL 0 BUS (b) 8 Bit Figure 6-6 Reading and Writing Control Registers 6.3.2.
INSTRUCTION FORMATS the user condition code register (CCR) occupying the low-order eight bits. The SR may be accessed as a word operand. The MR and CCR may be accessed individually as word operands (see Figure 6-6(b)). The LC, LA, system stack high (SSH), and system stack low (SSL) registers are 16 bits wide and may be accessed as word operands (see Figure 6-6(a)). When used as a source operand, these registers occupy the low-order portion of the 24-bit word; the high-order portion is zero.
INSTRUCTION FORMATS BA A10 B10 Address ALU Rn Nn Mn Accumulators B and A (B1:A1, 48 Bits)* Accumulator A (A1:A0, 48 Bits) Accumulator B (B1:B0, 48 Bits) Address Registers R0–R7 (16 Bits) Address Offset Registers N0–N7 (16 Bits) Address Modifier Registers M0–M7 (16 Bits) Program Control Unit PC Program Counter (16 Bits) MR Mode Register (8 Bits) CCR Condition Code Register (8 Bits) SR Status Register (MR:CCR, 16 Bits) OMR Operating Mode Register (8 Bits) LA Hardware Loop Address Register (16 Bits) LC Hard
INSTRUCTION FORMATS D[n] r I1,I0 LF Bit n of D Affected Rounding Constant Interrupt Priority Level in SR Loop Flag in SR 6.3.4 Operand References The DSP separates operand references into four classes: program, stack, register, and memory references. The type of operand reference(s) required for an instruction is specified by both the opcode field and the data bus movement field of the instruction. However, not all operand reference types can be used with all instructions.
INSTRUCTION FORMATS 6.3.4.4.1 X Memory References The operand, which is in X memory space, is a word reference. Data can be transferred from memory to a register or from a register to memory.
INSTRUCTION FORMATS 6.3.4.4.2 Y Memory References The operand, a word reference, is in Y memory space. Data can be transferred from memory to a register or from a register to memory. 6.3.4.4.3 L Memory References Long (L) memory space references both X and Y memory spaces with one operand address. The data operand is a long-word reference developed by concatenating the X and Y memory spaces (X:Y). The high-order word of the operand is in the X memory; the low-order word of the operand is in the Y memory.
INSTRUCTION FORMATS Some address register indirect modes require an offset and a modifier register for use in address calculations. These registers are implied by the address register specified in an effective address in the instruction word. Each offset register (Nn) and each modifier register (Mn) is assigned to an address register (Rn) having the same register number (n). Thus, the assigned register triplets are R0;N0;M0, R1;N1;M1, R2;N2;M2, R3;N3;M3, R4;N4;M4, R5;N5;M5, R6;N6;M6, and R7;N7;M7.
INSTRUCTION FORMATS 6.3.5.3 Special Addressing Modes The special addressing modes do not use specific registers to specify an effective address. These modes specify the operand or the operand address in a field of the instruction, or they implicitly reference an operand. Figure examples are given for each of the special addressing modes discussed in the following paragraphs. 6.3.5.3.
INSTRUCTION FORMATS EXAMPLE A: IMMEDIATE INTO 24-BIT REGISTER (MOVE #$123456,A0) BEFORE EXECUTION AFTER EXECUTION A2 A1 A0 55 48 47 24 23 0 X X X X X X X X X X X X X X 7 0 23 0 23 0 A2 A1 A0 55 48 47 24 23 0 X X X X X X X X 1 2 3 4 5 6 7 0 23 0 23 0 EXAMPLE B:POSITIVE IMMEDIATE INTO 56-BIT REGISTER (MOVE #$123456,A) AFTER EXECUTION BEFORE EXECUTION A2 A1 A0 55 48 47 24 23 0 X X X X X X X X X X X X X X 7 0 23 0 23 0 A2 55 0 7 A1 A0 48 47 24 23 0 0 1 2 3 4 5 6 0 0 0 0 0 0 0 23 0 23 0 EXAMPLE C: NEGA
INSTRUCTION FORMATS EXAMPLE: MOVE Y:$5432,B0 BEFORE EXECUTION AFTER EXECUTION B2 B1 B0 55 48 47 24 23 0 X X X X X X X X X X X X X X 7 0 23 0 23 0 B2 B1 B0 55 48 47 24 23 0 X X X X X X X X A B C D E F 7 0 23 0 23 0 23 Y MEMORY 0 $5432 A B C D E F 23 Y MEMORY 0 $5432 A B C D E F Assembler Syntax: XXXX or aa Memory Spaces: P: Additional Instruction Execution Time (Clocks): 2 Additional Effective Address Words: 1 Figure 6-8 Special Addressing – Absolute Addressing 6.3.5.3.
INSTRUCTION FORMATS EXAMPLE A: IMMEDIATE SHORT INTO A0, A1, A2, B0, B1, B2, Rn, Nn (MOVE #$FF,A1) BEFORE EXECUTION AFTER EXECUTION A2 A1 A0 55 48 47 24 23 0 X X X X X X X X X X X X X X 7 0 23 0 23 0 A2 A1 A0 55 48 47 24 23 0 X X 0 0 0 0 F F X X X X X X 7 0 23 0 23 0 EXAMPLE B:POSITIVE IMMEDIATE SHORT INTO X0, X1, Y0, Y1, A, B (MOVE #$1F, Y1) BEFORE EXECUTION AFTER EXECUTION Y1 Y1 47 X X X 23 Y0 24 23 0 X X X X X X X X X 0 23 0 47 1 F 0 23 Y0 24 23 0 0 0 0 X X X X X X 0 23 0 EXAMPLE C: POSITIVE IM
INSTRUCTION GROUPS EXAMPLE: JMP $123 BEFORE EXECUTION P MEMORY AFTER EXECUTION P MEMORY JMP $0123 JMP $0123 PC $0FFF $0FFF SHORT JUMP RANGE 4,096 WORDS $0123 $0000 PC $0123 NEXT INSTRUCTION $0000 Assembler Syntax: XXX Memory Spaces: P: Additional Instruction Execution Time (Clocks): 0 Additional Effective Address Words: 0 Figure 6-10 Special Addressing – Short Jump Address 6.
INSTRUCTION GROUPS EXAMPLE A: MOVE P: $3200,X0 AFTER EXECUTION BEFORE EXECUTION X1 47 0 0 0 23 X0 X1 X0 47 24 23 0 0 0 0 0 0 1 A 5 B 4 C 6 23 0 23 0 24 23 0 0 0 1 X X X X X X 0 23 0 P MEMORY 23 $3204 P MEMORY 0 23 $3204 X X X X X X $3200 $ A 5 B 4 C 6 0 X X X X X X $3200 $ A 5 B 4 C 6 EXAMPLE B: MOVE A1, X: $3 A2 55 X 7 BEFORE EXECUTION A1 A0 A2 48 47 24 23 0 X 3 4 F 5 E 6 X X X X X X 0 23 0 23 0 55 X 7 AFTER EXECUTION A1 A0 48 47 24 23 0 X 3 4 F 5 E 6 X X X X X X 0 23 0 23 0 X MEMORY
INSTRUCTION GROUPS EXAMPLE: MOVEP A1, X:<<$FFFE BEFORE EXECUTION A2 55 X 7 A1 AFTER EXECUTION A0 A2 48 47 24 23 0 X 1 2 3 4 5 6 X X X X X X 0 23 0 23 0 55 X 7 A1 A0 48 47 24 23 0 X 1 2 3 4 5 6 X X X X X X 0 23 0 23 0 X MEMORY 23 $FFFF $FFFE X MEMORY 0 23 $FFFF $FFFE 0 0 F F F F* 0 0 0 3 4 5 6 I/O SHORT ABSOLUTE ADDRESS SPACE $FFC0 $FFC0 *Contents of Bus Control Register (X:$FFFE) After Reset Assembler Syntax: pp Operands Referenced: X:, Y Memories Additional Instruction Execution Time (Cl
INSTRUCTION GROUPS Table 6-1 Addressing Modes Summary Addressing Mode Register Direct Data or Control Register Address Register Address Modifier Register Address Offset Register Modifier MMMM Operand Reference P No No No No S C D X X Address Register Indirect No Update No X Postincrement by 1 Yes X Postdecrement by 1 Yes X Postincrement by Offset Nn Yes X Postdecrement by Offset Nn Yes X Where: MMMM = Address Modifier Indexed byPOffset Nn Yes X = Program Reference Predecrement by 1 Yes X S = Stac
INSTRUCTION GROUPS ABS ADC ADD ADDL ADDR ASL ASR CLR CMP CMPM DEC* DIV* INC* MAC MACR MPY MPYR NEG NORM* RND SBC SUB SUBL SUBR Tcc* TFR TST Absolute Value Add Long with Carry Addition Shift Left and Add Shift Right and Add Arithmetic Shift Left Arithmetic Shift Right Clear an Operand Compare Compare Magnitude Decrement by One Divide Iteration Increment by One Signed Multiply-Accumulate** Signed Multiply-Accumulate and Round** Signed Multiply** Signed Multiply and Round** Negate Accumulator Normalize Round
INSTRUCTION GROUPS Therefore, the instruction actually ignores what appears to be a duplicate destination and logically ANDs the value in the X0 register with the bits in the A1 portion (bits 47-24) of the A accumulator. The parallel move shown above can simultaneously write to either of the other two portions of the A or the B accumulator without conflict. Avoid confusion by explicitly stating A1 or B1 in the original instruction.
INSTRUCTION GROUPS 6.4.3 Bit Manipulation Instructions The bit manipulation instructions test the state of any single bit in a memory location or a register and then optionally set, clear, or invert the bit. The carry bit of the CCR will contain the result of the bit test. The following list defines the bit manipulation instructions: BCLR BSET BCHG BTST Bit Test and Clear Bit Test and Set Bit Test and Change Bit Test on Memory and Registers 6.4.
INSTRUCTION GROUPS START OF LOOP 1)SP+1 - SP; LA - SSH; LC - SSL; #xxx - LC 2)SP+1 - SP; PC - SSH; SR - SSL; Expr–1 - LA 3)1 - LF END OF LOOP 1)SSL(LF) - SR 2)SP–1 - SP; SSH - LA; SSL - LC; SP–1 - SP 3)PC + 1 - PC NOTE: #xxx=Loop Count Number Expr=Expression Figure 6-13 Hardware DO Loop 2. The stack is pushed again. A. The SP is incremented. B. The address of the first instruction in the program loop (PC) and the current SR contents are pushed onto the SS. C.
INSTRUCTION GROUPS DO #n1,END1 : DO #n2,END2 : : MOVE A,X:(R0)+ END2 ADD A,B END1 X:(R1)+,X0 Figure 6-14 Nested DO Loops 6.4.5 Move Instructions The move instructions perform data movement over the XDB and YDB or over the GDB. Move instructions only affect the CCR bits S and L The S bit is affected if data growth is detected when the A or B registers are moved onto the bus. The L bit is affected if limiting is performed when reading a data ALU accumulator register.
INSTRUCTION GROUPS OPCODE/OPERANDS IMMEDIATE SHORT DATA ADDRESS REGISTER UPDATE REGISTER TO REGISTER X MEMORY X MEMORY PLUS REGISTER Y MEMORY Y MEMORY PLUS REGISTER ADD ADD ADD ADD ADD ADD ADD X0,A X0,A X0,A X0,A X0,A X0,A X0,A PARALLEL MOVE EXAMPLES #$05,Y1 (R0)+N0 A1,Y0 X0,X:(R3)+ X:(R4)–,X1 A,Y0 Y:(R6)+N6,X0 A,X0 B,Y:(R0) NOTE: Parallel Move Syntax—Source(Src), Destination(Dst) Figure 6-15 Classifications of Parallel Data Moves contents of the 56-bit registers A and B were rounded to 24 bits bef
INSTRUCTION GROUPS JCLR JSET JScc JSR JSCLR JSSET NOP REP RESET RTI RTS STOP SWI WAIT Jump if Bit Clear Jump if Bit Set Jump to Subroutine Conditionally Jump to Subroutine Jump to Subroutine if Bit Clear Jump to Subroutine if Bit Set No Operation Repeat Next Instruction Reset On-Chip Peripheral Devices Return from Interrupt Return from Subroutine Stop Processing (Low-Power Standby) Software Interrupt Wait for Interrupt (Low-Power Standby) Example A ADD X0,A XY MEMORY MOVE X0,X:(R3)+ Y:(R7)-,B +1 R7
INSTRUCTION GROUPS 6 - 30 INSTRUCTION SET INTRODUCTION MOTOROLA
SECTION 7 PROCESSING STATES STOP NORMAL WAIT RESET EXCEPTION MOTOROLA PROCESSING STATES 7-1
SECTION CONTENTS SECTION 7.1 PROCESSING STATES ............................................................ 3 SECTION 7.2 NORMAL PROCESSING STATE .............................................. 3 7.2.1 Instruction Pipeline ............................................................................. 3 7.2.2 Summary of Pipeline-Related Restrictions ......................................... 8 SECTION 7.3 EXCEPTION PROCESSING STATE ......................................... 10 7.3.1 Interrupt Types ............
PROCESSING STATES 7.1 PROCESSING STATES The DSP56K processor is always in one of five processing states: normal, exception, reset, wait, or stop. This section describes each of the processing states. 7.2 NORMAL PROCESSING STATE The normal processing state is associated with instruction execution. Details about normal processing of the individual instructions can be found in APPENDIX A - INSTRUCTION SET DETAILS.
NORMAL PROCESSING STATE Each instruction requires a minimum of three instruction cycles (12 clock phases) to be fetched, decoded, and executed. This means that there is a delay of three instruction cycles on powerup to fill the pipe. A new instruction may begin immediately following the previous instruction.
NORMAL PROCESSING STATE Case 2: One of the more common sequences where pipeline effects are apparent is as follows: • ;Move a number into register Rn (n=0–7). • MOVE #xx,Rn MOVE X:(Rn),A ;Use the new contents of Rn to address memory. • • In this case, before the first MOVE instruction has written Rn during its execution cycle, the second MOVE has accessed the old Rn, using the old contents of Rn. This is because the address for indirect moves is formed during the decode cycle.
NORMAL PROCESSING STATE second instruction of the downloaded code at P:$0001 of the internal RAM. However, the ANDI instruction allows the OMR to be changed before the JMP instruction uses it, and the JMP fetches P:$0000 of the internal RAM. Case 4: An interrupt has two additional control cycles that are executed in the interrupt controller concurrently with the fetch, decode, and execute cycles (see Section 7.3 and Figure 7-4).
NORMAL PROCESSING STATE Note 1: INST 3 may be executed at that point only if the preceding instruction (INST 2) was a single-word instruction. Note 2: II=Interrupt instruction from maskable interrupt. The following program flow will not occur because the new interrupt mask level becomes effective after a pipeline latency of four instruction cycles: • • ORI #03,MR ;Disable interrupts. INST 1 INST 2 INST 3 INST 4 II ;Interrupts disabled. II+1 ;Interrupts disabled. • • 1.
NORMAL PROCESSING STATE The DO instruction is another instruction that begins execution during the decode cycle of the pipeline. As a result, there are a number of restrictions concerning access contention with the program controller registers accessed by the DO instruction. The ENDDO instruction has similar restrictions. APPENDIX A - INSTRUCTION SET DETAILS contains additional information on the DO and ENDDO instruction restrictions.
NORMAL PROCESSING STATE The restricted instructions at LA-2, LA-1, and LA are as follows: DO BCHG/BCLR/BSET LA, LC, SR, SP, SSH, or SSL BTST SSH JCLR/JSET/JSCLR/JSSET SSH MOVEC/MOVEM/MOVEP from SSH MOVEC/MOVEM/MOVEP to LA, LC, SR, SP, SSH, or SSL ANDI/ORI MR The restricted instructions at LA include the following: Any two-word instruction Jcc, JMP, JScc, JSR, REP, RESET, RTI, RTS, STOP, WAIT Another restriction is shown below: JSR/JScc/JSCLR/JSSET to LA, if loop flag is set ENDDO instruction restrictions:
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) SP and SSH/SSL register manipulation restrictions: In addition to all the above restrictions concerning SP, SSH, and SSL, the following instruction sequences are illegal: 1. BCHG/BCLR/BSET SP 2. MOVEC/MOVEM/MOVEP from SSH or SSL and 1. MOVEC/MOVEM to SP 2. MOVEC/MOVEM/MOVEP from SSH or SSL and 1. MOVEC/MOVEM to SP 2. JCLR/JSET/JSCLR/JSSET SSH or SSL and 1. BCHG/BCLR/BSET SP 2. JCLR/JSET/JSCLR/JSSET SSH or SSL Also, the instruction MOVEC SSH,SSH is illegal.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) the main uses of interrupts is to transfer data between DSP memory or registers and a peripheral device. When such an interrupt occurs, a limited context switch with minimal overhead is ideal. A fast interrupt accomplishes a limited context switch. The processor relies on a long interrupt when it must accomplish a more complex task to service the interrupt. Fast interrupts and long interrupts are described in more detail in Section 7.3.1.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) fetches only two words and then automatically resumes execution of the main program; whereas, the long interrupt must be told to return to the main program by executing an RTI instruction. The fast routine consists of two automatically inserted interrupt instruction words. These words can contain any unrestricted, single two-word instruction or any two one-word instructions (see Section A.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) FAST INTERRUPT SERVICE ROUTINE MAIN PROGRAM SSI RECEIVE DATA $0100 — $0101 MACR INTERRUPT RECOGNIZED $0102 MOVE $0103 MAC $000C MOVEP $0104 REP $000D XXXXXX $0105 MAC $0106 — IMPLICIT RETURN FROM INTERRUPT (a) DSP56K Fast Interrupt LONG INTERRUPT SERVICE ROUTINE MAIN PROGRAM $0100 — $0101 MACR $0102 MOVE $0103 MAC $0104 REP $0105 MAC $0106 — SSI RECEIVE DATA WITH EXCEPTION STATUS INTERRUPT RECOGNIZED $000E JSR $000F
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) Table 7-2 Status Register Interrupt Mask Bits I1 I0 Exceptions Permitted Exceptions Masked 0 0 IPL 0, 1, 2, 3 None 0 1 IPL 1, 2, 3 IPL 0 1 0 IPL 2, 3 IPL 0, 1 1 1 IPL 3 IPL 0, 1, 2 ority levels, see the individual DSP56K family member’s User’s Manual. 7.3.2.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) Table 7-3 Interrupt Priority Level Bits xxL1 xxL0 Enabled IPL 0 0 No — Table 7-4 External Interrupt with the same IPL are pending, a second fixed-priority structure within that IPL determines which interrupt the processor will service. The fixed priority of interrupts within an IPL and the interrupt enable bits for all interrupts are shown in Table 7-5. 7.3.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) Table 7-6 Interrupt Sources Interrupt Starting Address IPL $0000 3 Hardware RESET $0002 3 Stack Error $0004 3 Trace $0006 3 SWI $0008 0-2 IRQA $000A 0-2 IRQB : : Vectors available for peripherals $001E 3 NMI : : Vectors available for peripherals $003E 3 Illegal Instruction Interrupt Source When an interrupt occurs, the instruction at the interrupt starting address is fetched first.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) When either the IRQA or IRQB pin is disabled in the interrupt priority register, the interrupt request coming in on the pin will be ignored, regardless of whether the input was defined as level sensitive or edge sensitive. If the interrupt input is defined as edge sensitive, its edge-detection latch will remain in the reset state for as long as the interrupt pin is disabled.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) CAUTION On all level-sensitive interrupts, the interrupt must be externally released before interrupts are internally re-enabled. Otherwise, the processor will be interrupted repeatedly until the release of the level-sensitive interrupt occurs. The edge sensitive NMI is a priority 3 interrupt and cannot be masked. Only RESET and illegal instruction have higher priority than NMI. 7.3.3.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) PROGRAM MAIN FAST INTERRUPT SERVICE ROUTINE FETCHES FETCHES II (NOP) INFINITE n6 LOOP NO FETCH I1 NO FETCH I2 (a) Instruction Fetches from Memory ILLEGAL INSTRUCTION INTERRUPT RECOGNIZED AS PENDING ILLEGAL INSTRUCTION INTERRUPT RECOGNIZED AS PENDING i INTERRUPT CONTROL CYCLE 1 i INTERRUPT CONTROL CYCLE 2 n1 FETCH DECODE n2 n3 n4 n5 n6 — — ii1 ii2 n5 n1 n2 n3 n4 II — — — i1 ii2 II n1 n2 n3 n4 NOP — — — ii1 ii2
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) PROGRAM MAIN LONG INTERRUPT SERVICE ROUTINE FETCHES FETCHES II (NOP) n6 NO FETCH I1 NO FETCH I2 I3 I4 I5 (a) Instruction Fetches from Memory ILLEGAL INSTRUCTION INTERRUPT RECOGNIZED AS PENDING ILLEGAL INSTRUCTION INTERRUPT RECOGNIZED AS PENDING i INTERRUPT CONTROL CYCLE 1 i INTERRUPT CONTROL CYCLE 2 n1 FETCH DECODE n2 n3 n4 n5 n6 — — ii1 ii2 ii3 ii4 ii5 n1 n2 n3 n4 II — — — ii1 ii2 ii3 ii4 n1 n2 n3 n4 NOP — — —
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) ILLEGAL INSTRUCTION INTERRUPT RECOGNIZED AS PENDING i INTERRUPT CONTROL CYCLE 1 i INTERRUPT CONTROL CYCLE 2 n1 FETCH DECODE n2 n3 n4 n5 n6 n7 — — — ii1 ii2 n8 n1 n2 n3 n4 REP II — — — — ii1 ii2 n8 n1 n2 n3 n4 REP REP NOP — — — ii1 ii2 n8 4 5 6 7 8 12 13 14 15 16 EXECUTE INSTRUCTION CYCLE COUNT i ii II n 1 2 3 9 10 11 = INTERRUPT = INTERRUPT INSTRUCTION WORD = ILLEGAL INSTRUCTION = NORMAL INSTRUCTIO
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) 7.3.3.3 Other Interrupt Sources Other interrupt sources include the stack error interrupt and trace interrupt (DSP56000/ 56001) which are IPL3 interrupts. An overflow or underflow of the system stack (SS) causes a stack error interrupt which is vectored to P:$0002 (see SECTION 5 - PROGRAM CONTROL UNIT for additional information on the stack error flag). Since the stack error is nonrecoverable, a long interrupt should be used to service it.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) MAIN TRACE INSTRUCTION n1 PROGRAM FETCHES NOP THREE NOP INSTRUCTIONS INSERTED BY TRACE MODE NOP NOP TRACE BIT SET IN SR n1 n2 FAST INTERRUPT CAUSED BY TRACE INTERRUPT JSR NOT USED DEBUGGER PROGRAM NEXT TRACE OPERATION SET TRACE BIT IN SSL RTI (a) Instruction Fetches from Memory INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING INTERRUPT CONTROL CYCLE 1 i INTERRUPT CONTROL CYCLE 2 i i FETCH n1 DECODE i NOP NOP NOP JSR — n1 NOP NOP NO
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) 7.3.4 Interrupt Arbitration Interrupt arbitration and control, which occurs concurrently with the fetch-decode-execute cycle, takes two instruction cycles. External interrupts are internally synchronized with the processor clock before their interrupt-pending flags are set. Each external and internal interrupt has its own flag. After each instruction is executed, the DSP arbitrates all interrupts.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) 7.3.6 Instructions Preceding the Interrupt Instruction Fetch The following one-word instructions are aborted when they are fetched in the cycle preceding the fetch of the first interrupt instruction word — REP, STOP, WAIT, RESET, RTI, RTS, Jcc, JMP, JScc, and JSR. Two-word instructions are aborted when the first interrupt instruction word fetched will replace the fetch of the second word of the two-word instruction.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) 7.3.7 Interrupt Instruction Execution Interrupt instruction execution is considered “fast” if neither of the instructions of the interrupt service routine causes a change of flow. A JSR within a fast interrupt routine forms a long interrupt, which is terminated with an RTI instruction to restore the PC and SR from the stack and return to normal program execution.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) MAIN PROGRAM MEMORY INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING n1 ADDITIONAL INTERRUPTS DISABLED DURING FAST INTERRUPT ii1 n2 ii2 n3 n4 INTERRUPTS RE-ENABLED ii = INTERRUPT INSTRUCTION n = NORMAL INSTRUCTION (a) Instruction Fetches from Memory INTERRUPTS RE-ENABLED INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING INTERRUPT CONTROL CYCLE 1 i i INTERRUPT CONTROL CYCLE 2 n1 FETCH DECODE n2 ii1 ii2 n3 n4 n1 n2 ii1 ii2 n3 n4 n1
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) MAIN PROGRAM MEMORY INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING n1 ADDITIONAL INTERRUPTS DISABLED DURING FAST INTERRUPT ii1 n2 ii2 n3 n4 n5 INTERRUPTS RE-ENABLED FOUR INSTRUCTION DECODES ii1 n6 ADDITIONAL INTERRUPTS DISABLED DURING FAST INTERRUPT ii2 n7 n8 n9 INTERRUPTS RE-ENABLED ii = INTERRUPT INSTRUCTION n = NORMAL INSTRUCTION (a) Instruction Fetches from Memory INTERRUPTS RE-ENABLED INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) 6. The fast interrupt returns without an RTI. 7. Normal instruction fetching resumes using the PC following the completion of the fast interrupt routine. 8. A fast interrupt is not interruptible. 9. A JSR instruction within the fast interrupt routine forms a long interrupt routine. 10. The primary application is to move data between memory and I/O devices. The execution of a long interrupt routine always conforms to the following rules: 1.
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) LONG INTERRUPT SERVICE ROUTINE FETCHES (STARTS WITH A FAST INTERRUPT) MAIN PROGRAM FETCHES JSR CAN BE IN EITHER LOCATION TO FORM A LONG INTERRUPT ii1 ii2 INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING n1 n2 n3 PROGRAM COUNTER RESUMES OPERATION ii3 n4 ii4 INTERRUPTS RE-ENABLED INTERRUPT ROUTINE ii7 RTI EXPLICIT RETURN FROM INTERRUPT (SHOULD BE RTI) (a) Instruction Fetches from Memory INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING INTERRUPTS RE-
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) FAST INTERRUPT VECTOR LONG INTERRUPT SUBROUTINE JSR ii2 NOT USED ii3 MAIN PROGRAM n1 ii4 n2 iin RTI (a) Instruction Fetches from Memory INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING INTERRUPTS RE-ENABLED INTERRUPT CONTROL CYCLE 1 i INTERRUPT CONTROL CYCLE 2 i FETCH n1 DECODE JSR — ii2 ii3 ii4 iin RTI — n2 n1 JSR NOP ii2 ii3 ii4 iin RTI NOP n2 n1 JSR NOP ii2 ii3 ii4 iin RTI NOP n2 4 5 6 7 8 9 10 11
EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) FAST INTERRUPT VECTOR LONG INTERRUPT SUBROUTINE n1 ii1 ii3 n2 JSR ii4 MAIN PROGRAM ii5 ii6 iin RTI (a) Instruction Fetches from Memory INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING INTERRUPTS RE-ENABLED INTERRUPT CONTROL CYCLE 1 i i INTERRUPT CONTROL CYCLE 2 n1 FETCH DECODE ii1 JSR — ii3 ii4 ii5 n1 ii1 JSR NOP ii3 ii4 n1 ii1 JSR NOP 4 5 6 7 EXECUTE INSTRUCTION CYCLE COUNT 1 2 3 iin RTI — n2 ii5 ii6 iin RTI
RESET PROCESSING STATE mented to one (see Figure 7-13). During the execution of n2 in Figure 7-13, no interrupts will be serviced. When LC finally decrements to one, the fetches are reinitiated, and pending interrupts can be serviced. Sequential REP packages will cause pending interrupts to be rejected until the sequence of REP packages ends. REP packages are not interruptible because the instruction being repeated is not refetched.
RESET PROCESSING STATE MAIN PROGRAM FETCHES n2 INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING n2 REPEAT m TIMES n1 REP m ADDITIONAL INTERRUPTS DISABLED DURING FAST INTERRUPT n2 n2 INSTRUCTION n2 REPLACED PER THE REP INSTRUCTION n2 n3 n4 INTERRUPTS RE-ENABLED n5 n6 i1 i2 FAST INTERRUPT SERVICE ROUTINE FETCHES (FROM BETWEEN P:$0000 AND P:$003F) i = INTERRUPT INSTRUCTION n = NORMAL INSTRUCTION (a) Instruction Fetches from Memory INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING INTERRUPTS RE-ENABL
RESET PROCESSING STATE MAIN REPEAT m TIMES PROGRAM FETCHES INTERRUPT PENDING INTERRUPT PENDING INTERRUPT PENDING INTERRUPT REJECTED n2 n1 REP m INTERRUPT REJECTED ••• n2 n2 REPEAT m TIMES n2 REP m n3 INTERRUPT REJECTED n4 REP m n4 n5 n4 n4 n6 INTERRUPT PENDING ••• n7 n8 REPEAT m TIMES n9 ii1 n6 ••• n6 n6 ii2 (a) Instruction Fetches from Memory INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING INTERRUPT CONTROL CYCLE 1 i INTERRUPT CONTROL CYCLE 2 FETCH i i% REP n2 DECODE i
WAIT PROCESSING STATE 7.5 WAIT PROCESSING STATE The WAIT instruction brings the processor into the wait processing state which is one of two low power-consumption states. Asserting the OnCE’s debug request pin releases the DSP from the wait state. In the wait state, the internal clock is disabled from all internal circuitry except the internal peripherals. All internal processing is halted until an unmasked interrupt occurs, the Debug Request pin of the OnCE is asserted, or the DSP is reset.
STOP PROCESSING STATE INTERRUPT SYNCHRONIZED AND RECOGNIZED AS PENDING i INTERRUPT CONTROL CYCLE 1 i INTERRUPT CONTROL CYCLE 2 i ii n FETCH n3 n4 — — — — — — ii1 ii2 n4 DECODE n2 WAIT — — — — — — — ii1 ii2 EXECUTE n1 n2 WAIT — — — — — — — ii1 INSTRUCTION CYCLE COUNT 1 2 3 4 5 6 7 8 9 10 11 = INTERRUPT = INTERRUPT INSTRUCTION WORD = NORMAL INSTRUCTION WORD EQUIVALENT TO EIGHT NOPs Figure 7-16 Simultaneous Wait Instruction and Interrupt 7.
STOP PROCESSING STATE The stop processing state halts all activity in the processor until one of the following actions occurs: 1. A low level is applied to the IRQA pin. 2. A low level is applied to the RESET pin. 3. A low level is applied to the DR pin Either of these actions will activate the oscillator, and, after a clock stabilization delay, clocks to the processor and peripherals will be re-enabled. The clock stabilization delay period is determined by the stop delay (SD) bit in the OMR.
STOP PROCESSING STATE IRQA FETCH n3 n4 — — DECODE n2 STOP — — EXECUTE n1 n2 STOP — STOP CYCLE COUNT 1 2 3 4 ii1 5 6 7 8 (9) RESUME STOP CYCLE COUNT 4, INTERRUPTS ENABLED CLOCK STOPPED 131,072 T OR 16 T CYCLE COUNT STARTED IRQA = INTERRUPT REQUEST A SIGNAL n = NORMAL INSTRUCTION WORD STOP = INTERRUPT INSTRUCTION WORD Figure 7-18 STOP Instruction Sequence Followed by IRQA Figure 7-18 shows the system being restarted by asserting the IRQA signal.
STOP PROCESSING STATE the first instruction fetch). If the IRQA signal is released (pulled high) after a minimum of 4T but less than 128K T cycles, no IRQA interrupt will occur, and the instruction fetched after stop cycle 8 will be the next sequential instruction (n4 in Figure 7-18).
STOP PROCESSING STATE the period of the first oscillator cycles will be irregular; thus, an additional period of 19,000 T cycles should be allowed for oscillator irregularity (the specification recommends a total minimum period of 150,000 T cycles for oscillator stabilization). If an external oscillator is used that is already stabilized, no additional time is needed. The PLL may be disabled or not when the chip enters the STOP state.
STOP PROCESSING STATE RESET PROCESSOR ENTERS RESET STATE PROCESSOR LEAVES RESET STATE INTERRUPT CONTROL CYCLE 1 INTERRUPT CONTROL CYCLE 2 FETCH n3 n4 — — nop nA nB nC nD nE DECODE n2 STOP — — nop nop nA nB nC nD EXECUTE n1 n2 STOP — nop nop nop nA nB nC STOP CYCLE COUNT 1 2 3 4 CLOCK STOPPED = INTERRUPT n = NORMAL INSTRUCTION WORD nA, nB, nC = INSTRUCTIONS IN RESET ROUTINE STOP = INTERRUPT INSTRUCTION WORD IRESET Figure 7-19 STOP Instruction Sequence Recovering w
STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 - 43
STOP PROCESSING STATE 7 - 44 PROCESSING STATES MOTOROLA
SECTION 8 PORT A MOTOROLA PORT A 8-1
SECTION CONTENTS SECTION 8.1 PORT A OVERVIEW ..................................................................3 SECTION 8.2 PORT A INTERFACE .................................................................3 8.2.1 Read/Write Control Signals .................................................................5 8.2.1.1 Program Memory Select (PS) ..................................................... 5 8.2.1.2 Data Memory Select (DS) ........................................................... 5 8.2.1.
PORT A OVERVIEW 8.1 PORT A OVERVIEW Port A provides a versatile interface to external memory, allowing economical connection with fast memories, slow memories/devices, and multiple bus master systems. This section introduces the signals associated with this memory expansion port that are common among the members of the DSP56K family of processors which feature Port A.
PORT A INTERFACE 16 - BIT INTERNAL ADDRESS BUSES X ADDRESS (XA) 16 Y ADDRESS (YA) EXTERNAL ADDRESS BUS SWITCH EXTERNAL ADDRESS BUS A0 - A15 PROGRAM ADDRESS (PA) 24 - BIT INTERNAL DATA BUSES X DATA (XD) 24 Y DATA (YD) EXTERNAL DATA BUS SWITCH EXTERNAL DATA BUS D0 - D23 PROGRAM DATA (PD) GLOBAL DATA (GD) BUS CONTROL SIGNALS EXTERNAL BUS CONTROL LOGIC RD - READ ENABLE WR - WRITE ENABLE PS - PROGRAM MEMORY SELECT DS - DATA MEMORY SELECT X/Y - X MEMORY/Y MEMORY SELECT BUS ACCESS CONTROL PINS Fig
PORT A INTERFACE be subdivided into three additional groups: read/write control (RD and WR), address space selection (including program memory select (PS), data memory select (DS), and X/ Y select) and bus access control. The read/write controls are self-descriptive. They can be used as decoded read and write controls, or, the write signal can be used as the read/write control and the read signal can be used as an output enable (or data enable) control for the memory.
PORT A INTERFACE 8.2.2.1 Address (A0–A15) These three-state output pins specify the address for external program and data memory accesses. To minimize power dissipation, A0–A15 do not change state when external memory spaces are not being accessed. 8.2.2.2 Data (D0–D23) These pins provide the bidirectional data bus for external program and data memory accesses. D0–D23 are in the high-impedance state when the bus grant signal is asserted. 8.2.
PORT A INTERFACE WT) facility, which allows an external device to insert an arbitrary number of wait states when accessing either a single location or multiple locations of external memory or I/O space. Wait states are executed until the external device releases the DSP to finish the external memory cycle. An internal wait-state generator can be programmed using the BCR to insert up to15 wait states if it is known ahead of time that access to slower memory or I/O devices is required.
PORT A INTERFACE 8-8 PORT A MOTOROLA
SECTION 9 PLL CLOCK OSCILLATOR Φ ∫ x dx VCO MOTOROLA PLL CLOCK OSCILLATOR 9-1
SECTION CONTENTS SECTION 9.1 PLL CLOCK OSCILLATOR INTRODUCTION ........................... 3 SECTION 9.2 PLL COMPONENTS .................................................................. 3 9.2.1 Phase Detector and Charge Pump Loop Filter ................................... 4 9.2.2 Voltage Controlled Oscillator (VCO) ................................................... 5 9.2.3 Frequency Multiplier ........................................................................... 5 9.2.4 Low Power Divider (LPD) ....
PLL CLOCK OSCILLATOR INTRODUCTION 9.1 PLL CLOCK OSCILLATOR INTRODUCTION The DSP56K family of processors (with the exception of the DSP56000 and DSP56001) features a PLL (phase-locked loop) clock oscillator in its central processing module, shown in Figure 9-2. The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input, a feature which offers two immediate benefits.
PLL COMPONENTS EXPANSION AREA Y MEMORY RAM/ROM EXPANSION EXTERNAL ADDRESS BUS SWITCH BUS CONTROL PORT A YAB XAB PAB ADDRESS GENERATION UNIT ADDRESS PERIPHERAL PINS 24-Bit 56K Mod- X MEMORY RAM/ROM EXPANSION CONTROL PROGRAM RAM/ROM EXPANSION PERIPHERAL MODULES YDB XDB PDB EXTERNAL DATA BUS SWITCH DATA INTERNAL DATA BUS SWITCH GDB PLL CLOCK GENERATOR PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLER PROGRAM ADDRESS GENERATOR DATA ALU 24X24+56→56-BIT MAC TWO 56-BIT ACCUMULATORS OnC
PLL COMPONENTS The charge pump loop filter receives signals from the PD, and either increases or decreases the phase based on the PD signals. An external capacitor is connected to the PCAP pin (described in Section 9.3) and determines the PLL operation. (See the appropriate Technical Data Sheet for more detailed information about a particular device’s phase and frequency.
PLL COMPONENTS 11 10 9 8 MF11 MF10 MF9 MF8 7 6 5 4 3 MF7 MF6 MF5 MF4 MF3 23 22 21 20 19 18 17 16 15 ** CKOS CSRC COD1 COD0 PEN PSTP XTLD DF3 2 1 0 MF2 MF1 MF0 14 13 12 DF2 DF1 DF0 ** Reserved bits, read as zero, should be written with zero for future compatibility. Figure 9-3 PLL Control Register (PCTL) shows how to program the MF0-MF11 bits. The VCO will oscillate at a frequency of MF x Fext, where Fext is the EXTAL clock frequency.
PLL COMPONENTS shows the programming of the DF0-DF3 bits. Changing the value of the DF0-DF3 bits will not cause a loss of lock condition. Whenever possible, changes of the operating frequency of the chip (for example, to enter a low power mode) should be made by changing the value of the DF0-DF3 bits rather than changing the MF0-MF11 bits.
PLL COMPONENTS cleared. To enable rapid recovery when exiting the STOP state, at the cost of higher power consumption in the STOP state, PSTP should be set. PSTP is cleared by hardware reset. 9.2.5.5 PCTL PLL Enable Bit (PEN) - Bit 18 The PEN bit enables the PLL operation. When this bit is set, the PLL is enabled and the internal clocks will be derived from the PLL VCO output.
PLL PINS Table 9-4 Clock Output Disable Bits COD0-COD1 COD1 COD0 CKOUT Pin 0 0 Clock Out Enabled, Full Strength Output Buffer 0 1 Clock Out Enabled, 2/3 Strength Output Buffer 1 0 Clock Out Enabled, 1/3 Strength Output Buffer 1 1 Clock Out Disabled 9.2.5.7 PCTL Chip Clock Source Bit (CSRC) - Bit 21 The CSRC bit specifies whether the clock for the chip is taken from the output of the VCO or is taken from the output of the Low Power Divider (LPD).
PLL PINS CLVCC VCC for the CKOUT output. The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the VCC power rail. CLVCC should be bypassed to CLGND by a 0.1µF capacitor located as close as possible to the chip package. CLGND GND for the CKOUT output. The pin should be provided with an extremely low impedance path to ground. CLVCC should be bypassed to CLGND by a 0.1µF capacitor located as close as possible to the chip package.
PLL OPERATION CONSIDERATIONS 9.4 PLL OPERATION CONSIDERATIONS The following paragraphs discuss PLL operation considerations. 9.4.
PLL OPERATION CONSIDERATIONS 4. For all input frequencies which would result in a VCO output frequency lower than the minimum specified in the device’s Technical Data Sheet (typically 10 MHz), PINIT must be cleared during hardware reset, disabling PLL operation. Otherwise, proper operation of the PLL cannot be guaranteed.
PLL OPERATION CONSIDERATIONS chip clock. (Here, T3 is equal to the phase described by the new divide factor plus the time required to wait for a synchronizing pulse, which is less than 1.5ETc.) For MF>4, such synchronization is not guaranteed and the instruction cycle is not lengthened. If the DF0-DF3 bits are changed by the same instruction that changes the MF0-MF11 bits, the LPD divider factor changes before the detection of the change in the multiplication factor.
PLL OPERATION CONSIDERATIONS While the PLL is regaining lock, the CKOUT clock output remains at the same logic level it held when the PLL lost lock, which is when the clocks were frozen in the DSP. When the chip enters the WAIT processing state, the core phases are disabled but CKOUT continues to operate. When PLL is disabled, CKOUT will be fed from EXTAL.
SECTION 10 ON-CHIP EMULATION (OnCE) 10- 2 ON-CHIP EMULATION (OnCE) MOTOROLA
SECTION CONTENTS SECTION 10.1 INTRODUCTION ......................................................................3 SECTION 10.2 ON-CHIP EMULATION (OnCE) PINS ......................................3 SECTION 10.3 OnCE CONTROLLER AND SERIAL INTERFACE ..................6 SECTION 10.4 OnCE MEMORY BREAKPOINT LOGIC ..................................11 SECTION 10.5 OnCE TRACE LOGIC ..............................................................13 SECTION 10.6 METHODS OF ENTERING THE DEBUG MODE ....................
ON-CHIP EMULATION INTRODUCTION 10.1 ON-CHIP EMULATION INTRODUCTION The DSP56K on-chip emulation (OnCE) circuitry provides a sophisticated debugging tool that allows simple, inexpensive, and speed independent access to the processor’s internal registers and peripherals. OnCE tells application programmers exactly what the status is within the registers, memory locations, buses, and even the last five instructions that were executed.
ON-CHIP EMULATION (OnCE) PINS EXPANSION AREA Y MEMORY RAM/ROM EXPANSION EXTERNAL ADDRESS BUS SWITCH BUS CONTROL PORT A YAB XAB PAB ADDRESS GENERATION UNIT ADDRESS PERIPHERAL PINS 24-Bit 56K Mod- X MEMORY RAM/ROM EXPANSION CONTROL PROGRAM RAM/ROM EXPANSION PERIPHERAL MODULES XDB PDB EXTERNAL DATA BUS SWITCH DATA YDB INTERNAL DATA BUS SWITCH GDB PLL CLOCK GENERATOR PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLER PROGRAM ADDRESS GENERATOR DATA ALU 24X24+56→56-BIT MAC TWO 56-BIT AC
ON-CHIP EMULATION (OnCE) PINS 10.2.2 Debug Serial Clock/Chip Status 1 (DSCK/OS1) The DSCK/OS1 pin supplies the serial clock to the OnCE when it is an input. The serial clock provides pulses required to shift data into and out of the OnCE serial port. (Data is clocked into the OnCE on the falling edge and is clocked out of the OnCE serial port on the rising edge.) The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency.
OnCE CONTROLLER AND SERIAL INTERFACE 10.2.4 Debug Request Input (DR) The debug request input (DR) allows the user to enter the debug mode of operation from the external command controller. When DR is asserted, it causes the DSP56K to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the DSI line.
OnCE CONTROLLER AND SERIAL INTERFACE 7 6 R/W GO 5 EX 4 3 2 1 0 RS4 RS3 RS2 RS1 RS0 Figure 10-4 OnCE Command Register 10.3.1.1 Register Select (RS4-RS0) Bits 0-4 The Register Select bits define which register is source (destination) for the read (write) operation. Table 10-2 indicates the OnCE register addresses.
OnCE CONTROLLER AND SERIAL INTERFACE 10.3.1.2 Exit Command (EX) Bit 5 If the EX bit is set, the processor will leave the debug mode and resume normal operation. The Exit command is executed only if the Go command is issued, and the operation is write to OPDBR or read/write to “No Register Selected”. Otherwise the EX bit is ignored. EX Action 0 Remain in debug mode 1 Leave debug mode 10.3.1.
OnCE CONTROLLER AND SERIAL INTERFACE shifted in (so a new command is available) and the second indicating that 24 bits were shifted in (the data associated with that command is available) or that 24 bits were shifted out (the data required by a read command was shifted out). 10.3.3 OnCE Decoder (ODEC) The ODEC supervises the entire OnCE activity.
OnCE CONTROLLER AND SERIAL INTERFACE When BC3-BC0=0011, program memory breakpoints are enabled for any read or write access to the Program space (any kind of MOVE, true and false fetches, fetches of second word, etc.). When BC3-BC0=0100, program memory breakpoints are enabled only for fetches of the first instruction word of instructions that are actually executed.
OnCE MEMORY BREAKPOINT LOGIC 10.3.4.4 Software Debug Occurrence (SWO) Bit 8 This read-only status bit is set when the processor enters debug mode of operation as a result of the execution of the DEBUG or DEBUGcc instruction with condition true. This bit is cleared on hardware reset or when leaving the debug mode with the GO and EX bits set. 10.3.4.5 Memory Breakpoint Occurrence (MBO) Bit 9 This read-only status bit is set when a memory breakpoint occurs.
OnCE MEMORY BREAKPOINT LOGIC DSCK DSO PAB XAB YAB DSI MEMORY ADDRESS LATCH MEMORY BUS SELECT HIGH ADDRESS COMPARATOR . . LOWER OR EQUAL UPPER LIMIT REGISTER MEMORY BREAKPOINT SELECTION LOW ADDRESS COMPARATOR . . . . BC3-BC0 HIGHER OR EQUAL LOWER LIMIT REGISTER . DEC BREAKPOINT OCCURRED BREAKPOINT COUNTER COUNT=0 . ISBKPT Figure 10-6 OnCE Memory Breakpoint Logic 10.4.2 Memory Upper Limit Register (OMULR) The 16-bit Memory Upper Limit Register stores the memory breakpoint upper limit.
OnCE TRACE LOGIC points, OMLLR must be loaded by the external command controller. 10.4.4 Memory High Address Comparator (OMHC) The OMHC compares the current memory address (stored in OMAL) with the OMULR contents. If OMULR is higher than or equal to OMAL then the comparator delivers a signal indicating that the address is lower than or equal to the upper limit. 10.4.5 Memory Low Address Comparator (OMLC) The OMLC compares the current memory address (stored in OMAL) with the OMLLR contents.
OnCE TRACE LOGIC The trace counter allows more than one instruction to be executed in real time before the chip returns to the debug mode of operation. This feature helps the software developer debug sections of code which do not have a normal flow or are getting hung up in infinite loops. The trace counter also enables the user to count the number of instructions executed in a code segment.
METHODS OF ENTERING THE DEBUG MODE 10.6 METHODS OF ENTERING THE DEBUG MODE The chip acknowledges having entered the debug mode by pulsing low the DSO line, informing the external command controller that the chip has entered the debug mode and is waiting for commands.The following paragraphs discuss conditions that bring the processor into the debug mode. 10.6.1 External Debug Request During RESET Holding the DR line asserted during the assertion of RESET causes the chip to enter the debug mode.
PIPELINE INFORMATION AND GLOBAL DATA BUS REGISTER 10.6.5 Software Request During Normal Activity Upon executing the DEBUG or DEBUGcc instruction when the specified condition is true, the chip enters the debug mode after the instruction following the DEBUG instruction has entered the instruction latch. 10.6.6 Enabling Trace Mode When the trace mode mechanism is enabled and the trace counter is greater than zero, the trace counter is decremented after each instruction execution.
PROGRAM ADDRESS BUS HISTORY BUFFER 10.7.2 Pipeline Instruction Latch Register (OPILR) The OPILR is a 24-bit latch that stores the value of the instruction latch before the debug mode is entered. OPILR can only be read through the OnCE serial interface. This register is affected by the operations performed during the debug mode and must be restored by the external command controller when returning to normal mode.
PROGRAM ADDRESS BUS HISTORY BUFFER PAB FETCH ADDRESS (OPABFR) DECODE ADDRESS (OPABDR) PAB FIFO REGISTER 0 PAB FIFO REGISTER 1 PAB FIFO REGISTER 2 CIRCULAR BUFFER POINTER PAB FIFO REGISTER 3 PAB FIFO REGISTER 4 PAB FIFO SHIFT REGISTER DSCK DSO Figure 10-9 OnCE PAB FIFO addresses of the last five instructions that were executed. 10.8.1 PAB Register for Fetch (OPABFR) The OPABFR is a 16-bit register that stores the address of the last instruction that was fetched before the debug mode was entered.
SERIAL PROTOCOL DESCRIPTION This register is not affected by the operations performed during the debug mode. 10.8.3 PAB FIFO The PAB FIFO stores the addresses of the last five instructions that were executed. The FIFO is implemented as a circular buffer containing five 16-bit registers and one 3-bit counter. All the registers have the same address but any read access to the FIFO address will cause the counter to increment, making it point to the next FIFO register.
DSP56K TARGET SITE DEBUG SYSTEM REQUIREMENTS 10.10 DSP56K TARGET SITE DEBUG SYSTEM REQUIREMENTS A typical DSP56K debug environment consists of a target system where the DSP56K resides in the user defined hardware. The debug serial port interfaces to the external command controller over a 6-wire link which includes the 4 OnCE wires, a ground, and a reset wire. The reset wire is optional and is only used to reset the DSP56K and its associated circuitry.
USING THE OnCE f. CLK g. Send command READ FIFO REGISTER and increment counter (10010001) h. ACK i. CLK j. Send command READ FIFO REGISTER and increment counter (10010001) k. ACK l. CLK m. Send command READ FIFO REGISTER and increment counter (10010001) n. ACK o. CLK p. Send command READ FIFO REGISTER and increment counter (10010001) q. ACK r. CLK s. Send command READ FIFO REGISTER and increment counter (10010001) t. ACK u. CLK 10.11.2 Displaying A Specified Register 1.
USING THE OnCE The OnCE controller selects GDB as source for serial data. 6. ACK 7. CLK 10.11.3 Displaying X Memory Area Starting From Address XXXX This command uses R0 to minimize serial traffic. 1. Send command WRITE PDB REGISTER, GO, no EX (01001001). The OnCE controller selects PDB as destination for serial data. 2. ACK 3. Send the 24-bit DSP56K opcode: “MOVE R0,x:OGDB” After 24 bits have been received the PDB register drives the PDB.
USING THE OnCE troller releases the chip from the debug mode and the instruction starts execution. The signal that marks the end of the instruction returns the chip to the debug mode. 15. ACK 16. Send command WRITE PDB REGISTER, GO, no EX (01001001) The OnCE controller selects PDB as destination for serial data. 17. ACK 18. Send the 24-bit DSP56K opcode: “MOVE X:(R0)+,x:OGDB” After 24 bits have been received, the PDB register drives the PDB.
USING THE OnCE troller causes the processor to load the opcode. 33. ACK 34. Send command WRITE PDB REGISTER, GO, no EX (01001001) The OnCE controller selects PDB as destination for serial data. 35. ACK 36. Send the 24-bit second word of: “MOVE #saved_r0,R0” (the saved_r0 field). After 24 bits have been received, the PDB register drives the PDB. The OnCE controller releases the chip from the debug mode and the instruction starts execution.
USING THE OnCE 10.11.4 Executing a Single-Word DSP56K Instruction While in Debug Mode 1. Send command WRITE PDB REGISTER, GO, no EX (01001001). The OnCE controller selects PDB as destination for serial data. 2. ACK 3. Send the single-word 24-bit DSP56K opcode to be executed. After 24 bits have been received, the PDB register drives the PDB. The OnCE controller releases the chip from the debug mode and the chip executes the instruction.
USING THE OnCE 10.11.6.1 Case 1: Return To The Previous Program (Return To Normal Mode) 1. Send command WRITE PDB REGISTER, no GO, no EX (00001001) The OnCE controller selects the PDB as the destination for serial data. Also, the OnCE controller selects the on-chip PAB register as the source for the PAB bus. 2. ACK 3. Send the 24 bits of the saved PIL (instruction latch) value. After the 24 bits have been received, the PDB register drives the PDB. The OnCE controller causes the PIL to latch the PDB value.
USING THE OnCE ecution. The EX bit causes the OnCE controller to release the chip from the debug mode and the status bits in OSCR are cleared. The GO bit causes the chip to start executing the jump instruction which will then cause the chip to continue instruction execution from the target address. Note that the trace counter will count the jump instruction so the current trace counter may need to be corrected if the trace mode is enabled. 10.11.
USING THE OnCE MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 29
SECTION 11 ADDITIONAL SUPPORT Motorola ola DSP Audio: Codec Routines: DTMF Routines: Fast Fourier Transforms: Filters: Floating-Point Routines: Functions: Lattice Filters: Matrix Operations: Reed-Solomon Encoder: Sorting Routines: Speech: Standard I/O Equates: Tools and Utilities: Motorola DSP Product Support DSP56000CLASx Assembler/Simulator C Language Compiler DSP56000ADSx Application Development System MOTOROLA ADDITIONAL SUPPORT Motorola DSP News Motorola Field Application Engineers Design Hotline
SECTION CONTENTS SECTION 11.1 USER SUPPORT .....................................................................3 SECTION 11.2 MOTOROLA DSP PRODUCT SUPPORT ...............................4 11.2.1 DSP56000CLASx Assembler/Simulator ...........................................4 11.2.2 Macro Cross Assembler Features: ....................................................4 11.2.3 Simulator Features: ...........................................................................5 11.2.
USER SUPPORT 11.
MOTOROLA DSP PRODUCT SUPPORT The following is a partial list of the support available for the DSP56000/DSP56001. Additional information can be obtained through Dr. BuB or the appropriate support telephone service. 11.
MOTOROLA DSP PRODUCT SUPPORT • • • • • • the DSP56K family of processors Modular programming features: local labels, sections, and external definition/reference directives Nested macro processing capability with support for macro libraries Complex expression evaluation including boolean operators Built-in functions for data conversion, string comparison, and common transcendental math functions Directives to define circular and bit-reversed buffers Extensive error checking and reporting 11.2.
DSP56KADSx APPLICATION DEVELOPMENT SYSTEM • In-line assembler language code compatibility • Full Function preprocessor for: –Macro definition/expansion –File Inclusion –Conditional compilation • Full error detection and reporting 11.3 DSP56KADSx APPLICATION DEVELOPMENT SYSTEM 11.3.
Dr. BuB ELECTRONIC BULLETIN BOARD 11.3.3 Support Integrated Circuits: • 8Kx24 Static RAM – MC56824 • DSP56ADC16 16-bit, sigma-delta 100-kHz analog-to-digital converter • DSP56401 AES/EBU processor • DSP56200 FIR filter 11.4 Dr. BuB ELECTRONIC BULLETIN BOARD Dr. BuB is an electronic bulletin board which provides free source code for a large variety of topics that can be used to develop applications with Motorola DSP products.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version Synopsis Size rvb1.asm 1.0 Easy-to-read reverberation routine 17056 rvb2.asm 1.0 Same as RVB1.ASM but optimized 15442 stereo.hlp 1.0 Help file for STEREO.ASM dge.asm 1.0 Digital Graphic Equalizer code from 1.0 Companded CODEC to linear PCM data conversion 4572 Help for loglin.asm 1479 Test program for loglin.asm 2184 Help for loglint.asm 1993 Linear PCM to companded CODEC data conversion 4847 Help for linlog.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version Synopsis sub.asm 1.0 Subroutine linked for use in IIR DTMF read.me 1.0 Instructions Size 2491 738 Fast Fourier Transforms: sincos.asm 1.2 sincos.hlp sinewave.asm Help for sincos.asm 1.1 sinewave.hlp fftr2a.asm 1.1 fftr2a.hlp fftr2at.asm 1.1 fftr2at.hlp fftr2b.asm 1.1 fftr2b.hlp fftr2c.asm 1.2 fftr2c.hlp fftr2d.asm 1.0 fftr2d.hlp fftr2dt.asm 1.0 fftr2dt.hlp fftr2e.asm 1.0 1.0 fftr2et.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version Synopsis Size fftr2cn.hlp 1.0 Help file for fftr2cn.asm 2468 fftr2en.asm 1.0 1024 point, not-in-place, complex FFT macro with normally ordered input/output 9723 fftr2en.hlp 1.0 Help file for fftr2en.asm 4886 dhit1.asm 1.0 Routine to compute Hilbert transform in the frequency domain 1851 dhit1.hlp 1.0 Help file for dhit1.asm 1007 fftr2bf.asm 1.0 Radix-2, decimation-in-time FFT with block floating point fftr2bf.hlp 1.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version iir5t.asm 1.0 Test program for iir5.asm iir6.asm 1.0 Arbitrary Order Direct Canonic IIR Filter iir6.hlp Synopsis 1289 923 Help for iir6.asm 3020 1377 iir6t.asm 1.0 Test program for iir6.asm iir7.asm 1.0 Cascaded Biquad IIR Filters iir7.hlp Size 900 Help for iir7.asm 3947 iir7t.asm 1.0 Test program for iir7.asm 1432 lms.hlp 1.0 LMS Adaptive Filter Algorithm 5818 transiir.asm 1.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version Synopsis Size fpfloor.asm 2.0 Floating point FLOOR subroutine 2119 durbin.asm 1.0 Solution for LPC coefficients 5615 durbin.hlp 1.0 Help file for DURBIN.ASM 2904 fpfrac.asm 2.0 Floating point FRACTION subroutine 1862 1.0 Log base 2 by polynomial approximation 1118 Functions: log2.asm log2.hlp Help for log2.asm 719 log2t.asm 1.0 Test program for log2.asm 1018 log2nrm.asm 1.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version rand1.hlp Synopsis Help for rand1.asm Size 704 Lattice Filters: latfir1.asm 1.0 latfir1.hlp Lattice FIR Filter Macro 1156 Help for latfir1.asm 6327 latfir1t.asm 1.0 Test program for latfir1.asm 1424 latfir2.asm 1.0 Lattice FIR Filter Macro (modified modulo count) 1174 Help for latfir2.asm 1295 latfir2.hlp latfir2t.asm 1.0 Test program for latfir2.asm 1423 latiir.asm 1.0 Lattice IIR Filter Macro 1257 Help for latiir.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version Synopsis Size table1.asm 1.0 Include file for R-S coder 7971 table2.asm 1.0 Include file for R-S coder 4011 1.0 Array Sort by Straight Selection 1312 Help for sort1.asm 1908 Sorting Routines: sort1.asm sort1.hlp sort1t.asm 1.0 Test program for sort1.asm sort2.asm 1.1 Array Sort by Heapsort Method 2183 Help for sort2.asm 2004 sort2.hlp sort2t.asm 689 1.0 Test program for sort2.asm 700 2.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version Synopsis Size srec.exe 4.10 Srec executable for IBM PC sloader.asm 1.1 Serial loader from the SCI port for the DSP56001 3986 sloader.hlp 1.1 Help for sloader.asm 2598 sloader.p 1.1 Serial loader s-record file for download to EPROM 736 parity.asm 1.0 Parity calculation of a 24-bit number in accumulator A 1641 parity.hlp 1.0 Help for parity.asm 936 parityt.asm 1.0 Test program for parity.asm 685 parityt.hlp 1.
MOTOROLA DSP NEWS 11.5 MOTOROLA DSP NEWS The Motorola DSP News is a quarterly newsletter providing information on new products, application briefs, questions and answers, DSP product information, third-party product news, etc. This newsletter is free and is available upon request by calling the marketing information phone number listed below. 11.6 MOTOROLA FIELD APPLICATION ENGINEERS Information and assistance for DSP applications is available through the local Motorola field office.
TRAINING COURSES – (602) 897-3665 or (800) 521-6274 11.12 TRAINING COURSES – (602) 897-3665 or (800) 521-6274 There are two DSP56000 Family training courses available: 1. Introduction to the DSP5600X (MTTA5) is a 4.5-hour audio-tape course on the DSP56K Family architecture and programming. 2. Introduction to the DSP5600X (MTT31) is a four-day instructor-led course and laboratory which covers the details of the DSP5600X architecture and programming.
REFERENCE BOOKS AND MANUALS DIGITAL SIGNAL PROCESSING Alan V. Oppenheim and Ronald W. Schafer Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975 DIGITAL SIGNAL PROCESSING: A SYSTEM DESIGN APPROACH David J. DeFatta, Joseph G. Lucas, and William S. Hodgkiss New York, NY: John Wiley and Sons, 1988 FOUNDATIONS OF DIGITAL SIGNAL PROCESSING AND DATA ANALYSIS J. A. Cadzow New York, NY: MacMillan Publishing Company, 1987 HANDBOOK OF DIGITAL SIGNAL PROCESSING D. F. Elliott San Diego, CA: Academic Press, Inc.
REFERENCE BOOKS AND MANUALS ADAPTIVE SIGNAL PROCESSING B. Widrow and S. D. Stearns Englewood Cliffs, NJ: Prentice-Hall, Inc., 1985 ART OF DIGITAL AUDIO, THE John Watkinson Stoneham. MA: Focal Press, 1988 DESIGNING DIGITAL FILTERS Charles S. Williams Englewood Cliffs, NJ: Prentice-Hall, Inc., 1986 DIGITAL AUDIO SIGNAL PROCESSING AN ANTHOLOGY John Strawn William Kaufmann, Inc., 1985 DIGITAL CODING OF WAVEFORMS N. S. Jayant and Peter Noll Englewood Cliffs, NJ: Prentice-Hall, Inc.
REFERENCE BOOKS AND MANUALS C Programming Language: C: A REFERENCE MANUAL Samuel P. Harbison and Guy L. Steele Prentice-Hall Software Series, 1987. PROGRAMMING LANGUAGE - C American National Standards Institute, ANSI Document X3.159-1989 American National Standards Institute, inc., 1990 THE C PROGRAMMING LANGUAGE Brian W. Kernighan, and Dennis M. Ritchie Prentice-Hall, Inc., 1978. Controls: ADAPTIVE CONTROL K. Astrom and B. Wittenmark New York, NY: Addison-Welsey Publishing Company, Inc.
REFERENCE BOOKS AND MANUALS Graphics: CGM AND CGI D. B. Arnold and P. R. Bono New York, NY: Springer-Verlag, 1988 COMPUTER GRAPHICS (Second Edition) D. Hearn and M. Pauline Baker Englewood Cliffs, NJ: Prentice-Hall, Inc., 1986 FUNDAMENTALS OF INTERACTIVE COMPUTER GRAPHICS J. D. Foley and A. Van Dam Reading MA: Addison-Wesley Publishing Company Inc., 1984 GEOMETRIC MODELING Michael E. Morteson New York, NY: John Wiley and Sons, Inc. GKS THEORY AND PRACTICE P. R. Bono and I. Herman (Eds.
REFERENCE BOOKS AND MANUALS Image Processing: DIGITAL IMAGE PROCESSING William K. Pratt New York, NY: John Wiley and Sons, 1978 DIGITAL IMAGE PROCESSING (Second Edition) Rafael C. Gonzales and Paul Wintz Reading, MA: Addison-Wesley Publishing Company, Inc., 1977 DIGITAL IMAGE PROCESSING TECHNIQUES M. P. Ekstrom New York, NY: Academic Press, Inc., 1984 DIGITAL PICTURE PROCESSING Azriel Rosenfeld and Avinash C. Kak New York, NY: Academic Press, Inc., 1982 SCIENCE OF FRACTAL IMAGES, THE M. F. Barnsley, R. L.
REFERENCE BOOKS AND MANUALS NUMERICAL RECIPES IN C - THE ART OF SCIENTIFIC PROGRAMMING William H. Press, Brian P. Flannery, Saul A. Teukolsky, and William T. Vetterling Cambridge University Press, 1988 NUMBER THEORY IN SCIENCE AND COMMUNICATION Manfred R. Schroeder New York, NY: Springer-Verlag, 1986 Pattern Recognition: PATTERN CLASSIFICATION AND SCENE ANALYSIS R. O. Duda and P. E.
REFERENCE BOOKS AND MANUALS LINEAR PREDICTION OF SPEECH J. D. Markel and A. H. Gray, Jr. New York, NY: Springer-Verlag, 1976 SPEECH ANALYSIS, SYNTHESIS, AND PERCEPTION J. L. Flanagan New York, NY: Springer-Verlag, 1972 SPEECH COMMUNICATION – HUMAN AND MACHINE D. O’Shaughnessy Reading, MA: Addison-Wesley Publishing Company, Inc., 1987 Telecommunications: DIGITAL COMMUNICATION Edward A. Lee and David G. Messerschmitt Higham, MA: Kluwer Academic Publishers, 1988 DIGITAL COMMUNICATIONS John G.
SECTION 12 ADDITIONAL SUPPORT Motorola ola DSP Audio Codec Routines DTMF Routines Fast Fourier Transforms Filters Floating-Point Routines Functions Lattice Filters Matrix Operations Reed-Solomon Encoder Sorting Routines Speech Standard I/O Equates Tools and Utilities Motorola DSP Product Support DSP56100CLASx Assembler/Simulator C Language Compiler DSP56156ADSx Application Development System MOTOROLA ADDITIONAL SUPPORT Motorola DSP News Motorola Field Application Engineers Design Hotline – 1-800-521-
SECTION CONTENTS 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 12 - 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THIRD PARTY SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOTOROLA DSP PRODUCT SUPPORT . . . . . . . . . . . . . . . . . . . . . SUPPORT INTEGRATED CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . MOTOROLA DSP NEWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTRODUCTION 12.1 INTRODUCTION This section is intended as a guide to the DSP support services and products offered by Motorola. This includes training, development hardware and software tools, telephone support, etc. 12.
MOTOROLA DSP PRODUCT SUPPORT The following is a partial list of the support available for the DSP561xx. Additional information on DSP56100 family members can be obtained through Dr. BuB or the appropriate support telephone service. 12.
MOTOROLA DSP PRODUCT SUPPORT • Modular programming features: local labels, sections, and external definition/reference directives • Nested macro processing capability with support for macro libraries • Complex expression evaluation including boolean operators • Built-in functions for data conversion, string comparison, and common transcendental math functions • Directives to define circular and bit-reversed buffers • Extensive error checking and reporting 12.3.1.
SUPPORT INTEGRATED CIRCUITS 12.3.2.
MOTOROLA DSP NEWS 12.5 MOTOROLA DSP NEWS The Motorola DSP News is a quarterly newsletter providing information on new products, application briefs, questions and answers, DSP product information, third-party product news, etc. This newsletter is free and is available upon request by calling the marketing information phone number listed below. 12.6 MOTOROLA FIELD APPLICATION ENGINEERS Information and assistance for DSP applications is available through the local Motorola field office.
DSP TRAINING COURSES – (602) 897-3665 or (800) 521-6274 12.12 DSP TRAINING COURSES – (602) 897-3665 or (800) 521-6274 Training information on the DSP56100 family members is available by writing: Motorola SPS Training and Technical Operations Mail Drop EL524 P. O. Box 21007 Phoenix, Arizona 85036 or by calling the number above. A technical training catalog is available which describes these courses and gives the current training schedule and prices. 12.13 Dr. BuB ELECTRONIC BULLETIN BOARD Dr.
Dr. BuB ELECTRONIC BULLETIN BOARD 3. If you open a new account, you will be asked to answer some questions such as name, address, phone number, etc. After answering these questions, you will have immediate access to all features of the system including download privilege, electronic mail and participation in discussion groups. 4. You will have an hour of access time for each call (upload and download time doesn’t count against you) and you can call as often as you like.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version Synopsis dtmf.asm 1.0 Main routine used in IIR DTMF dtmf.mem 1.0 Memory for DTMF routine dtmfmstr.asm 1.0 Main routine for multichannel DTMF dtmfmstr.mem 1.0 Memory for multichannel DTMF routine dtmftwo.asm 1.0 10256 ex56.bat 1.0 94 genxd.lod 1.0 Data file 183 genyd.lod 1.0 Data file 180 goertzel.asm 1.0 Goertzel routine 4393 goertzel.lnk 1.0 Link file for Goertzel routine 6954 goertzel.lst 1.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version fftr2dt.asm 1.0 fftr2dt.hlp fftr2e.asm Test program for fftr2d.asm Help for fftr2dt.asm 1.0 fftr2e.hlp fftr2et.asm Synopsis 1.0 fftr2et.hlp Size 1287 614 1024 Point, Non-In-Place, FFT (3.39ms) 8976 Help for fftr2e.asm 5011 Test program for fftr2e.asm 984 Help for fftr2et.asm 408 dct1.asm 1.1 Discrete Cosine Transform using FFT dct1.hlp 1.1 Help file for dct1.asm fftr2cc.asm 1.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version iir2.hlp Synopsis Help for iir2.asm 2286 1311 iir2t.asm 1.0 Test program for iir2.asm iir3.asm 1.0 Direct Form Arbitrary Order All Pole IIR Filter iir3.hlp 2605 1309 1.0 Test program for iir3.asm iir4.asm 1.0 Second Order Direct Canonic IIR Filter (Biquad IIR Filter) 2255 1202 1.0 Test program for iir4.asm iir5.asm 1.0 Second Order Direct Canonic IIR Filter with Scaling (Biquad IIR Filter) 2803 1289 1.0 Test program for iir5.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version fpsub.asm 2.1 Floating point subtract 3072 fpcmp.asm 2.1 Floating point compare 2605 fpmpy.asm 2.0 Floating point multiply 2250 fpmac.asm 2.1 Floating point multiply-accumulate 2712 fpdiv.asm 2.0 Floating point divide 3835 fpsqrt.asm 2.0 Floating point square root 2873 fpneg.asm 2.0 Floating point negate 2026 fpabs.asm 2.0 Floating point absolute value 1953 fpscale.asm 2.0 Floating point scaling 2127 fpfix.asm 2.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version sqrt2.asm 1.0 sqrt2.hlp Synopsis Size Square Root by polynomial approximation, 10 bit accuracy 899 Help for sqrt2.asm 776 sqrt2t.asm 1.0 Test program for sqrt2.asm 1031 sqrt3.asm 1.0 Full precision Square Root Macro 1388 sqrt3.hlp Help for sqrt3.asm 794 sqrt3t.asm 1.0 Test program for sqrt3.asm 1053 tli.asm 1.1 Linear table lookup/interpolation routine for function generation 3253 tli.hlp 1.1 Help for tli.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version 12.13.10 Matrix Operations matmul1.asm 1.0 matmul1.hlp matmul2.asm Synopsis Size [1x3][3x3]=[1x3] Matrix Multiplication 1817 Help for matmul1.asm 1.0 matmul2.hlp General Matrix Multiplication, C=AB Help for matmul2.asm matmul3.asm 1.0 General Matrix Multiply-Accumulate, C=AB+Q matmul3.hlp 1.0 Help for matmul3.asm 12.13.11 Reed-Solomon Encoder readme.rs 1.0 Instructions for Reed-Solomon coding 527 2650 780 2815 865 5200 rscd.asm 1.
Dr. BuB ELECTRONIC BULLETIN BOARD Document ID Version Synopsis Size g722.zip 1.11 G.722 Speech Processing Code (pkzip file for PC) 235864 g722.tar.Z 1.11 G.722 Speech Processing Code (Compressed tar file for Unix) 339297 12.13.14 Standard I/O Equates ioequ16.asm 1.1 DSP56100 Standard I/O Equate File 10329 ioequ.asm 1.1 Motorola Standard I/O Equate File 8774 ioequlc.asm 1.1 Lower Case Version of ioequ.asm 8788 intequ.asm 1.0 Standard Interrupt Equate File 1082 intequlc.asm 1.
REFERENCE BOOKS AND MANUALS Document ID Version Synopsis p5 1.0 “C” code implementation of p4 p6 1.1 Interrupt Driven Dual FIR Filter Flowchart. p7 1.0 “C” code implementation of p6 p8 1.0 Polled I/O Dual FIR Filter Flowchart p9 1.0 “C” code implementation of p8 Size 24806 9535 28489 9656 28525 12.14 REFERENCE BOOKS AND MANUALS A list of DSP-related books is included here as an aid for the engineer who is new to the field of DSP.
REFERENCE BOOKS AND MANUALS HANDBOOK OF DIGITAL SIGNAL PROCESSING D. F. Elliott San Diego, CA: Academic Press, Inc., 1987 INTRODUCTION TO DIGITAL SIGNAL PROCESSING John G. Proakis and Dimitris G. Manolakis New York, NY: Macmillan Publishing Company, 1988 MULTIRATE DIGITAL SIGNAL PROCESSING R. E. Crochiere and L. R. Rabiner Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983 SIGNAL PROCESSING ALGORITHMS S. Stearns and R. Davis Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988 SIGNAL PROCESSING HANDBOOK C.H.
REFERENCE BOOKS AND MANUALS DIGITAL CODING OF WAVEFORMS N. S. Jayant and Peter Noll Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984 DIGITAL FILTERS: ANALYSIS AND DESIGN Andreas Antoniou New York, NY: McGraw-Hill Company, Inc., 1979 DIGITAL FILTERS AND SIGNAL PROCESSING Leland B. Jackson Higham, MA: Kluwer Academic Publishers, 1986 DIGITAL SIGNAL PROCESSING Richard A. Roberts and Clifford T. Mullis New York, NY: Addison-Welsey Publishing Company, Inc.
REFERENCE BOOKS AND MANUALS ADAPTIVE FILTERING PREDICTION & CONTROL G. Goodwin and K. Sin Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984 AUTOMATIC CONTROL SYSTEMS B. C. Kuo Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987 COMPUTER CONTROLLED SYSTEMS: THEORY & DESIGN K. Astrom and B. Wittenmark Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984 DIGITAL CONTROL SYSTEMS B. C. Kuo New York, NY: Holt, Reinholt, and Winston, Inc., 1980 DIGITAL CONTROL SYSTEM ANALYSIS & DESIGN C. Phillips and H.
REFERENCE BOOKS AND MANUALS POSTSCRIPT LANGUAGE PROGRAM DESIGN Glenn C. Reid - Adobe Systems, Inc. Reading MA: Addison-Wesley Publishing Company, Inc., 1988 MICROCOMPUTER DISPLAYS, GRAPHICS, AND ANIMATION Bruce A. Artwick Englewood Cliffs, NJ: Prentice-Hall, Inc., 1985 PRINCIPLES OF INTERACTIVE COMPUTER GRAPHICS William M. Newman and Roger F. Sproull New York, NY: McGraw-Hill Company, Inc., 1979 PROCEDURAL ELEMENTS FOR COMPUTER GRAPHICS David F. Rogers New York, NY: McGraw-Hill Company, Inc.
REFERENCE BOOKS AND MANUALS MOTOROLA DSP ASSEMBLER REFERENCE MANUAL Motorola, Inc., 1992. MOTOROLA DSP SIMULATOR REFERENCE MANUAL Motorola, Inc., 1992. MOTOROLA DSP56000/DSP56001 USER’S MANUAL Motorola, Inc.,1990. MOTOROLA DSP56100 FAMILY MANUAL Motorola, Inc.,1992. MOTOROLA DSP56156 USER’S MANUAL Motorola, Inc.,1992. MOTOROLA DSP56166 USER’S MANUAL Motorola, Inc.,1992. MOTOROLA DSP96002 USER’S MANUAL Motorola, Inc.,1989. 12.14.8 Numerical Methods ALGORITHMS (THE CONSTRUCTION, PROOF, PROGRAMS) P.
REFERENCE BOOKS AND MANUALS CLASSIFICATION ALGORITHMS Mike James New York, NY: Wiley-Interscience, 1985 Spectral Analysis: STATISTICAL SPECTRAL ANALYSIS, A NONPROBABILISTIC THEORY William A. Gardner Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988 THE FAST FOURIER TRANSFORM AND ITS APPLICATIONS E. Oran Brigham Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988 THE FAST FOURIER TRANSFORM AND ITS APPLICATIONS R. N. Bracewell New York, NY: McGraw-Hill Company, Inc., 1986 12.14.
REFERENCE BOOKS AND MANUALS DIGITAL COMMUNICATIONS John G. Proakis New York, NY: McGraw-Hill Publishing Co.
APPENDIX A INSTRUCTION SET DETAILS • Arithmetic MAC(su,uu) • Bit Field Manipulation • Program Control ABS NEG ADC NEGC ADD NORM ASL RND ASL4 SBC ASR SUB ASR4 SUBL ASR16 SWAP Tcc DOLoop Jcc CLR TFR DO FOREVER JMP CLR24 TFR2 JSR CMP ENDDO TST JScc CMPM BRKcc DEC TST2 DEC24 DIV ZERO • Logical BFTSTL Bcc BFTSTH BSR BFCLR BRA BFSET BScc BFCHG DEBUG • Loop • Move LEA MOVE DMAC AND MOVE(C) EXT ANDI MOVE(I) IMAC EOR MOVE(M) IMPY LSL MOVE(P) INC LSR
SECTION CONTENTS SECTION A.1 APPENDIX A INTRODUCTION .................................................3 SECTION A.2 INSTRUCTION GUIDE ..............................................................3 SECTION A.3 NOTATION .................................................................................4 SECTION A.4 ADDRESSING MODES .............................................................10 A.4.1 Addressing Mode Modifiers ................................................................13 SECTION A.
APPENDIX A INTRODUCTION A.1 APPENDIX A INTRODUCTION This appendix contains detailed information about each instruction in the DSP56K instruction set. It presents an instruction guide to help the user understand the individual instruction descriptions and follows with sections on notation and addressing modes. The instructions are then discussed in alphabetical order. A.
NOTATION word is optional, it is so indicated. The values which can be assumed by each of the variables in the various instruction fields are shown under the instruction field’s heading. Note that the symbols used in decoding the various opcode fields of an instruction are completely arbitrary. Furthermore, the opcode symbols used in one instruction are completely independent of the opcode symbols used in a different instruction. 7.
NOTATION Table A-1 Instruction Description Notation Data ALU Registers Operands Xn Input Register X1 or X0 (24 Bits) Yn Input Register Y1 or Y0 (24 Bits) An Accumulator Registers A2, A1, A0 (A2 — 8 Bits, A1 and A0 — 24 Bits) Bn Accumulator Registers B2, B1, B0 (B2 — 8 Bits, B1 and B0 — 24 Bits) X Input Register X = X1: X0 (48 Bits) Y Input Register Y = Y1: Y0 (48 Bits) A Accumulator A = A2: A1: A0 (56 Bits)* B Accumulator B = B2: B1: B0 (56 BIts)* AB Accumulators A and B = A1: B1 (48 Bits)
NOTATION Table A-1 Instruction Description Notation (Continued) Program Control Unit Registers Operands PC Program Counter Register (16 Bits) MR Mode Register (8 Bits) CCR Condition Code Register (8 Bits) SR Status Register = MR:CCR (16 Bits) OMR Operating Mode Register (8 Bits) LA Hardware Loop Address Register (16 Bits) LC Hardware Loop Counter Register (16 Bits) SP System Stack Pointer Register (6 Bits) SSH Upper Portion of the Current Top of the Stack (16 Bits) SSL Lower Portion of t
NOTATION Table A-1 Instruction Description Notation (Continued) Miscellaneous Operands S, Sn Source Operand Register D, Dn Destination Operand Register D [n] Bit n of D Destination Operand Register #n Immediate Short Data (5 Bits) #xx Immediate Short Data (8 Bits) #xxx Immediate Short Data (12 Bits) #xxxxxx Immediate Data (24 Bits) Unary Operators - Negation Operator — Logical NOT Operator (Overbar) PUSH Push Specified Value onto the System Stack (SS) Operator PULL Pull Specified Value
NOTATION Table A-1 Instruction Description Notation (Continued) Addressing Mode Operators << I/O Short Addressing Mode Force Operator < Short Addressing Mode Force Operator > Long Addressing Mode Force Operator # Immediate Addressing Mode Operator #> Immediate Long Addressing Mode Force Operator #< Immediate Short Addressing Mode Force Operator Mode Register (MR) Symbols DM Double Precision Multiply Bit Indicating if the Chip is in Double Precision Multiply Mode LF Loop Flag Bit Indicating W
NOTATION Table A-1 Instruction Description Notation (Continued) Instruction Timing Symbols aio Time Required to Access an I/O Operand ap Time Required to Access a P Memory Operand ax Time Required to Access an X Memory Operand ay Time Required to Access a Y Memory Operand axy Time Required to Access XY Memory Operands ea Time or Number of Words Required for an Effective Address jx Time Required to Execute Part of a Jump-Type Instruction mv Time or Number of Words Required for a Move-Type Ope
ADDRESSING MODES A.4 ADDRESSING MODES The addressing modes are grouped into three categories: register direct, address register indirect, and special. These addressing modes are summarized in Table A-2. All address calculations are performed in the address ALU to minimize execution time and loop overhead. Addressing modes, which specify whether the operands are in registers, in memory, or in the instruction itself (such as immediate data), provide the specific address of the operands.
ADDRESSING MODES Table A-2 DSP56K Addressing Modes Addressing Mode Uses Mn Modifier Operand Reference S C D A P X Y L XY Register Direct Data or Control Register No X X X Address Register Rn No X Address Modifier Register Mn No X Address Offset Register Nn No X Address Register Indirect No Update No X X X X X Postincrement by 1 Yes X X X X X Postdecrement by 1 Yes X X X X X Postincrement by Offset Nn Yes X X X X X Postdecrement by Offset Nn Yes X X
ADDRESSING MODES Table A-3 DSP56K Addressing Mode Encoding Addressing Mode Mode MMM Reg RRR Addressing Categories U P M A Assembler Syntax Register Direct Data or Control Register — — X (See Table A-1) Address Register — — X Rn Address Offset Register — — X Nn Address Modifier Register — — X Mn Address Register Indirect No Update 100 Rn X X X (Rn) Postincrement by 1 011 Rn X X X X (Rn) + Postdecrement by 1 010 Rn X X X X (Rn) - Postincrement by Offset Nn
ADDRESSING MODES The address register indirect addressing modes require that the offset register number be the same as the address register number. The assembler syntax “N” may be used instead of “Nn” in the address register indirect memory addressing modes. If “N” is specified, the offset register number is the same as the address register number. A.4.1 Addressing Mode Modifiers The addressing mode selected in the instruction word is further specified by the contents of the address modifier register Mn.
ADDRESSING MODES Table A-4 Addressing Mode Modifier Summary A - 14 Binary M0-M7 Hex M0-M7 Addressing Mode Arithmetic 0000 0000 0000 0000 0000 Reverse Carry (Bit Reverse) 0000 0000 0000 0001 0001 Modulo 2 00000000 0000 0010 0002 Modulo 3 : : : 0111 1111 1111 1110 7FFE Modulo 32767 0111 1111 1111 1111 7FFF Modulo 32768 1000 0000 0000 0000 8000 Reserved 1000 0000 0000 0001 8001 Multiple Wrap-Around Modulo 2 1000 0000 0000 0010 8002 Reserved 1000 0000 0000 0011 8003 Multiple W
CONDITION CODE COMPUTATION A.
CONDITION CODE COMPUTATION S (Scaling Bit) The scaling bit (S) is used to detect data growth, which is required in Block Floating Point FFT operation. Typically, the bit is tested after each pass of a radix 2 decimation-in-time FFT and, if it is set, the appropriate scaling mode should be activated in the next pass.
CONDITION CODE COMPUTATION S1 S0 Scaling Mode Signed Integer Portion 0 0 1 0 1 0 No Scaling Scale Down Scale Up Bits 55, 54, . . . . 48, 47 Bits 55, 54, . . . . 49, 48 Bits 55, 54, . . . . 47, 46 Note that the signed integer portion of an accumulator IS NOT necessarily the same as the extension register portion of that accumulator. The signed integer portion of an accumulator consists of the MS 8, 9, or 10 bits of that accumulator, depending on the scaling mode being used.
CONDITION CODE COMPUTATION C (Carry Bit) Set if a carry is generated out of the MS bit of the A or B result of an addition or if a borrow is generated out of the MS bit of the A or B result of a subtraction. The carry or borrow is generated out of bit 55 of the A or B result. Cleared otherwise. Table A-5 shows how each condition code bit is affected by each instruction. Exceptions to the standard definitions given above are indicated by a number or a “?”.
CONDITION CODE COMPUTATION Table A-5 Condition Code Computations for Instructions (No Parallel Move) Mnemonic S L E U N Z V S L E U N Z V C ABS — 1 9 1 11 LUA — — — — — — — — MAC — ✓ ✓ ✓ ✓ — — ✓ ✓ ADDR — ✓ — ✓ ✓ ✓ ✓ 2 ✓ ✓ ✓ — ADDL ✓ ✓ ✓ ✓ ✓ — — ✓ ✓ ✓ ✓ ✓ — — ✓ ✓ ✓ ✓ ✓ — ADD ✓ ✓ ✓ ✓ ✓ LSR ADC ✓ ✓ ✓ ✓ ✓ C Notes — — — — AND — — — — 8 9 1 — ANDI ? ? ? ? ? ? ? ? ASL — 4 MOVEP — ✓ ✓ ✓ ✓ ✓ — ✓ ✓ ✓ ✓ 2 ASR 1 5 MPY BCHG ? ?
PARALLEL MOVE DESCRIPTIONS 1. The bit is cleared. 2. V — Set if an arithmetic overflow occurs in the 56-bit A or B result or if the MS bit of the destination operand is changed as a result of the left shift. Cleared otherwise. 3. For destination operand CCR, the bits are cleared if the corresponding bits in the immediate data are cleared. Otherwise they are not affected. For other destination operands, the bits are not affected. 4.
INSTRUCTION DESCRIPTIONS A.7 INSTRUCTION DESCRIPTIONS The following section describes each instruction in the DSP56K instruction set in complete detail. The format of each instruction description is given in Section A.2. Instructions which allow parallel moves include the notation “(parallel move)” in both the Assembler Syntax and the Operation fields.
INSTRUCTION DESCRIPTIONS ABS ABS Absolute Value Operation: | D | ➞ D (parallel move) Assembler Syntax: ABS D (parallel move) Description: Take the absolute value of the destination operand D and store the result in the destination accumulator. Example: : A1 : ABS #$123456,X0 A,Y0 ;take abs.
INSTRUCTION DESCRIPTIONS ABS ABS Absolute Value Instruction Format: ABS D Opcode: 23 8 DATA BUS MOVE FIELD 7 4 0 0 1 0 3 0 d 1 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Dd A0 B1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 23
INSTRUCTION DESCRIPTIONS ADC ADC Add Long with Carry Operation: S+C+D ➞ D (parallel move) Assembler Syntax: ADC S,D (parallel move) Description: Add the source operand S and the carry bit C of the condition code register to the destination operand D and store the result in the destination accumulator. Long words (48 bits) may be added to the (56-bit) destination accumulator.
INSTRUCTION DESCRIPTIONS ADC ADC Add Long with Carry result. The actual 96-bit result is stored in memory using the A10 and B10 operands (instead of A and B) because shifting and limiting is not desired. Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS ADD ADD Add Operation: S+D➞D (parallel move Assembler Syntax: ADD S,D (parallel move) Description: Add the source operand S to the destination operand D and store the result in the destination accumulator. Words (24 bits), long words (48 bits), and accumulators (56 bits) may be added to the destination accumulator.
INSTRUCTION DESCRIPTIONS ADD ADD Add Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS ADDL Shift Left and Add Accumulators Operation: S+2∗D➞D (parallel move) ADDL Assembler Syntax: ADDL S,D (parallel move) Description: Add the source operand S to two times the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the left, and a zero is shifted into the LS bit of D prior to the addition operation.
INSTRUCTION DESCRIPTIONS ADDL ADDL Shift Left and Add Accumulators Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS ADDR Shift Right and Add Accumulators Operation: S+D / 2➞D (parallel move) ADDR Assembler Syntax: ADDR S,D (parallel move) Description: Add the source operand S to one-half the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the right while the MS bit of D is held constant prior to the addition operation.
INSTRUCTION DESCRIPTIONS ADDR ADDR Shift Right and Add Accumulators Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS AND AND Logical AND Operation: S • D[47:24]➞D[47:24] (parallel move) where •denotes the logical AND operator Assembler Syntax: AND S,D (parallel move) Description: Logically AND the source operand S with bits 47–24 of the destination operand D and store the result in bits 47–24 of the destination accumulator. This instruction is a 24-bit operation. The remaining bits of the destination operand D are not affected.
INSTRUCTION DESCRIPTIONS AND AND Logical AND Instruction Format: AND S,D Opcode: 23 8 7 DATA BUS MOVE FIELD 4 0 1 J J 3 d 0 1 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S JJ X0 X1 Y0 Y1 00 10 01 11 Dd A 0 (only A1 is changed) B 1 (only B1 is changed) Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 33
INSTRUCTION DESCRIPTIONS ANDI AND Immediate with Control Register ANDI Operation: Assembler Syntax: #xx • D➞D AND(I) #xx,D where • denotes the logical AND operator Description: Logically AND the 8-bit immediate operand (#xx) with the contents of the destination control register D and store the result in the destination control register. The condition codes are affected only when the condition code register (CCR) is specified as the destination operand.
INSTRUCTION DESCRIPTIONS ANDI ANDI AND Immediate with Control Register Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR For CCR Operand: S — Cleared if bit 7 of the immediate operand is cleared L — Cleared if bit 6 of the immediate operand is cleared E — Cleared if bit 5 of the immediate operand is cleared U — Cleared if bit 4 of the immediate operand is cleared N — Cleared if bit 3 of the immediate operand is cleared
INSTRUCTION DESCRIPTIONS ASL ASL Arithmetic Shift Accumulator Left 55 Operation: 47 23 0 C 0 (parallel move) Assembler Syntax: ASL D (parallel move) Description: Arithmetically shift the destination operand D one bit to the left and store the result in the destination accumulator. The MS bit of D prior to instruction execution is shifted into the carry bit C and a zero is shifted into the LS bit of the destination accumulator D. If a zero shift count is specified, the carry bit is cleared.
INSTRUCTION DESCRIPTIONS ASL ASL Arithmetic Shift Accumulator Left Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS ASR ASR Arithmetic Shift Accumulator Right 55 47 23 0 Operation: C (parallel move) Assembler Syntax: ASR D (parallel move) Description: Arithmetically shift the destination operand D one bit to the right and store the result in the destination accumulator. The LS bit of D prior to instruction execution is shifted into the carry bit C, and the MS bit of D is held constant.
INSTRUCTION DESCRIPTIONS ASR ASR Arithmetic Shift Accumulator Right Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Operation: D[n] ➞ C; D[n] ➞ D[n] Assembler Syntax: BCHG #n,X:ea D[n] ➞ C; D[n] ➞ D[n] BCHG #n,X:aa D[n] ➞ C; D[n] ➞ D[n] BCHG #n,X:pp D[n] ➞ C; D[n] ➞ D[n] BCHG #n,Y:ea D[n] ➞ C; D[n] ➞ D[n] BCHG #n,Y:aa D[n] ➞ C; D[n] ➞ D[n] BCHG #n,Y:pp D[n] ➞ C; D[n] ➞ D[n] BCHG #n,D Description: Test the nth bit of the destination operand D, complement it, and store the result in the destination location.
INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Explanation of Example: Prior to execution, the 24-bit X location X:$FFE2 (I/O port B data direction register) contains the value $000000. The execution of the BCHG #$7,X:<<$FFE2 instruction tests the state of the 7th bit in X:$FFE2, sets the carry bit C accordingly, and then complements the 7th bit in X:$FFE2.
INSTRUCTION DESCRIPTIONS BCHG Bit Test and Change BCHG For other destination operands: S — Not affected L — Not affected E — Not affected U — Not affected N — Not affected Z — Not affected V — Not affected C — Set if bit tested is set. Cleared otherwise. MR Status Bits: For destination operand SR: I0 — Changed if bit 8 is specified. Not affected otherwise. I1 — Changed if bit 9 is specified. Not affected otherwise. S0 — Changed if bit 10 is specified. Not affected otherwise.
INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Instruction Format: BCHG #n,X:ea BCHG #n,Y:ea Opcode: 23 0 0 0 0 1 0 1 16 15 1 0 8 1 M M M R R 7 R 0 0 S 0 b b b b b OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address 0 0 0 0 1 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 r r r r r r
INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Instruction Format: BCHG #n,X:aa BCHG #n,Y:aa Opcode: 23 0 16 15 0 0 0 1 0 1 1 0 8 0 a a a a a a 7 0 0 S 0 b b b b b Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 44 INSTRUCTION SET DETAILS MOTOROLA
INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Instruction Format: BCHG #n,X:pp BCHG #n,Y:pp Opcode: 23 0 16 15 0 0 0 1 0 1 1 1 8 0 p p p p p p 7 0 0 S 0 b b b b b Instruction Fields: #n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 45
INSTRUCTION DESCRIPTIONS BCHG BCHG Bit Test and Change Instruction Format: BCHG #n,D Opcode: 23 0 16 15 0 0 0 1 0 1 1 1 1 D D D D D 8 7 D 0 0 1 0 b b b b b Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address in extension word Destination Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier registers in AGU 8 program controller regis
INSTRUCTION DESCRIPTIONS BCHG Bit Test and Change BCHG Notes: If A or B is specified as the destination operand, the following sequence of events takes place: 1. The S bit is computed according to its definition (See Section A.5) 2. The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR). 3. If the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the L bit is set. 4.
INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Operation: D[n] ➞ C; 0 ➞ D[n] Assembler Syntax: BCLR #n,X:ea D[n] ➞ C; 0 ➞ D[n] BCLR #n,X:aa D[n] ➞ C; 0 ➞ D[n] BCLR #n,X:pp D[n] ➞ C; 0 ➞ D[n] BCLR #n,Y:ea D[n] ➞ C; 0 ➞ D[n] BCLR #n,Y:aa D[n] ➞ C; 0 ➞ D[n] BCLR #n,Y:pp D[n] ➞ C; 0 ➞ D[n] BCLR #n,D Description: Test the nth bit of the destination operand D, clear it and store the result in the destination location.
INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Explanation of Example: Prior to execution, the 24-bit X location X:$FFE4 (I/O port B data register) contains the value $FFFFFF. The execution of the BCLR #$E,X:<<$FFE4 instruction tests the state of the 14th bit in X:$FFE4, sets the carry bit C accordingly, and then clears the 14th bit in X:$FFE4.
INSTRUCTION DESCRIPTIONS BCLR Bit Test and Clear BCLR For other destination operands: C — Set if bit tested is set. Cleared otherwise. V — Not affected Z — Not affected N — Not affected U — Not affected E — Not affected L — Not affected S — Not affected MR Status Bits: For destination operand SR: I0 — Cleared if bit 8 is specified. Not affected otherwise. I1 — Cleared if bit 9 is specified. Not affected otherwise. S0 — Cleared if bit 10 is specified. Not affected otherwise.
INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Instruction Format: BCLR #n,X:ea BCLR #n,Y:ea Opcode: 23 0 0 0 0 1 0 1 16 15 0 0 8 1 M M M R R 7 R 0 0 S 0 b b b b b OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address 0 0 0 0 1 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 r r r r r r r
INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Instruction Format: BCLR #n,X:aa BCLR #n,Y:aa Opcode: 23 0 16 15 0 0 0 1 0 1 0 0 8 0 a a a a a a 7 0 0 S 0 b b b b b Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 52 INSTRUCTION SET DETAILS MOTOROLA
INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Instruction Format: BCLR #n,X:pp BCLR #n,Y:pp Opcode: 23 0 16 15 0 0 0 1 0 1 0 1 8 0 p p p p p p 7 0 0 S 0 b b b b b Instruction Fields: #n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 53
INSTRUCTION DESCRIPTIONS BCLR BCLR Bit Test and Clear Instruction Format: BCLR #n,D Opcode: 23 0 16 15 0 0 0 1 0 1 0 1 8 1 D D D D D D 7 0 0 1 0 b b b b b Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address in extension word Destination Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier registers in AGU 8 program controller register
INSTRUCTION DESCRIPTIONS BCLR Bit Test and Clear BCLR Notes: If A or B is specified as the destination operand, the following sequence of events takes place: 1. The S bit is computed according to its definition (See Section A.5) 2. The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR). 3. If the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the L bit is set. 4.
INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Operation: D[n] ➞ C; 1 ➞ D[n] Assembler Syntax: BSET #n,X:ea D[n] ➞ C; 1 ➞ D[n] BSET #n,X:aa D[n] ➞ C; 1 ➞ D[n] BSET #n,X:pp D[n] ➞ C; 1 ➞ D[n] BSET #n,Y:ea D[n] ➞ C; 1 ➞ D[n] BSET #n,Y:aa D[n] ➞ C; 1 ➞ D[n] BSET #n,Y:pp D[n] ➞ C; 1 ➞ D[n] BSET #n,D Description: Test the nth bit of the destination operand D, set it, and store the result in the destination location.
INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Explanation of Example: Prior to execution, the 24-bit X location X:$FFE5 (I/O port C data register) contains the value $000000. The execution of the BSET #$0,X:<<$FFE5 instruction tests the state of the 0th bit in X:$FFE5, sets the carry bit C accordingly, and then sets the 0th bit in X:$FFE5.
INSTRUCTION DESCRIPTIONS BSET Bit Test and Set For other destination operands: C — Set if bit tested is set. Cleared otherwise. V — Not affected Z — Not affected N — Not affected U — Not affected E — Not affected L — Not affected S — Not affected MR Status Bits: For destination operand SR: I0 — Set if bit 8 is specified. Not affected otherwise. I1 — Set if bit 9 is specified. Not affected otherwise. S0 — Set if bit 10 is specified. Not affected otherwise. S1 — Set if bit 11 is specified.
INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Instruction Format: BSET #n,X:ea BSET #n,Y:ea Opcode: 23 0 0 0 0 1 0 1 16 15 0 0 8 1 M M M R R 7 R 0 0 S 1 b b b b b OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address 0 0 0 0 1 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 r r r r r r r 0 r r
INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Instruction Format: BSET #n,X:aa BSET #n,Y:aa Opcode: 23 0 16 15 0 0 0 1 0 1 0 0 8 0 a a a a a a 7 0 0 S 1 b b b b b Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 60 INSTRUCTION SET DETAILS MOTOROLA
INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Instruction Format: BSET #n,X:pp BSET #n,Y:pp Opcode: 23 0 16 15 0 0 0 1 0 1 0 1 8 0 p p p p p p 7 0 0 S 1 b b b b b Instruction Fields: #n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 61
INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Instruction Format: BSET #n,D Opcode: 23 0 16 15 0 0 0 1 0 1 0 1 8 1 D D D D D D 7 0 0 1 1 b b b b b Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address in extension word Destination Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier registers in AGU 8 program controller registers 0 0 0
INSTRUCTION DESCRIPTIONS BSET Bit Test and Set Notes: If A or B is specified as the destination operand, the following sequence of events takes place: 1. The S bit is computed according to its definition (See Section A.5) 2. The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR). 3. If the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the L bit is set. 4.
INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Operation: D[n] ➞ C; Assembler Syntax: BTST #n,X:ea D[n] ➞ C; BTST #n,X:aa D[n] ➞ C; BTST #n,X:pp D[n] ➞ C; BTST #n,Y:ea D[n] ➞ C; BTST #n,Y:aa D[n] ➞ C; BTST #n,Y:pp BTST #n,D D[n] ➞ C; th Description: Test the n bit of the destination operand D. The state of the nth bit is stored in the carry bit C of the condition code register. The bit to be tested is selected by an immediate bit number from 0–23.
INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR CCR Condition Codes: For destination operand A or B: C — Set if bit tested is set. Cleared otherwise. V — Not affected Z — Not affected N — Not affected U — Not affected E — Not affected L — Set if data limiting has occurred. See Notes on page A-69. S — Computed according to the definition. See Notes on page A-69.
INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Instruction Format: BTST #n,X:ea BTST #n,Y:ea Opcode: 23 0 0 0 0 1 0 1 16 15 1 0 8 1 M M M R R 7 R 0 0 S 1 b b b b b OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address 0 0 0 0 1 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 r r r r r r r 0 r r r
INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Instruction Format: BTST #n,X:aa BTST #n,Y:aa Opcode: 23 0 16 15 0 0 0 1 0 1 1 0 8 0 a a a a a a 7 0 0 S 1 b b b b b Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 67
INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Instruction Format: BTST #n,X:pp BTST #n,Y:pp Opcode: 23 0 16 15 0 0 0 1 0 1 1 1 8 0 p p p p p p 7 0 0 S 1 b b b b b Instruction Fields: #n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 68 INSTRUCTION SET DETAILS MOTOROLA
INSTRUCTION DESCRIPTIONS BTST BTST Bit Test Instruction Format: BTST #n,D Opcode: 23 0 16 15 0 0 0 1 0 1 1 1 8 1 D D D D D D 7 0 0 1 1 b b b b b Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD, xxxx=16-bit Absolute Address in extension word Destination Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier registers in AGU 8 program controller registers 0 0 0
INSTRUCTION DESCRIPTIONS CLR CLR Clear Accumulator Operation: 0 ➞D (parallel move) Assembler Syntax: CLR D (parallel move) Description: Clear the destination accumulator. This is a 56-bit clear instruction. Example: : CLR A : #$7F,N ;clear A, set up N0 addr. reg. Before Execution After Execution A $12:345678:9ABCDE A $00:000000:000000 Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $12:345678:9ABCDE.
INSTRUCTION DESCRIPTIONS CLR CLR Clear Accumulator Instruction Format: CLR D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 0 1 3 d 0 0 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: D d A B 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 71
INSTRUCTION DESCRIPTIONS CMP CMP Compare Operation: S2 – S1(parallel move) Assembler Syntax: CMP S1, S2 (parallel move) Description: Subtract the source one operand, S1, from the source two accumulator, S2, and update the condition code register. The result of the subtraction operation is not stored. Note: This instruction subtracts 56-bit operands. When a word is specified as S1, it is sign extended and zero filled to form a valid 56-bit operand.
INSTRUCTION DESCRIPTIONS CMP CMP Compare Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS CMPM CMPM Compare Magnitude Operation: |S2| – |S1|(parallel move) Assembler Syntax: CMPM S1, S2 (parallel move) Description: Subtract the absolute value (magnitude) of the source one operand, S1, from the absolute value of the source two accumulator, S2, and update the condition code register. The result of the subtraction operation is not stored. Note: This instruction subtracts 56-bit operands.
INSTRUCTION DESCRIPTIONS CMPM CMPM Compare Magnitude Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS DEBUG DEBUG Enter Debug Mode Operation: Assembler Syntax: Enter the debug mode DEBUG Description: Enter the debug mode and wait for OnCE commands. Example: : DEBUG ;enter the debug mode : Explanation of Example: Upon executing the DEBUG instruction, the chip enters the debug mode after the instruction following the DEBUG instruction has entered the instruction latch. Entering the debug mode is acknowledged by the chip by pulsing low the DSO line.
INSTRUCTION DESCRIPTIONS DEBUG DEBUG Enter Debug Mode Opcode: 23 0 16 15 0 0 0 0 0 0 0 0 8 0 0 0 0 0 1 0 7 0 0 0 0 0 0 0 0 0 Timing: 4 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 77
INSTRUCTION DESCRIPTIONS DEBUGcc DEBUGcc Enter Debug Mode Conditionally Operation: Assembler Syntax: If cc, then enter the debug mode DEBUGcc Description: If the specified condition is true, enter the debug mode and wait for OnCE commands. If the specified condition is false, continue with the next instruction.
INSTRUCTION DESCRIPTIONS DEBUGcc DEBUGcc Enter Debug Mode Conditionally Example: : CMP Y0, DEBUGge B ; Compare register Y0 with the B accumulator. ; Enter the debug mode if ; the previous test result is “greater than”. : Explanation of Example: The results of the comparison between Y0 and B will be recorded in the status register bits.
INSTRUCTION DESCRIPTIONS DEC DEC Decrement by One Operation: D–1 ➞ D Assembler Syntax: DEC D Description: Decrement by one the specified operand and store the result in the destination accumulator. One is subtracted from the LSB of D. Example: : DEC A ;Decrement the content of A accumulator by one : Explanation of Example: One is subtracted from the content of the A accumulator.
INSTRUCTION DESCRIPTIONS DEC DEC Decrement by One Instruction Format: DEC D Opcode: 23 0 16 15 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 7 0 0 0 0 0 1 0 1 d Instruction Fields: D d A B 0 1 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 81
INSTRUCTION DESCRIPTIONS DIV Operation: DIV Divide Interation If D[55]⊕S[23]=1, 55 47 23 0 then C+S D C–S D Destination Accumulator D 55 47 23 0 else Destination Accumulator D where ⊕ denotes the logical exclusive OR operator Assembler Syntax: DIV S,D Description: Divide the destination operand D by the source operand S and store the result in the destination accumulator D.
INSTRUCTION DESCRIPTIONS DIV Divide Interation DIV The DIV instruction calculates one quotient bit based on the divisor and the previous partial remainder. To produce an N-bit quotient, the DIV instruction is executed N times where N is the number of bits of precision desired in the quotient, 1≤N≤24. Thus, for a full-precision (24 bit) quotient, 24 DIV iterations are required.
INSTRUCTION DESCRIPTIONS DIV DIV Divide Interation Example: (4-Quadrant division, 24-bit signed quotient, 48-bit signed remainder) ABS A A,B ;make dividend positive, copy A1 to B1 EOR X0,B B,X:$0 ;save rem. sign in X:$0, quo.
INSTRUCTION DESCRIPTIONS DIV Divide Interation DIV Note that the divide routine used in the previous example assumes that the signextended 56-bit signed fractional dividend is stored in the A accumulator and that the 24bit signed fractional divisor is stored in the X0 register. This routine produces a full 24-bit signed quotient and a 48-bit signed remainder.
INSTRUCTION DESCRIPTIONS DIV DIV Divide Interation A complete discussion of the various division routines is beyond the scope of this manual. For a more complete discussion of these routines, refer to the application note entitled Fractional and Integer Arithmetic Using the DSP56001. For extended precision division (i.e., for N-bit quotients where N>24), the DIV instruction is no longer applicable, and a user-defined N-bit division routine is required.
INSTRUCTION DESCRIPTIONS DIV DIV Divide Interation Instruction Format: DIV S,D Opcode: 23 0 16 15 0 0 0 0 0 Instruction Fields: S,D JJd X0,A X0,B Y0,A Y0,B 000 001 010 011 0 1 1 8 0 0 S,D JJd X1,A X1,B Y1,A Y1,B 100 101 110 111 0 0 0 0 0 7 0 0 1 J J d 0 0 0 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 87
INSTRUCTION DESCRIPTIONS DO DO Start Hardware Loop Operation: Assembler Syntax: SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;X:ea ➞ LC DO X:ea,expr SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA 1 ➞ LF SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;X:aa ➞ LC SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA 1 ➞ LF DO X:aa,expr SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;Y:ea ➞ LC SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA 1 ➞ LF DO Y:ea,expr SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;Y:aa ➞ LC SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA 1 ➞ LF DO Y:aa,expr SP+1 ➞ SP;LA ➞ SSH;LC ➞
INSTRUCTION DESCRIPTIONS DO Start Hardware Loop DO executed 65,536 times. All address register indirect addressing modes may be used to generate the effective address of the source operand. If immediate short data is specified, the 12 LS bits of LC are loaded with the 12-bit immediate value, and the four MS bits of LC are cleared. During the second instruction cycle, the current contents of the program counter (PC) register and the status register (SR) are pushed onto the system stack.
INSTRUCTION DESCRIPTIONS DO Start Hardware Loop DO ing the last instruction in the DO loop. Note that LF is the only bit in the status register (SR) that is restored after a hardware DO loop has been exited. Note: The loop flag (LF) is cleared by a hardware reset. Restrictions: The “end-of-loop” comparison previously described actually occurs at instruction fetch time. That is, LA is being compared with PC when the instruction at LA– 2 is being executed.
INSTRUCTION DESCRIPTIONS DO At LA DO Start Hardware Loop any two-word instruction* Jcc JCLR JSET JMP JScc JSR REP RESET RTI RTS STOP WAIT *This restriction applies to the situation in which the DSP56K simulator’s single-line assembler is used to change the last instruction in a DO loop from a oneword instruction to a two-word instruction.
INSTRUCTION DESCRIPTIONS DO DO Start Hardware Loop Example: : DO #cnt1, END1 : DO #cnt2, END2 : : MOVE A,X:(R0)+ : ;begin outer DO loop ;begin inner DO loop END2 END1 ;last instruction in inner loop ;(in outer loop) ;last instruction in outer loop ;first instruction after outer loop ADD A,B X:(R1)+,X0 : : Explanation of Example: This example illustrates a nested DO loop. The outer DO loop will be executed “cnt1” times while the inner DO loop will be executed (“cnt1” * “cnt2”) times.
INSTRUCTION DESCRIPTIONS DO DO Start Hardware Loop Instruction Format: DO X:ea, expr DO Y:ea, expr Opcode: 23 0 0 0 20 19 0 0 16 15 1 1 0 0 8 1 M M M R R R 7 0 0 S 0 0 0 0 0 0 ABSOLUTE ADDRESS EXTENSION Instruction Fields: ea=6-bit Effective Address=MMMRRR, expr=16-bit Absolute Address in 24-bit extension word Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) 0 0 0 0 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 0 1 0 1 0 1 1 r r r r
INSTRUCTION DESCRIPTIONS DO DO Start Hardware Loop Instruction Format: DO X:aa, expr DO Y:aa, expr Opcode: 23 0 0 0 20 19 0 0 16 15 1 1 0 0 8 0 a a a a a a 7 0 0 S 0 0 0 0 0 0 ABSOLUTE ADDRESS EXTENSION Instruction Fields: ea=6-bit Effective Short Address=aaaaaa, expr=16-bit Absolute Address in 24-bit extension word Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory • • 0 1 111111 Timing: 6+mv oscillator clock cycles Memory: 2 program words A - 94 INSTR
INSTRUCTION DESCRIPTIONS DO DO Start Hardware Loop Instruction Format: DO #xxx, expr Opcode: 23 0 0 0 20 19 0 0 16 15 1 1 0 i 8 i i i i i i i 7 1 0 0 0 0 h h h h ABSOLUTE ADDRESS EXTENSION Instruction Fields: #xxx=12-bit Immediate Short Data = hhhhiiiiiiii, expr=16-bit Absolute Address in 24-bit extension word Immediate Short Data hhhh i i i i i i i i 000000000000 • • 111111111111 Timing: 6+mv oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS
INSTRUCTION DESCRIPTIONS DO DO Start Hardware Loop Instruction Format: DO S, expr Opcode: 23 0 0 0 20 19 0 0 16 15 1 1 0 1 8 1 D D D D D D 7 D 0 0 0 0 0 0 0 0 ABSOLUTE ADDRESS EXTENSION Instruction Fields: S=6-bit Source operand = DDDDDD, expr=16-bit Absolute Address in 24-bit extension word Source D D D D D D X0 0 0 0 1 0 X1 0 0 0 1 0 Y0 0 0 0 1 1 Y1 0 0 0 1 1 A0 0 0 1 0 0 B0 0 0 1 0 0 A2 0 0 1 0 1 B2 0 0 1 1 0 A1 0 0 1 1 0 A 0 0 1 1 1 B 0 0 1 1 1 where rrr=Rn register wher
INSTRUCTION DESCRIPTIONS DO Start Hardware Loop DO Notes: If A or B is specified as the destination operand, the following sequence of events takes place: 1. The S bit is computed according to its definition (See Section A.5) 2. The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR). 3. If the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the L bit is set. 4.
INSTRUCTION DESCRIPTIONS ENDDO End Current DO Loop Operation: SSL(LF) ➞ SR;SP – 1➞ SP SSH ➞ LA; SSL ➞ LC;SP –1 ➞ SP ENDDO Assembler Syntax: ENDDO Description: Terminate the current hardware DO loop before the current loop counter (LC) equals one. If the value of the current DO loop counter (LC) is needed, it must be read before the execution of the ENDDO instruction.
INSTRUCTION DESCRIPTIONS ENDDO ENDDO End Current DO Loop Explanation of Example: This example illustrates the use of the ENDDO instruction to terminate the current DO loop. The value of the loop counter (LC) is compared with the value in the Y1 register to determine if execution of the DO loop should continue. Note that the ENDDO instruction updates certain program controller registers but does not automatically jump past the end of the DO loop. Thus, if this action is desired, a JMP instruction (i.e.
INSTRUCTION DESCRIPTIONS EOR EOR Logical Exclusive OR Operation: S ⊕ D[47:24] ➞D[47:24] (parallel move) Assembler Syntax: EOR S,D (parallel move) where ⊕ denotes the logical Exclusive OR operator Description: Logically exclusive OR the source operand S with bits 47–24 of the destination operand D and store the result in bits 47–24 of the destination accumulator. This instruction is a 24-bit operation. The remaining bits of the destination operand D are not affected.
INSTRUCTION DESCRIPTIONS EOR EOR Logical Exclusive OR Instruction Format: EOR S,D Opcode: 23 8 DATA BUS MOVE FIELD 7 4 0 1 J J 3 d 0 0 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S JJ D X0 X1 Y0 Y1 00 10 01 11 d A 0 B 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 101
INSTRUCTION DESCRIPTIONS ILLEGAL Illegal Instruction Interrupt Operation: Begin Illegal Instruction exception processing ILLEGAL Assembler Syntax: ILLEGAL Description: The ILLEGAL instruction is executed as if it were a NOP instruction. Normal instruction execution is suspended and illegal instruction exception processing is initiated. The interrupt vector address is located at address P:$3E.
INSTRUCTION DESCRIPTIONS ILLEGAL ILLEGAL Illegal Instruction Interrupt Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR The condition codes are not affected by this instruction.
INSTRUCTION DESCRIPTIONS INC INC Increment by One Operation: D+1 ➞ D Assembler Syntax: INC D Description: Increment by one the specified operand and store the result in the destination accumulator. One is added from the LSB of D. Example: : INC B ;Increment the content of the B accumulator by one : Explanation of Example: One is added to the content of the B accumulator.
INSTRUCTION DESCRIPTIONS INC INC Increment by One Instruction Format: INC D Opcode: 23 0 16 15 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 7 0 0 0 0 0 1 0 0 d Instruction Fields: D d A B 0 1 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 105
INSTRUCTION DESCRIPTIONS Jcc Jcc Jump Conditionally Operation: If cc, then 0xxx ➞PC else PC+1 ➞PC Assembler Syntax: Jcc xxx If cc, then ea ➞PC else PC+1 ➞PC Jcc xxx Description: Jump to the location in program memory given by the instruction’s effective address if the specified condition is true. If the specified condition is false, the program counter (PC) is incremented and the effective address is ignored.
INSTRUCTION DESCRIPTIONS Jcc Jcc Jump Conditionally Restrictions: A Jcc instruction used within a DO loop cannot begin at the address LA within that DO loop. A Jcc instruction cannot be repeated using the REP instruction. Example: : JNN – (R4) : ;jump to P:(R4) –1 if not normalized Explanation of Example: In this example, program execution is transferred to the address P:(R4)–1 if the result is not normalized.
INSTRUCTION DESCRIPTIONS Jcc Jcc Jump Conditionally Instruction Fields: cc=4-bit condition code=CCCC, xxx=12-bit Short Jump Address=aaaaaaaaaaaa Mnemonic C C C C Mnemonic C C C C CC (HS) GE NE PL NN EC LC GT 0 0 0 0 0 0 0 0 CS (LO) LT EQ MI NR ES LS LE 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Timing: 4+jx oscillator clock cycles Memory: 1+ea program words Instruction Format: Jcc ea Opcode: 23 0 0 0 0 1 0 1 16 15
INSTRUCTION DESCRIPTIONS Jcc Jcc Jump Conditionally Effective Addressing Mode MM MRRR (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute Address 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 r r r r r r r 0 r r r r r r r 0 r r r r r r r 0 where “rrr” refers to an address register R0-R7 Mnemonic C C C C Mnemonic C C C C CC (HS) GE NE PL NN EC LC GT 0 0 0 0 0 0 0 0 CS (LO) LT EQ MI NR ES LS LE 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1
INSTRUCTION DESCRIPTIONS JCLR JCLR Jump if Bit Clear Operation: If S[n]=0, then xxxx➞PC else PC+1➞PC Assembler Syntax: JCLR #n,X:ea,xxxx If S[n]=0, then xxxx ➞PC else PC+1 ➞PC JCLR #n,X:aa,xxxx If S[n]=0, then xxxx ➞PC else PC+1 ➞PC JCLR #n,X:pp,xxxx If S[n]=0, then xxxx ➞PC else PC+1 ➞PC JCLR #n,Y:ea,xxxx If S[n]=0, then xxxx ➞PC else PC+1 ➞PC JCLR #n,Y:aa,xxxx If S[n]=0, then xxxx ➞PC else PC+1 ➞PC JCLR #n,Y:pp,xxxx If S[n]=0, then xxxx ➞PC else PC+1 ➞PC JCLR #n,S,xxxx Description:
INSTRUCTION DESCRIPTIONS JCLR JCLR Jump if Bit Clear Restrictions: A JCLR instruction cannot be repeated using the REP instruction. A JCLR located at LA, LA–1, or LA–2 of the DO loop cannot specify the program controller registers SR, SP, SSH, SSL, LA, or LC as its target. JCLR SSH or JCLR SSL cannot follow an instruction that changes the SP.
INSTRUCTION DESCRIPTIONS JCLR JCLR Jump if Bit Clear Instruction Format: JCLR #n,X:ea,xxxx JCLR #n,Y:ea,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 0 0 8 1 M M M R R 7 R 1 0 S 0 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR xxxx=16-bit Absolute Address in extension word Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) 0 0 0 0 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 0 1 0
INSTRUCTION DESCRIPTIONS JCLR JCLR Jump if Bit Clear Instruction Format: JCLR #n,X:aa,xxxx JCLR #n,Y:aa,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 0 0 8 0 a a a a a 7 a 1 0 S 0 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa xxxx=16-bit Absolute Address in extension word Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 6+jx oscillator
INSTRUCTION DESCRIPTIONS JCLR JCLR Jump if Bit Clear Instruction Format: JCLR #n,X:pp,xxxx JCLR #n,Y:pp,xxxx Opcode: 23 0 16 0 0 0 1 0 1 0 15 1 8 0 p p p p p 7 p 1 0 S 0 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, pp=6-bit I/O Short Address=pppppp xxxx=16-bit Absolute Address in extension word I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 6+jx oscillator clock cycles
INSTRUCTION DESCRIPTIONS JCLR JCLR Jump if Bit Clear Instruction Format: JCLR #n,S,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 0 1 8 1 D D D D D D 7 0 0 0 0 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, S=source register=DDDDDD xxxx=16-bit Absolute Address in extension word Source Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier registers in AGU 8 pro
INSTRUCTION DESCRIPTIONS JMP JMP Jump Operation: 0xxx ➞ PC ea ➞ PC Assembler Syntax: JMP xxx JMP ea Description: Jump to the location in program memory given by the instruction’s effective address. All memory alterable addressing modes may be used for the effective address. A Fast Short Jump addressing mode may also be used. The 12-bit data is zero extended to form the effective address. Restrictions: A JMP instruction used within a DO loop cannot begin at the address LA within that DO loop.
INSTRUCTION DESCRIPTIONS JMP JMP Jump Instruction Fields: xxx=12-bit Short Jump Address=aaaaaaaaaaaa Timing: 4+jx oscillator clock cycles Memory: 1+ea program words Instruction Format: JMP ea Opcode: 23 0 16 15 0 0 0 1 0 1 0 1 8 1 M M M R R R 7 1 0 0 0 0 0 0 0 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: ea=6-bit Effective Address=MMMRRR Effective Addressing Mode MM MRRR (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1
INSTRUCTION DESCRIPTIONS JScc Jump to Subroutine Conditionally Operation: If cc, then SP+1➞SP; PC➞SSH; SR➞SSL; 0xxx➞PC else PC+1➞PC JScc Assembler Syntax: JScc xxx If cc, then SP+1➞SP; PC➞SSH; SR➞SSL; ea➞PC else PC+1➞PC JScc ea Description: Jump to the subroutine whose location in program memory is given by the instruction’s effective address if the specified condition is true.
INSTRUCTION DESCRIPTIONS JScc JScc Jump to Subroutine Conditionally where U denotes the logical complement of U, + denotes the logical OR operator, • denotes the logical AND operator, and ⊕ denotes the logical Exclusive OR operator Restrictions: A JScc instruction used within a DO loop cannot specify the loop address (LA) as its target. A JScc instruction used within in a DO loop cannot begin at the address LA within that DO loop. A JScc instruction cannot be repeated using the REP instruction.
INSTRUCTION DESCRIPTIONS JScc JScc Jump to Subroutine Conditionally Instruction Format: JScc xxx Opcode: 23 0 16 15 0 0 0 1 1 1 1 C 8 C C C a a a 7 a 0 a a a a a a a a Instruction Fields: cc=4-bit condition code=CCCC, xxx=12-bit Short Jump Address=aaaaaaaaaaaa Mnemonic C C C C Mnemonic C C C C CC (HS) GE NE PL NN EC LC GT 0 0 0 0 0 0 0 0 CS (LO) LT EQ MI NR ES LS LE 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1
INSTRUCTION DESCRIPTIONS JScc JScc Jump to Subroutine Conditionally Instruction Format: JScc ea Opcode: 23 0 0 0 0 1 0 1 16 15 1 1 8 1 M M M R R 7 R 1 0 0 1 0 C C C C OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: cc=4-bit condition code=CCCC, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode M M M R R R Mnemonic (Rn)–Nn 0 0 0 r r r CC (HS) (Rn)+Nn0 0 0 1 r r r GE (Rn)– 0 1 0 r r r NE (Rn)+ 0 1 1 r r r PL (Rn) 1 0 0 r r r NN (Rn+Nn) 1 0 1 r r r EC –(Rn) 1
INSTRUCTION DESCRIPTIONS JSCLR Jump to Subroutine if Bit Clear JSCLR Operation: Assembler Syntax If S[n]=0, JSCLR #n,X:ea,xxxx then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx ➞PC else PC+1 ➞PC f S[n]=0, then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC else PC+1➞PC JSCLR #n,X:aa,xxxx If S[n]=0, then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC else PC+1➞PC JSCLR #n,X:pp,xxxx If S[n]=0, then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC else PC+1➞PC JSCLR #n,Y:ea,xxxx If S[n]=0, then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC else PC+1➞PC JSCLR #n,Y:aa
INSTRUCTION DESCRIPTIONS JSCLR Jump to Subroutine if Bit Clear JSCLR specified in the effective address field is always updated independently of the state of the nth bit. All address register indirect addressing modes may be used to reference the source operand S. Absolute short and I/O short addressing modes may also be used. Restrictions: A JSCLR instruction used within a DO loop cannot specify the loop address (LA) as its target.
INSTRUCTION DESCRIPTIONS JSCLR JSCLR Jump to Subroutine if Bit Clear Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR For destination operand A or B: S —Computed according to the definition. See Notes on page A-129. L — Set if data limiting has occurred. See Notes on page A-129.
INSTRUCTION DESCRIPTIONS JSCLR JSCLR Jump to Subroutine if Bit Clear Instruction Format: JSCLR #n,X:ea,xxxx JSCLR #n,Y:ea,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 1 0 8 1 M M M R R 7 R 1 0 S 0 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR, xxxx=16-bit Absolute Address in extension word Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) 0 0 0 0 1 1 1 X Memory Y Memory 0
INSTRUCTION DESCRIPTIONS JSCLR JSCLR Jump to Subroutine if Bit Clear Instruction Format: JSCLR #n,X:aa,xxxx JSCLR #n,Y:aa,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 1 0 8 0 a a a a a 7 a 1 0 S 0 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa, xxxx=16-bit Absolute Address in extension word Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timin
INSTRUCTION DESCRIPTIONS JSCLR JSCLR Jump to Subroutine if Bit Clear Instruction Format: JSCLR #n,X:pp,xxxx JSCLR #n,Y:pp,xxxx Opcode: 23 0 16 0 0 0 1 0 1 1 15 1 8 0 p p p p p 7 p 1 0 S 0 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, pp=6-bit I/O Short Address=pppppp, xxxx=16-bit Absolute Address in extension word I/O Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 6+jx osci
INSTRUCTION DESCRIPTIONS JSCLR JSCLR Jump to Subroutine if Bit Clear Instruction Format: JSCLR #n,S,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 1 1 8 1 D D D D D D 7 0 0 0 0 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, S=source register=DDDDDD, xxxx=16-bit Absolute Address in extension word Source Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier regi
INSTRUCTION DESCRIPTIONS JSCLR Jump to Subroutine if Bit Clear JSCLR Notes: If A or B is specified as the destination operand, the following sequence of events takes place: 1. The S bit is computed according to its definition (See Section A.5) 2. The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR). 3.
INSTRUCTION DESCRIPTIONS JSET Jump if Bit Set Operation: If S[n]=0, then xxxx➞PC else PC+1➞PC Assembler Syntax: JSET #n,X:ea,xxxx If S[n]=1, then xxxx➞PC else PC+1➞PC JSET #n,X:ea,xxxx If S[n]=1, then xxxx➞PC else PC+1➞PC JSET #n,X:aa,xxxx If S[n]=1, then xxxx ➞PC else PC+1➞PC JSET #n,X:pp,xxxx If S[n]=1, then xxxx➞PC else PC+1➞PC JSET #n,Y:ea,xxxx If S[n]=1, then xxxx ➞PC else PC+1➞PC JSET #n,Y:aa,xxxx If S[n]=1, then xxxx➞PC else PC+1➞PC JSET #n,Y:pp,xxxx If S[n]=1, then xxxx➞PC els
INSTRUCTION DESCRIPTIONS JSET Jump if Bit Set Restrictions: A JSET instruction used within a DO loop cannot specify the loop address (LA) as its target. A JSET located at LA, LA–1, or LA–2 of a DO loop cannot specify the program controller registers SR, SP, SSH, SSL, LA, or LC as its target. JSET SSH or JSET SSL cannot follow an instruction that changes the SP. A JSET instruction cannot be repeated using the REP instruction.
INSTRUCTION DESCRIPTIONS JSET Jump if Bit Set Instruction Format: JSET #n,X:ea,xxxx JSET #n,Y:ea,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 0 0 1 M M M R R 8 7 R 1 0 S 1 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR xxxx=16-bit Absolute Address in extension word Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) 0 0 0 0 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 0 1 0 1 0 1
INSTRUCTION DESCRIPTIONS JSET Jump if Bit Set Instruction Format: JSET #n,X:aa,xxxx JSET #n,Y:aa,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 0 0 8 0 a a a a a 7 a 1 0 S 1 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa, xxxx=16-bit Absolute Address in extension word Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 6+jx oscillator clock c
INSTRUCTION DESCRIPTIONS JSET Jump if Bit Set Instruction Format: JSET #n,X:pp,xxxx JSET #n,Y:pp,xxxx Opcode: 23 0 16 0 0 0 1 0 1 0 15 1 8 0 p p p p p 7 p 1 0 S 1 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, pp=6-bit I/O Short Address=pppppp, xxxx=16-bit Absolute Address in extension word I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 6+jx oscillator clock cycles Memory
INSTRUCTION DESCRIPTIONS JSET Jump if Bit Set Instruction Format: JSET #n,S,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 0 1 8 1 D D D D D D 7 0 0 0 1 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, S=source register=DDDDDD, xxxx=16-bit Absolute Address in extension word Source Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier registers in AGU 8 program co
INSTRUCTION DESCRIPTIONS JSR JSR Jump to Subroutine Operation: SP+1➞SP; PC➞SSH; SR➞SSL; 0xxx➞PC Assembler Syntax: JSR xxx SP+➞SP; PC➞SSH; SR➞SSL; ea➞PC JSR ea Description: Jump to the subroutine whose location in program memory is given by the instruction’s effective address. The address of the instruction immediately following the JSR instruction (PC) and the system status register (SR) is pushed onto the system stack.
INSTRUCTION DESCRIPTIONS JSR JSR Jump to Subroutine Instruction Format: JSR xxx Opcode: 23 0 16 15 0 0 0 1 1 0 1 0 8 0 0 0 a a a 7 a 0 a a a a a a a a Instruction Fields: xxx=12-bit Short Jump Address=aaaaaaaaaaaa Timing: 4+jx oscillator clock cycles Memory: 1+ea program words Instruction Format: JSR ea Opcode: 23 0 0 0 0 1 0 1 16 15 1 1 8 1 M M M R R R 7 1 0 0 0 0 0 0 0 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: ea=6-bit Effective Add
INSTRUCTION DESCRIPTIONS JSSET Jump to Subroutine if Bit Set Operation: If S[n]=1, then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC else PC+1➞PC JSSET Assembler Syntax JSSET #n,X:ea,xxxx If S[n]=1, then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC else PC+1➞PC JSSET #n,X:aa,xxxx If S[n]=1, then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC else PC+1➞PC JSSET #n,X:pp,xxxx If S[n]=1, then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC else PC+1➞PC JSSET #n,Y:ea,xxxx If S[n]=1, then SP+1➞SP; PC➞SSH; SR ➞SSL; xxxx➞PC else PC+1➞PC JSSET #n,Y:aa
INSTRUCTION DESCRIPTIONS JSSET JSSET Jump to Subroutine if Bit Set nth bit. All address register indirect addressing modes may be used to reference the source operand S. Absolute short and I/O short addressing modes may also be used. Restrictions: A JSSET instruction used within a DO loop cannot specify the loop address (LA) as its target. A JSSET located at LA, LA–1, or LA–2 of a DO loop, cannot specify the program controller registers SR, SP, SSH, SSL, LA, or LC as its target.
INSTRUCTION DESCRIPTIONS JSSET JSSET Jump to Subroutine if Bit Set Instruction Format: JSSET #n,X:ea,xxxx JSSET #n,Y:ea,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 1 0 8 1 M M M R R 7 R 1 0 S 1 b b b b b ABSOLUTE ADDRESS EXTEN- Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR, xxxx=16-bit Absolute Address in extension word Effective Addressing Mode MM MRRR Memory SpaceS (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) 0 0 0 0 1 1 1 X Memory Y Memory 0 0 1
INSTRUCTION DESCRIPTIONS JSSET JSSET Jump to Subroutine if Bit Set Instruction Format: JSSET #n,X:aa,xxxx JSSET #n,Y:aa,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 1 0 8 0 a a a a a 7 a 1 0 S 1 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa, xxxx=16-bit Absolute Address in extension word Absolute Short Address aaaaaa 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing:
INSTRUCTION DESCRIPTIONS JSSET JSSET Jump to Subroutine if Bit Set Instruction Format: JSSET #n,X:pp,xxxx JSSET #n,Y:pp,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 1 1 8 0 p p p p p 7 p 1 0 S 1 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, pp=6-bit I/O Short Address=pppppp, xxxx=16-bit Absolute Address in extension word I/O Short Address pppppp 000000 Memory SpaceS X Memory Y Memory • • 0 1 Bit Number bbbbb 00000 • 10111 111111 Timing: 6+jx osci
INSTRUCTION DESCRIPTIONS JSSET JSSET Jump to Subroutine if Bit Set Instruction Format: JSSET #n,S,xxxx Opcode: 23 0 0 0 0 1 0 1 16 15 1 1 8 1 D D D D D D 7 0 0 0 1 b b b b b ABSOLUTE ADDRESS EXTENSION Instruction Fields: #n=bit number=bbbbb, S=source register=DDDDDD, xxxx=16-bit Absolute Address in extension word Source Register DD D D D D 4 registers in Data ALU 8 accumulators in Data ALU 8 address registers in AGU 8 address offset registers in AGU 8 address modifier regist
INSTRUCTION DESCRIPTIONS LSL LSL Logical Shift Left 47 Operation: 24 C 0 (parallel move) Assembler Syntax: LSL D (parallel move) Description: Logically shift bits 47–24 of the destination operand D one bit to the left and store the result in the destination accumulator. Prior to instruction execution, bit 47 of D is shifted into the carry bit C, and a zero is shifted into bit 24 of the destination accumulator D. This instruction is a 24-bit operation.
INSTRUCTION DESCRIPTIONS LSL LSL Logical Shift Left Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS LSR LSR Logical Shift Right 47 Operation: 24 0 C (parallel move) Assembler Syntax: LSR D (parallel move) Description: Logically shift bits 47–24 of the destination operand D one bit to the right and store the result in the destination accumulator. Prior to instruction execution, bit 24 of D is shifted into the carry bit C, and a zero is shifted into bit 47 of the destination accumulator D. This instruction is a 24-bit operation.
INSTRUCTION DESCRIPTIONS LSR LSR Logical Shift Right Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS LUA LUA Load Updated Address Operation: ea➞d Assembler Syntax: LUA ea,D Description: Load the updated address into the destination address register D. The source address register and the update mode used to compute the updated address are specified by the effective address (ea). Note that the source address register specified in the effective address is not updated. All update addressing modes may be used. Note: This instruction is considered to be a move-type instruction.
INSTRUCTION DESCRIPTIONS LUA LUA Load Updated Address Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR The condition codes are not affected by this instruction.
INSTRUCTION DESCRIPTIONS MAC MAC Signed Multiply-Accumulate Operation: D±S1∗S2➞D (parallel move) Assembler Syntax: MAC (±)S1,S2,D (parallel move) D±S1∗S2➞D (parallel move) MAC (±)S2,S1,D (parallel move) D±(S1∗2-n)➞D (no parallel move) MAC (±)S,#n,D (no parallel move) Description: Multiply the two signed 24-bit source operands S1 and S2 (or the signed 24-bit source operand S by the positive 24-bit immediate operand 2-n) and add/subtract the product to/from the specified 56-bit destination accumul
INSTRUCTION DESCRIPTIONS MAC MAC Signed Multiply-Accumulate Condition Codes: 15 14 13 LF DM T 12 11 10 9 8 7 6 5 4 3 2 1 0 ** S1 S0 I1 I0 S L E U N Z V C MR CCR S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION.
INSTRUCTION DESCRIPTIONS MAC MAC Signed Multiply-Accumulate Timing: 2+mv oscillator clock cycles Memory: 1+mv program words Example 2: : X0, : MAC #3, A ; Before Execution X0 A After Execution $654321 X0 $654321 $00:100000:000000 A $00:1CA864:200000 Explanation of Example 2: The content of X0 ($654321) is multiplied by 2-3 and then added to the content of the A accumulator ($00:100000:000000). The result is then placed in the A accumulator.
INSTRUCTION DESCRIPTIONS MAC Signed Multiply-Accumulate n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 sssss 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 MAC constant 010000000000000000000000 001000000000000000000000 000100000000000000000000 000010000000000000000000 000001000000000000000000 000000100000000000000000 000000010000000000000000 000000001000000000000000 000000000100000000000000 000000
INSTRUCTION DESCRIPTIONS MACR Signed Multiply-Accumulate and Round Operation: D±S1∗S2+r➞D (parallel move) MACR Assembler Syntax: MACR (±)S1,S2,D (parallel move) D±S1∗S2+r➞ D (parallel move) MACR (±)S2,S1,D (parallel move) D±(S1∗2-n)+r➞D (no parallel move) MACR (±)S,#n,D (no parallel move) Description: Multiply the two signed 24-bit source operands S1 and S2 (or the signed 24-bit source operand S by the positive 24-bit immediate operand 2-n), add/subtract the product to/from the specified 56-bit
INSTRUCTION DESCRIPTIONS MACR MACR Signed Multiply-Accumulate and Round Explanation of Example 1: Prior to execution, the 24-bit X0 register contains the value $123456 (0.142222166), the 24-bit Y0 register contains the value $123456 (0.142222166), and the 56-bit B accumulator contains the value $00:100000:000000 (0.125).
INSTRUCTION DESCRIPTIONS MACR Signed Multiply-Accumulate and Round Instruction Fields 1: S1∗S2 Q Q Q X0 X0 Y0 Y0 X1 X0 Y1 Y0 X0 Y1 Y0 X0 X1 Y0 Y1 X1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sign k D d + – 0 1 A 0 B 1 MACR Note: Only the indicated S1∗S2 combinations are valid. X1∗X1 and Y1∗Y1 are not valid.
INSTRUCTION DESCRIPTIONS MACR MACR Signed Multiply-Accumulate and Round Instruction Format 2: MACR (±)S,#n,D Opcode 2: 23 0 16 15 0 0 0 0 0 0 Instruction Fields 2: S Q Q Sign Y1 X0 Y0 X1 0 0 1 1 0 1 0 1 + – n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 0 0 0 s s k D d 0 1 A B 0 1 sssss 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 s s 8 7 s 1 0 1 Q Q d k 1 1
INSTRUCTION DESCRIPTIONS MOVE MOVE Move Data Operation: S➞D Assembler Syntax: MOVE S,D Description: Move the contents of the specified data source S to the specified destination D. This instruction is equivalent to a data ALU NOP with a parallel data move. When a 56-bit accumulator (A or B) is specified as a source operand S, the accumulator value is optionally shifted according to the scaling mode bits S0 and S1 in the system status register (SR).
INSTRUCTION DESCRIPTIONS MOVE MOVE Move Data Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $FF:FFFFFF:FFFFFF, and the 24-bit X0 register contains the value $234567. The execution of the MOVE X0,A1 instruction moves the 24-bit value in the X0 register into the 24-bit A1 register without automatic sign extension and without automatic zeroing.
INSTRUCTION DESCRIPTIONS MOVE Move Data MOVE Parallel Move Descriptions: Thirty of the sixty-two instructions allow an optional parallel data bus movement over the X and/or Y data bus. This allows a data ALU operation to be executed in parallel with up to two data bus moves during the instruction cycle. Ten types of parallel moves are permitted, including register to register moves, register to memory moves, and memory to register moves.
INSTRUCTION DESCRIPTIONS MOVE Move Data MOVE When a 56-bit accumulator (A or B) is specified as a destination operand D, any 24-bit source data to be moved into that accumulator is automatically extended to 56 bits by sign extending the MS bit of the source operand (bit 23) and appending the source operand with 24 LS zeros. Similarly, any 48-bit source data to be loaded into a 56-bit accumulator is automatically sign extended to 56 bits.
INSTRUCTION DESCRIPTIONS No Parallel Data Move Operation: (. . . . . ) Assembler Syntax: (. . . . .) where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. Description: Many (30 of the total 66) instructions in the DSP56K instruction set allow parallel moves. The parallel moves have been divided into 10 opcode categories. This category is a parallel move NOP and does not involve data bus move activity.
INSTRUCTION DESCRIPTIONS No Parallel Data Move Instruction Format: (.....
INSTRUCTION DESCRIPTIONS I Operation: ( . . . . . ), #xx➞D Immediate Short Data Move I Assembler Syntax: ( . . . . . ) #xx,D where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. Description: Move the 8-bit immediate data value (#xx) into the destination operand D. If the destination register D is A0, A1, A2, B0, B1, B2, R0–R7, or N0–N7, the 8-bit immediate short operand is interpreted as an unsigned integer and is stored in the specified destination register.
INSTRUCTION DESCRIPTIONS I I Immediate Short Data Move Example: : ABS B #$18,R1 : ;take absolute value of B, #$18➞R1 Before Execution R1 $0000 After Execution R1 $0018 Explanation of Example: Prior to execution, the 16-bit address register R1 contains the value $0000. The execution of the parallel move portion of the instruction, #$18,R1, moves the 8-bit immediate short operand into the eight LS bits of the R1 register and zeros the remaining eight MS bits of that register.
INSTRUCTION DESCRIPTIONS I I Immediate Short Data Move Condition Codes: 15 14 13 LF DM T 12 11 10 9 8 7 6 5 4 3 2 1 0 ** S1 S0 I1 I0 S L E U N Z V C MR CCR The condition codes are not affected by this type of parallel move. Instruction Format: ( . . . . .
INSTRUCTION DESCRIPTIONS I Immediate Short Data Move D X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B R0-R7 N0-N7 D Sign Ext d d d d d 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 r n 0 0 1 1 0 0 1 1 0 0 1 1 r n 0 1 0 1 0 1 0 1 0 1 0 1 r n no no no no no no no no no no A2 B2 I D Zero no no no no no no no no no no A0 B0 where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 167
INSTRUCTION DESCRIPTIONS R Operation: ( . . . . . ); S➞D Register to Register Data Move R Assembler Syntax: ( . . . . . ) S,D where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. Description: Move the source register S to the destination register D.
INSTRUCTION DESCRIPTIONS R R Register to Register Data Move Example: : MACR–X0,Y0,A Y1,N5 : ;–X0∗Y0+A➞A, move Y1➞N5 Before Execution After Execution Y1 $001234 Y1 $001234 N5 $0000 N5 $1234 Explanation of Example: Prior to execution, the 24-bit Y1 register contains the value $001234 and the 16-bit address offset register N5 contains the value $0000.
INSTRUCTION DESCRIPTIONS R R Register to Register Data Move Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during parallel move Instruction Format: ( . . . . .
INSTRUCTION DESCRIPTIONS R Register to Register Data Move Instruction Fields: e e e e e S or D d d d d d X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B R0-R7 N0-N7 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 r n 0 0 1 1 0 0 1 1 0 0 1 1 r n 0 1 0 1 0 1 0 1 0 1 0 1 r n S S/L D Sign Ext D Zero no no no no no no no no no no yes yes no no no no no no no no no no A2 B2 no no no no no no no no no no A0 B0 R where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clo
INSTRUCTION DESCRIPTIONS U U Address Register Update Operation: ( . . . . . ); ea➞Rn Assembler Syntax: ( . . . . . ) ea where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. Description: Update the specified address register according to the specified effective addressing mode. All update addressing modes may be used.
INSTRUCTION DESCRIPTIONS U U Address Register Update Instruction Format: ( . . . . .
INSTRUCTION DESCRIPTIONS X: Operation: ( . . . . . ); X:ea➞D X Memory Data Move X: Assembler Syntax: ( . . . . . ) X:ea,D ( . . . . . ); X:aa➞D ( . . . . . ) X:aa,D ( . . . . . ); S➞X:ea ( . . . . . ) S,X:ea ( . . . . . ); S➞X:aa ( . . . . . ) S,X:aa ( . . . . . ); #xxxxxx➞D ( . . . . . ) #xxxxxx,D where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. Description: Move the specified word operand from/to X memory.
INSTRUCTION DESCRIPTIONS X: X: X Memory Data Move Note:Due to instruction pipelining, if an AGU register (Mn, Nn, or Rn) is directly changed with this instruction, the new contents may not be available for use until the second following instruction. See the restrictions discussed in A.9.6 - R, N, and M Register Restrictions on page A-page 310.
INSTRUCTION DESCRIPTIONS X: X: X Memory Data Move Instruction Format: ( . . . . . ) X:ea,D ( . . . . . ) S,X:ea ( . . . . .
INSTRUCTION DESCRIPTIONS X: X Memory Data Move S,D d d d d d X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B R0-R7 N0-N7 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 r n 0 0 1 1 0 0 1 1 0 0 1 1 r n 0 1 0 1 0 1 0 1 0 1 0 1 r n S S/L D Sign Ext D Zero no no no no no no no no no no yes yes no no no no no no no no no no A2 B2 no no no no no no no no no no A0 B0 X: where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOR
INSTRUCTION DESCRIPTIONS X: X: X Memory Data Move Instruction Format: ( . . . . . ) X:aa,D ( . . . . .
INSTRUCTION DESCRIPTIONS X: X Memory Data Move S,D d d d d d X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B R0-R7 N0-N7 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 r n 0 0 1 1 0 0 1 1 0 0 1 1 r n 0 1 0 1 0 1 0 1 0 1 0 1 r n S S/L D Sign Ext D Zero no no no no no no no no no no yes yes no no no no no no no no no no A2 B2 no no no no no no no no no no A0 B0 X: where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOR
INSTRUCTION DESCRIPTIONS X:R X:R X Memory and Register Data Move Operation: Class I ( . . . . . ); X:ea➞D1; S2➞D2 Assembler Syntax: Class I ( . . . . . ) X:ea,D1 S2,D2 ( . . . . . ); S1➞X:ea; S2➞D2 ( . . . . . ) S1,X:ea S2,D2 ( . . . . . ); #xxxxxx➞D1; S2➞D2 ( . . . . . ) #xxxxxx,D1 S2,D2 Class II ( . . . . . ); A➞X:ea; X0➞A Class II ( . . . . . ) A,X:ea X0,A ( . . . . . ); B➞X:ea; X0➞B ( . . . . . ) B,X:ea X0,B where ( . . . . .
INSTRUCTION DESCRIPTIONS X:R X:R X Memory and Register Data Move If the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source S1 and/or S2 in the parallel data bus move operation. This allows data to be moved in the same instruction in which it is being used as a source operand by a data ALU operation. That is, duplicate sources are allowed within the same instruction.
INSTRUCTION DESCRIPTIONS X:R X:R X Memory and Register Data Move Class II Example: : MAC X0,Y0,A B,X:(R1)+ X0,B : ;multiply X0 and Y0 and accumulate in A ;move B to X memory location pointed to ;by R1 and postincrement R1 ;move X0 to B Before Execution X0 After Execution $400000 X0 $400000 Y0 $600000 Y0 $600000 A $00:000000:000000 A $00:300000:000000 B $FF:7FFFFF:000000 B $00:400000:000000 X:$1234 $000000 X:$1234 $800000 R1 $1234 R1 $1235 Explanation of the Class II Example: P
INSTRUCTION DESCRIPTIONS X:R X:R X Memory and Register Data Move Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during parallel move. Class I Instruction Format: ( . . . . . ) X:ea,D1 S2,D2 ( . . . . . ) S1,X:ea S2, D2 ( . . . . .
INSTRUCTION DESCRIPTIONS X:R X:R X Memory and Register Data Move S1,D1 f f S1 D1 D1 S/L Sign Ext Zero X0 X1 A B 0 0 1 1 no no yes yes 0 1 0 1 no no A2 B2 no no A0 B0 S2 S2 d S/L D2 D2 D2 f Sign Ext Zero A B 0 1 Y0 Y1 0 1 yes yes no no no no Timing: mv oscillator clock cycles Memory: mv program words A - 184 INSTRUCTION SET DETAILS MOTOROLA
INSTRUCTION DESCRIPTIONS X:R X Memory and Register Data Move X:R Class II Instruction Format: ( . . . . . ) A➞X:ea X0➞A ( . . . . .
INSTRUCTION DESCRIPTIONS Y: Operation: ( . . . . . ); Y:ea➞D Y Memory Data Move Y: Assembler Syntax: ( . . . . . ) Y:ea,D ( . . . . . ); Y:aa➞D ( . . . . . ) Y:aa,D ( . . . . . ); S➞Y:ea ( . . . . . ) S,Y:ea ( . . . . . ); S➞Y:aa ( . . . . . ) S,Y:aa ( . . . . . ); #xxxxxx➞D ( . . . . . ) #xxxxxx,D where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. Description: Move the specified word operand from/to Y memory.
INSTRUCTION DESCRIPTIONS Y: Y: Y Memory Data Move Note: This parallel data move is considered to be a move-type instruction. Due to instruction pipelining, if an AGU register (Mn, Nn, or Rn) is directly changed with this instruction, the new contents may not be available for use until the second following instruction. See the restrictions discussed in A.9.6 - R, N, and M Register Restrictions on page A-page 310.
INSTRUCTION DESCRIPTIONS Y: Y: Y Memory Data Move Note: The MOVE A,Y:ea operation will result in a 24-bit positive or negative saturation constant being stored in the specified 24-bit Y memory location if the signed integer portion of the A accumulator is in use. Instruction Format: ( . . . . . ) Y:ea,D ( . . . . . ) S,Y:ea ( . . . . .
INSTRUCTION DESCRIPTIONS Y: Y Memory Data Move S,D d d d d d X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B R0-R7 N0-N7 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 r n 0 0 1 1 0 0 1 1 0 0 1 1 r n 0 1 0 1 0 1 0 1 0 1 0 1 r n S S/L D Sign Ext D Zero no no no no no no no no no no yes yes no no no no no no no no no no A2 B2 no no no no no no no no no no A0 B0 Y: where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOR
INSTRUCTION DESCRIPTIONS Y: Y: Y Memory Data Move Instruction Format: ( . . . . . ) Y:aa,D ( . . . . .
INSTRUCTION DESCRIPTIONS Y: Y Memory Data Move S,D d d d d d X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B R0-R7 N0-N7 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 r n 0 0 1 1 0 0 1 1 0 0 1 1 r n 0 1 0 1 0 1 0 1 0 1 0 1 r n S S/L D Sign Ext D Zero no no no no no no no no no no yes yes no no no no no no no no no no A2 B2 no no no no no no no no no no A0 B0 Y: where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOR
INSTRUCTION DESCRIPTIONS R:Y R:Y Register and Y Memory Data Move Operation: Class I ( . . . . . ); S1➞D1; Y:ea➞D2 Assembler Syntax: Class I ( . . . . . ) S1,D1 Y:ea,D2 ( . . . . . ); S1➞D1; S2➞Y:ea ( . . . . . ) S1,D1 S2,Y:ea ( . . . . . ); S1➞D1; #xxxxxx➞D2 ( . . . . . ) S1,D1 #xxxxxx,D2 Class II ( . . . . . ); Y0 ➞A; A➞Y:ea Class II ( . . . . . ) Y0,A A,Y:ea ( . . . . . ); Y0➞B; B➞Y:ea ( . . . . . ) Y0,B B,Y:ea where ( . . . . .
INSTRUCTION DESCRIPTIONS R:Y R:Y Register and Y Memory Data Move If the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source S1 and/or S2 in the parallel data bus move operation. This allows data to be moved in the same instruction in which it is being used as a source operand by a data ALU operation. That is, duplicate sources are allowed within the same instruction.
INSTRUCTION DESCRIPTIONS R:Y R:Y Register and Y Memory Data Move Class II Example: : MAC X0,Y0,A Y0,B B,Y:(R1)+ : ;multiply X0 and Y0 and accumulate in A ;move B to Y memory location pointed to ;by R1 and postincrement R1 ;move Y0 to B Before Execution After Execution X0 $400000 X0 $400000 Y0 $600000 Y0 $600000 A $00:000000:000000 A $00:300000:000000 B $00:800000:000000 B $00:600000:000000 Y:$1234 $000000 Y:$1234 $7FFFFF R1 $1234 R1 $1235 Explanation of the Class II Exampl
INSTRUCTION DESCRIPTIONS R:Y R:Y Register and Y Memory Data Move Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during parallel move. Class I Instruction Format: ( . . . . . ) S1,D1 Y:ea,D2 ( . . . . . ) S1,D1 S2,Y:ea ( . . . . .
INSTRUCTION DESCRIPTIONS R:Y R:Y Register and Y Memory Data Move Instruction Fields: ea=6-bit Effective Address=MMMRRR Register W Read S2 0 Write D2 1 Effective Addressing Mode M M M R R R (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address Immediate data 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 0 0 r r r r r r r 0 1 r r r r r r r 0 0 r r r r r r r 0 0 where “rrr” refers to an address register R0–R7 S1 S1 d S/L D1 D1 D1 e Sign Ext Zero A 0 B 1 X0 0 X1 1 yes yes no no no
INSTRUCTION DESCRIPTIONS R:Y Register and Y Memory Data Move R:Y Class II Instruction Format: ( . . . . . ) Y0 ➞ A A ➞ Y:ea ( . . . . .
INSTRUCTION DESCRIPTIONS L: Long Memory Data Move Operation: ( . . . . . ); X:ea ➞ D1; Y:ea ➞ D2 L: Assembler Syntax: ( . . . . . ) L:ea,D ( . . . . . ); X:aa ➞ D1; Y:aa ➞ D2 ( . . . . . ) L:aa,D ( . . . . . ); S1 ➞ X:ea; S2 ➞ Y:ea ( . . . . . ) S,L:ea ( . . . . . ); S1 ➞ X:aa; S2 ➞ Y:aa ( . . . . . ) S,L:aa where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves. Description: Move one 48-bit long-word operand from/to X and Y memory.
INSTRUCTION DESCRIPTIONS L: L: Long Memory Data Move Example: : CMP Y0,B : A,L:$1234 ;compare Y0 and B, save 48-bit A1:A0 value Before Execution A After Execution A $01:234567:89ABCD X:$1234 $000000 Y:$1234 $:000000 $01:234567:89ABCD X:$1234 $7FFFFF Y:$1234 $FFFFFF Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $01:234567:89ABCD, the 24-bit X memory location X:$1234 contains the value $000000, and the 24-bit Y memory location Y:$1234 contains the v
INSTRUCTION DESCRIPTIONS L: L: Long Memory Data Move Instruction Format: ( . . . . . ) L:ea,D ( . . . . .
INSTRUCTION DESCRIPTIONS L: L: Long Memory Data Move Instruction Format: ( . . . . . ) L:aa,D ( . . . . .
INSTRUCTION DESCRIPTIONS X: Y: XY Memory Data Move X: Y: Operation: ( . . . . . ); X: ➞ D1; Y: ➞ D2 Assembler Syntax: ( . . . . . ) X:,D1 Y:,D2 ( . . . . . ); X: ➞ D1; S2 ➞ Y: ( . . . . . ) X:,D1 S2,Y: ( . . . . . ); S1 ➞ X:; Y: ➞ D2 ( . . . . . ) S1,X: Y:,D2 ( . . . . . ); S1 ➞ X:; S2 ➞ Y: ( . . . . . ) S1,X: S2,Y: where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves.
INSTRUCTION DESCRIPTIONS X: Y: X: Y: XY Memory Data Move Example: : MPYR X1,Y0,A : X1,X:(R0)+ ;X1∗Y0 ➞ A,save X1 and Y0 Y0,Y:(R4)+N4 Before Execution After Execution X1 $123123 X1 Y0 $456456 Y0 $456456 R0 $1000 R0 $1001 R4 $0100 R4 $0123 $0023 N4 $123123 $0023 N4 X:$1000 $000000 X:$1000 $123123 Y:$0100 $000000 Y:$0100 $456456 Explanation of Example: Prior to execution, the 24-bit X1 register contains the value $123123, the 24-bit Y0 register contains the value $456456,
INSTRUCTION DESCRIPTIONS X: Y: X: Y: XY Memory Data Move Note: The MOVE A,X: B,Y: operation will result in one or two 24-bit positive and/or negative saturation constant(s) being stored in the specified 24-bit X and/or Y memory location(s) if the signed integer portion of the A and/or B accumulator(s) is in use. Instruction Format: ( . . . . . ) X:,D1 Y:,D2 ( . . . . . ) X:,D1 S2,Y: ( . . . . . ) S1,X: Y:,D2 ( . . . . .
INSTRUCTION DESCRIPTIONS X: Y: XY Memory Data Move X: Y: S1 D1 D1 Y Effective S1, D1 e e S/L Sign Ext Zero Addressing Mode m m r r X0 0 0 no no no (Rn) +Nn 0 1 t t X1 0 1 no no no (Rn) 1 0 t t A 1 0 yes A2 A0 (Rn) + 1 1 t t B 1 1 yes B2 B0 (Rn) 0 0 t t where “tt” refers to an address register R4 - R7 or R0 - R3 which is in the opposite address register bank from the one used in the X effective address, previously described Register w Read S1 0 Write D1 1 Register W Read S2 0 Write D2 1 S2, D2 Y0 Y1 A
INSTRUCTION DESCRIPTIONS MOVEC Operation: X:ea➞D1 Move Control Register MOVEC Assembler Syntax: MOVE(C) X:ea,D1 X:aa➞D1 MOVE(C) X:aa,D1 S1➞X:ea MOVE(C) S1,X:ea S1➞X:aa MOVE(C) S1,X:aa Y:ea➞D1 MOVE(C) Y:ea,D1 Y:aa➞D1 MOVE(C) Y:aa,D1 S1➞Y:ea MOVE(C) S1,Y:ea S1➞Y:aa MOVE(C) S1,Y:aa S1➞D2 MOVE(C) S1,D2 S2➞D1 MOVE(C) S2,D1 #xxxx➞D1 MOVE(C) #xxxx,D1 #xx➞D1 MOVE(C) #xx,D1 Description: Move the contents of the specified source control register S1 or S2 to the specified destinat
INSTRUCTION DESCRIPTIONS MOVEC Move Control Register MOVEC register is in use, and the data is to be moved into a 24-bit destination, the value stored in the destination is limited to a maximum positive or negative saturation constant to minimize truncation error.
INSTRUCTION DESCRIPTIONS MOVEC MOVEC Move Control Register A MOVEC instruction which specifies SSH as the source operand or LA, LC, SSH, SSL, or SP as the destination operand cannot be used immediately before a DO instruction. A MOVEC instruction which specifies SSH as the source operand or LA, LC, SR, SSH, SSL, or SP as the destination operand cannot be used immediately before an ENDDO instruction.
INSTRUCTION DESCRIPTIONS MOVEC MOVEC Move Control Register Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR For D1 or D2=SR operand: S — Set according to bit 7 of the source operand L — Set according to bit 6 of the source operand E — Set according to bit 5 of the source operand U — Set according to bit 4 of the source operand N — Set according to bit 3 of the source operand Z — Set according to bit 2 of the source ope
INSTRUCTION DESCRIPTIONS MOVEC Register W Read S Write D 0 1 MOVEC Move Control Register Effective Addressing Mode M M M R R R (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address Immediate Data 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 0 0 r r r r r r r 0 1 r r r r r r r 0 0 r r r r r r r 0 0 where “rrr” refers to an address register R0–R7 Memory Space s X Memory 0 Y Memory 1 S1, D1 M0–M7 SR OMR SP SSH SSL LA LC where “nnn” = Mn number (M0–M7) ddddd 00nnn 11001 11010 11011 11
INSTRUCTION DESCRIPTIONS MOVEC MOVEC Move Control Register Instruction Format: MOVE(C) X:aa,D1 MOVE(C) S1,X:aa MOVE(C) Y:aa,D1 MOVE(C) S1,Y:aa Opcode: 23 0 16 15 0 0 0 0 1 0 1 W 0 a a a a a 8 7 a 0 0 s 1 d d d d d Instruction Fields: aa=6-bit Absolute Short Address=aaaaaa Register W Read S 0 Write D 1 Absolute Short Address aaaaaa 000000 • • 111111 Memory Space s X Memory 0 Y Memory 1 S1, D1 M0–M7 SR OMR SP SSH SSL LA LC where “nnn” = Mn number (M0–M7) ddddd 00nnn 11001 110
INSTRUCTION DESCRIPTIONS MOVEC MOVEC Move Control Register Instruction Format: MOVE(C) S1,D2 MOVE(C) S2,D1 Opcode: 23 0 16 15 0 0 0 0 1 0 0 W 1 e e e e e 8 7 e 1 0 0 1 d d d d d Instruction Fields: Register Read S1 Write D1 S1, D1 M0–M7 SR OMR SP Memory Space s SSH X Memory 0 SSL Y Memory 1 LA LC where “nnn” = Mn number (M0–M7) S2, D2 X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B W 0 1 eeeeee 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 S2 S/L no n
INSTRUCTION DESCRIPTIONS MOVEC MOVEC Move Control Register Timing: 2+mvc oscillator clock cycles Memory: 1+ea program words Instruction Format: MOVE(C) #xx,D1 Opcode: 23 0 16 15 0 0 0 0 1 0 1 i 8 i i i i i i i 7 1 0 0 1 d d d d d Instruction Fields: #xx=8-bit Immediate Short Data=i i i i i i i i D1 ddddd M0–M7 00nnn SR 11001 OMR 11010 SP 11011 SSH 11100 SSL 11101 LA 11110 LC 11111 where “nnn” = Mn number (M0–M7) Timing: 2+mvc oscillator clock cycles Memory: 1+ea program words M
INSTRUCTION DESCRIPTIONS MOVEM Operation: S➞P:ea Move Program Memory MOVEM Assembler Syntax: MOVE(M) S,P:ea S➞P:aa MOVE(M) S,P:aa P:ea➞D MOVE(M) P:ea,D P:aa➞D MOVE(M) P:aa,D Description: Move the specified operand from/to the specified program (P) memory location. This is a powerful move instruction in that the source and destination registers S and D may be any register. All memory alterable addressing modes may be used as well as the absolute short addressing mode.
INSTRUCTION DESCRIPTIONS MOVEM Move Program Memory MOVEM operands, both the automatic sign-extension and zeroing features may be disabled by specifying the destination register to be one of the individual 24-bit accumulator registers (A1 or B1). Note: Due to instruction pipelining, if an AGU register (Mn, Nn, or Rn) is directly changed with this instruction, the new contents may not be available for use until the second following instruction. See the restrictions discussed in A.9.
INSTRUCTION DESCRIPTIONS MOVEM MOVEM Move Program Memory Example: : MOVEM P:(R5+N5), LC : :move P:(R5+N5) into the loop counter (LC) Before Execution P:(R5 + N5) After Execution P:(R5 + N5) $000116 LC $000116 LC $0000 $0116 Explanation of Example: Prior to execution, the 16-bit loop counter (LC) register contains the value $0000, and the 24-bit program (P) memory location P:(R5+N5) contains the value $000116.
INSTRUCTION DESCRIPTIONS MOVEM MOVEM Move Program Memory Instruction Format: MOVE(M) S,P:ea MOVE(M) P:ea,D Opcode: 23 0 0 0 0 0 1 1 16 15 1 W 8 1 M M M R R R 7 1 0 0 d d d d d d OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: ea=6-bit Effective Address=MMMRRR Register W Read S Write D 0 1 Effective Addressing Mode M M M R R R (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 r r r r r r r 0 r r r r r r
INSTRUCTION DESCRIPTIONS MOVEM S,D X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B S d d d d d d S/L 0 0 0 1 0 0 no 0 0 0 1 0 1 no 0 0 0 1 1 0 no 0 0 0 1 1 1 no 0 0 1 0 0 0 no 0 0 1 0 0 1 no 0 0 1 0 1 0 no 0 0 1 0 1 1 no 0 0 1 1 0 0 no 0 0 1 1 0 1 no 0 0 1 1 1 0 yes 0 0 1 1 1 1 yes Move Program Memory D Sign Ext no no no no no no no no no no A2 B2 D Zero no no no no no no no no no no A0 B0 S,D R0 - R7 N0 - N7 M0 - M7 SR OMR SP SSH SSL LA LC MOVEM dddddd 010nnn 011nnn 100nnn 111001 111010 111011 111100 111101 111110
INSTRUCTION DESCRIPTIONS MOVEM MOVEM Move Program Memory Instruction Format: MOVE(M) S,P:aa MOVE(M) P:aa,D Opcode: 23 0 16 15 0 0 0 0 1 1 1 W 0 a a a a a 8 7 a 0 0 0 d d d d d d Instruction Fields: aa=6-bit Absolute Short Address=aaaaa Register W Read S 0 Write D 1 Absolute Short Address aaaaaa 000000 • • 111111 S,D X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B S d d d d d d S/L 0 0 0 1 0 0 no 0 0 0 1 0 1 no 0 0 0 1 1 0 no 0 0 0 1 1 1 no 0 0 1 0 0 0 no 0 0 1 0 0 1 no 0 0 1 0 1 0 no 0 0
INSTRUCTION DESCRIPTIONS MOVEP Operation: X:pp ➞ D Move Peripheral Data MOVEP Assembler Syntax: MOVEP X:pp,D X:pp ➞ X:ea MOVEP X:pp,X:ea X:pp ➞ Y:ea MOVEP X:pp,Y:ea X:pp ➞ P:ea MOVEP X:pp,P:ea S ➞ X:pp MOVEP S,X:pp #xxxxxx ➞ X:pp MOVEP #xxxxxx,X:pp X:ea ➞ X:pp MOVEP X:ea,X:pp Y:ea ➞ X:pp MOVEP Y:ea,X:pp P:ea ➞ X:pp MOVEP P:ea,X:pp Y:pp ➞ D MOVEP Y:pp,D Y:pp ➞ X:ea MOVEP Y:pp,X:ea Y:pp ➞ Y:ea MOVEP Y:pp,Y:ea Y:pp ➞ P:ea MOVEP Y:pp,P:ea S ➞ Y:pp MOVEP S,Y:pp #xxxxxx
INSTRUCTION DESCRIPTIONS MOVEP Move Peripheral Data MOVEP ister SSH is specified as a destination operand, the system stack pointer (SP) is preincremented by 1 before SSH is written. This allows the system stack to be efficiently extended using software stack pointer operations. When a 56-bit accumulator (A or B) is specified as a source operand S, the accumulator value is optionally shifted according to the scaling mode bits S0 and S1 in the system status register (SR).
INSTRUCTION DESCRIPTIONS MOVEP MOVEP Move Peripheral Data A MOVEP instruction which specifies SSH as the source operand or LA, LC, SSH, SSL, or SP as the destination operand cannot be used immediately before a DO instruction. A MOVEP instruction which specifies SSH as the source operand or LA, LC, SR, SSH, SSL, or SP as the destination operand cannot be used immediately before an ENDDO instruction.
INSTRUCTION DESCRIPTIONS MOVEP MOVEP Move Peripheral Data Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR For D=SR operand: S — Set according to bit 7 of the source operand L — Set according to bit 6 of the source operand E — Set according to bit 5 of the source operand U — Set according to bit 4 of the source operand N — Set according to bit 3 of the source operand Z — Set according to bit 2 of the source operand V —
INSTRUCTION DESCRIPTIONS MOVEP MOVEP Move Peripheral Data Instruction Format (X: or Y: Reference): MOVEP X:ea,X:pp MOVEP Y:ea,X:pp MOVEP #xxxxxx,X:pp MOVEP X:pp,X:ea MOVEP X:pp,Y:ea MOVEP X:ea,Y:pp MOVEP Y:ea,Y:pp MOVEP #xxxxxx,Y:pp MOVEP Y:pp,Y:ea MOVEP Y:pp,Y:ea Opcode: 23 0 0 0 0 1 0 0 16 15 s W 8 1 M M M R R R 7 1 0 S p p p p p p OPTIONAL EFFECTIVE ADDRESS EXTENSION A - 224 INSTRUCTION SET DETAILS MOTOROLA
INSTRUCTION DESCRIPTIONS MOVEP MOVEP Move Peripheral Data Instruction Fields: ea=6-bit Effective Address=MMMRRR, pp=6-bit I/O Short Address=pppppp Memory Space S X Memory Y Memory 0 1 Peripheral Space s X Memory 0 Y Memory 1 Peripheral Read Write W 0 1 Effective Addressing Mode M M M R R R (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) –(Rn) Absolute address Immediate data 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 0 0 r r r r r r r 0 1 r r r r r r r 0 0 r r r r r r r 0 0 where “rrr” refer
INSTRUCTION DESCRIPTIONS MOVEP MOVEP Move Peripheral Data Instruction Format (P: Reference): MOVEP P:ea,X:pp MOVEP X:pp,P:ea MOVEP P:ea,Y:pp MOVEP Y:pp,P:ea Opcode: 23 0 0 0 0 1 0 0 16 15 S W 8 1 M M M R R R 7 0 0 1 p p p p p p OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: ea=6-bit Effective Address=MMMRRR pp=6-bit I/O Short Address=pppppp Peripheral Space S X Memory Y Memory 0 1 Peripheral Read Write W 0 1 Effective Addressing Mode M M M R R R (Rn)-Nn (Rn)+Nn
INSTRUCTION DESCRIPTIONS MOVEP MOVEP Move Peripheral Data Instruction Format (Register Reference): MOVEP S,X:pp MOVEP X:pp,D MOVEP S,Y:pp MOVEP Y:pp,D Opcode: 23 0 16 15 0 0 0 1 0 0 S W 1 d d d d d 8 7 d 0 0 0 p p p p p p Instruction Fields: pp=6-bit I/O Short Address=pppppp Peripheral Space X Memory Y Memory S,D X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B S 0 1 Peripheral W Read 0 Write 1 S d d d d d d S/L 0 0 0 1 0 0 no 0 0 0 1 0 1 no 0 0 0 1 1 0 no 0 0 0 1 1 1 no 0 0 1 0 0 0 no 0 0
INSTRUCTION DESCRIPTIONS MPY MPY Signed Multiply Operation: ±S1∗S2 ➞ D (parallel move) ±S1∗S2 Assembler Syntax: MPY (±)S1,S2,D (parallel move) MPY (±)S2,S1,D (parallel move) ➞ D (parallel move) ±(S1∗2-n)➞D (no parallel move) MPY (±)S,#n,D (no parallel move) Description: Multiply the two signed 24-bit source operands S1 and S2 and store the resulting product in the specified 56-bit destination accumulator D.
INSTRUCTION DESCRIPTIONS MPY MPY Signed Multiply Explanation of Example 1: Prior to execution, the 24-bit X1 register contains the value $800000 (–1.0), the 24-bit Y1 register contains the value $C00000, (–0.5), and the 56-bit A accumulator contains the value $00:000000:000000 (0.0).
INSTRUCTION DESCRIPTIONS MPY MPY Signed Multiply Instruction Fields 1: S1∗S2 Q Q Q X0 X0 Y0 Y0 X1 X0 Y1 Y0 X0 Y1 Y0 X0 X1 Y0 Y1 X1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sign k D d + – 0 1 A 0 B 1 Note: Only the indicated S1∗S2 combinations are valid. X1∗X1 and Y1∗Y1 are not valid.
INSTRUCTION DESCRIPTIONS MPY MPY Signed Multiply Instruction Format 2: MPY (±)S,#n,D Opcode 2: 23 0 16 15 0 0 0 Instruction Fields: S Q Q Y1 X0 Y0 X1 0 0 1 1 0 1 0 1 0 0 0 1 0 0 0 s s Sign k D d + – 0 1 A B 0 1 n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 sssss 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 s s 8 7 s 1 0 1 Q Q d k 0 0 constant 0100000000000000
INSTRUCTION DESCRIPTIONS MPYR MPYR Signed Multiply and Round Operation: ±S1∗S2+r ➞ D (parallel move) Assembler Syntax: MPYR (±)S1,S2,D (parallel move) ±S1∗S2+r ➞ D (parallel move) MPYR (±)S2,S1,D (parallel move) ±(S1∗2-n)+r ➞ D (no parallel move) MPYR (±)S,#n,D (no parallel move) Description: Multiply the two signed 24-bit source operands S1 and S2 (or the signed 24-bit source operand S by the positive 24-bit immediate operand 2-n), round the result using convergent rounding, and store it in the s
INSTRUCTION SET DESCRIPTIONS MPYR MPYR Signed Multiply and Round Condition Codes: 15 14 13 LF DM T 12 11 10 9 8 7 6 5 4 3 2 1 0 ** S1 S0 I1 I0 S L E U N Z V C MR CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS MPYR Instruction Fields 1: Q Q Q S1∗S2 X0 X0 Y0 Y0 X1 X0 Y1 Y0 X0 Y1 Y0 X0 X1 Y0 Y1 X1 MPYR Signed Multiply and Round 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sign k D d + – A 0 B 1 0 1 Note: Only the indicated S1∗S2 combinations are valid. X1∗X1 and Y1∗Y1 are not valid.
INSTRUCTION SET DESCRIPTIONS MPYR MPYR Signed Multiply and Round Instruction Format 2: MPYR (±)S,#n,D Opcode 2: 23 0 16 15 0 0 0 0 0 0 Instruction Fields 2: S Q Q Sign Y1 X0 Y0 X1 0 0 1 1 0 1 0 1 + – n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 0 0 0 s s k D d 0 1 A B 0 1 sssss 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 s s 8 7 s 1 0 1 Q Q d k 0 1 consta
INSTRUCTION DESCRIPTIONS NEG NEG Negate Accumulator Operation: 0–D ➞ D (parallel move) Assembler Syntax: NEG D (parallel move) Description: Negate the destination operand D and store the result in the destination accumulator. This is a 56-bit, twos-complement operation.
INSTRUCTION SET DESCRIPTIONS NEG NEG Negate Accumulator Instruction Format: NEG D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 1 1 3 d 0 1 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: D d A B 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 237
INSTRUCTION DESCRIPTIONS NOP NOP No Operation Operation: PC+1➞PC Assembler Syntax: NOP Description: Increment the program counter (PC). Pending pipeline actions, if any, are completed. Execution continues with the instruction following the NOP. Example: : NOP : ;increment the program counter Explanation of Example: The NOP instruction increments the program counter and completes any pending pipeline actions.
INSTRUCTION SET DESCRIPTIONS NOP NOP No Operation Instruction Format: NOP Opcode: 23 0 16 15 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 Instruction Fields: None Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 239
INSTRUCTION DESCRIPTIONS NORM NORM Normalize Accumulator Iteration Operation: Assembler Syntax: If E • U • Z=1, then ASL D and Rn–1➞Rn NORM Rn,D else if E=1, then ASR D and Rn+1➞Rn else NOP where E denotes the logical complement of E, and where • denotes the logical AND operator Description: Perform one normalization iteration on the specified destination operand D, update the specified address register Rn based upon the results of that iteration, and store the result back in the destination accumulator
INSTRUCTION SET DESCRIPTIONS NORM NORM Normalize Accumulator Iteration cess in the R3 address register. A negative value reflects the number of left shifts performed; a positive value reflects the number of right shifts performed during the normalization process.
INSTRUCTION DESCRIPTIONS NOT NOT Logical Complement Operation: Assembler Syntax: D[47:24] ➞ D[47:24] (parallel move) NOT D (parallel move) where “—” denotes the logical NOT operator Description: Take the ones complement of bits 47–24 of the destination operand D and store the result back in bits 47–24 of the destination accumulator. This is a 24-bit operation. The remaining bits of D are not affected.
INSTRUCTION SET DESCRIPTIONS NOT NOT Logical Complement Instruction Format: NOT D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 0 1 3 d 0 1 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: D d A 0 B 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 243
INSTRUCTION DESCRIPTIONS OR OR Logical Inclusive OR Operation: Assembler Syntax: S+D[47:24] ➞ D[47:24] (parallel move) OR S,D (parallel move) where + denotes the logical inclusive OR operator Description: Logically inclusive OR the source operand S with bits 47–24 of the destination operand D and store the result in bits 47–24 of the destination accumulator. This instruction is a 24-bit operation. The remaining bits of the destination operand D are not affected.
INSTRUCTION SET DESCRIPTIONS OR OR Logical Inclusive OR Instruction Format: OR S,D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 1 J J 3 d 0 0 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S JJ X0 X1 Y0 Y1 00 10 01 11 Dd A0 B1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 245
INSTRUCTION DESCRIPTIONS ORI ORI OR Immediate with Control Register Operation: Assembler Syntax: #xx+D ➞ D OR(I) #xx,D where + denotes the logical inclusive OR operator Description: Logically OR the 8-bit immediate operand (#xx) with the contents of the destination control register D and store the result in the destination control register. The condition codes are affected only when the condition code register is specified as the destination operand.
INSTRUCTION SET DESCRIPTIONS ORI ORI OR Immediate with Control Register For MR and OMR operands: The condition codes are not affected using these operands.
INSTRUCTION DESCRIPTIONS REP REP Repeat Next Instruction Operation: LC ➞ TEMP; X:ea ➞ LC Repeat next instruction until LC=1 TEMP ➞ LC Assembler Syntax: REP X:ea LC ➞ TEMP; X:aa ➞ LC Repeat next instruction until LC=1 TEMP ➞ LC REP X:aa LC ➞ TEMP; Y:ea ➞ LC Repeat next instruction until LC=1 TEMP ➞ LC REP Y:ea LC ➞ TEMP; Y:aa ➞ LC Repeat next instruction until LC=1 TEMP ➞ LC REP Y:aa LC ➞ TEMP; S ➞ LC Repeat next instruction until LC=1 TEMP ➞ LC REP S LC ➞ TEMP; #xxx ➞ LC Repeat next instru
INSTRUCTION SET DESCRIPTIONS REP REP Repeat Next Instruction Restrictions: The REP instruction can repeat any single-word instruction except the REP instruction itself and any instruction that changes program flow. The following instructions are not allowed to follow an REP instruction: Immediately after REP DO Jcc JCLR JMP JSET JScc JSCLR JSR JSSET REP RTI RTS STOP SWI WAIT ENDDO Also, a REP instruction cannot be the last instruction in a DO loop (at LA).
INSTRUCTION DESCRIPTIONS REP REP Repeat Next Instruction Explanation of Example: Prior to execution, the 24-bit X0 register contains the value $000100, and the 16-bit loop counter (LC) register contains the value $0000. The execution of the REP X0 instruction takes the 24-bit value in the X0 register, truncates the MS 8 bits, and stores the 16 LS bits in the 16-bit loop counter (LC) register. Thus, the singleword MAC instruction immediately following the REP instruction is repeated $100 times.
INSTRUCTION SET DESCRIPTIONS REP REP Repeat Next Instruction Instruction Format: REP X:ea REP Y:ea Opcode: 23 0 16 15 0 0 0 0 1 1 0 0 8 1 M M M R R R 7 0 0 s 1 0 0 0 0 0 Instruction Fields: ea=6-bit Effective Address=MMMRRR, Effective Addressing Mode MM MRRR Memory Space s (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) 0 0 0 0 1 1 1 X Memory Y Memory 0 0 1 1 0 0 1 0 1 0 1 0 1 1 r r r r r r r r r r r r r r r r r r r r r 0 1 where “rrr” refers to an address register R0-
INSTRUCTION DESCRIPTIONS REP REP Repeat Next Instruction Instruction Format: REP X:aa REP Y:aa Opcode: 23 0 16 15 0 0 0 0 1 1 0 0 8 0 a a a a a a 7 0 0 s 1 0 0 0 0 0 Instruction Fields: aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory Space s X Memory Y Memory • • 0 1 111111 Timing: 4+mv oscillator clock cycles Memory: 1 program word A - 252 INSTRUCTION SET DETAILS MOTOROLA
INSTRUCTION SET DESCRIPTIONS REP REP Repeat Next Instruction Instruction Format: REP #xxx Opcode: 23 0 16 15 0 0 0 0 1 1 0 i 8 i i i i i i i 7 1 0 0 1 0 h h h h Instruction Fields: #xxx=12-bit Immediate Short Data = hhhh i i i i i i i i Immediate Short Data hhhh i i i i i i i i i 000000000000 • • 111111111111 Timing: 4+mv oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 253
INSTRUCTION DESCRIPTIONS REP REP Repeat Next Instruction Instruction Format: REP S Opcode: 23 0 16 15 0 0 0 0 1 1 0 1 8 1 d d d d d 7 d 0 0 0 1 0 0 0 0 0 Instruction Fields: S X0 X1 Y0 Y1 A0 B0 A2 B2 A1 B1 A B dddddd 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 S S/L S d d no R0 - R7 0 1 no N0 - N7 0 1 no M0 - M7 1 0 no SR 1 1 no OMR 1 1 no SP 1 1 no SSH 1 1 no SSL 1 1 no LA 1 1 no LC 1 1 yes (See Notes on page A-255) yes (See Notes on p
INSTRUCTION SET DESCRIPTIONS REP Repeat Next Instruction REP Notes: If A or B is specified as the destination operand, the following sequence of events takes place: 1. The S bit is computed according to its definition (See Section A.5 CONDITION CODE COMPUTATION) 2. The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR). 3.
INSTRUCTION DESCRIPTIONS RESET RESET Reset On-Chip Peripheral Devices Operation: Reset the interrupt priority register and all on-chip peripherals Assembler Syntax: RESET Description: Reset the interrupt priority register and all on-chip peripherals. This is a software reset which is NOT equivalent to a hardware reset since only on-chip peripherals and the interrupt structure are affected. The processor state is not affected, and execution continues with the next instruction.
INSTRUCTION SET DESCRIPTIONS RESET RESET Reset On-Chip Peripheral Devices Instruction Format: RESET Opcode: 23 0 16 15 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 7 1 0 0 0 0 0 1 0 0 Instruction Fields: None Timing: 4 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 257
INSTRUCTION DESCRIPTIONS RND RND Round Accumulator Operation: D+r ➞ D (parallel move) Assembler Syntax: RND D (parallel move) Description: Round the 56-bit value in the specified destination operand D and store the result in the MSP portion of the destination accumulator (A1 or B1). This instruction uses a convergent rounding technique.
INSTRUCTION SET DESCRIPTIONS RND RND Round Accumulator Convergent rounding differs from ‘‘standard’’ rounding in that convergent rounding attempts to remove the aforementioned positive bias by equally distributing the round-off error. The convergent rounding technique initially performs “standard” rounding as previously described. Again, the rounding constant depends on the scaling mode being used.
INSTRUCTION DESCRIPTIONS RND RND Round Accumulator Condition Codes: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF DM T ** S1 S0 I1 I0 S L E U N Z V C MR CCR S — Computed according to the definition in A.
INSTRUCTION SET DESCRIPTIONS RND RND Round Accumulator Instruction Format: RND D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 0 1 3 d 0 0 0 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: D D A B 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 261
INSTRUCTION DESCRIPTIONS ROL ROL Rotate Left 47 Operation: 24 C Assembler Syntax: (parallel move) ROL D (parallel move) Description: Rotate bits 47–24 of the destination operand D one bit to the left and store the result in the destination accumulator. Prior to instruction execution, bit 47 of D is shifted into the carry bit C, and, prior to instruction execution, the value in the carry bit C is shifted into bit 24 of the destination accumulator D. This instruction is a 24-bit operation.
INSTRUCTION DESCRIPTIONS ROL ROL Rotate Left Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS ROR 47 Operation: ROR Rotate Right 24 C Assembler Syntax: (parallel move) ROR D (parallel move) Description: Rotate bits 47–24 of the destination operand D one bit to the right and store the result in the destination accumulator. Prior to instruction execution, bit 24 of D is shifted into the carry bit C, and, prior to instruction execution, the value in the carry bit C is shifted into bit 47 of the destination accumulator D. This instruction is a 24-bit operation.
INSTRUCTION DESCRIPTIONS ROR ROR Rotate Right Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during parallel move N — Set if bit 47 of A or B result is set Z — Set if bits 47–24 of A or B result are zero V — Always cleared C — Set if bit 24 of A or B was set prior to instruction execution.
INSTRUCTION DESCRIPTIONS RTI Return from Interrupt Operation: SSH ➞ PC; SSL ➞ SR; SP–1 ➞ SP RTI Assembler Syntax: RTI Description: Pull the program counter (PC) and the status register (SR) from the system stack. The previous program counter and status register are lost.
INSTRUCTION DESCRIPTIONS RTI RTI Return from Interrupt Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Set according to the value pulled from the stack L — Set according to the value pulled from the stack E — Set according to the value pulled from the stack U — Set according to the value pulled from the stack N — Set according to the value pulled from the stack Z — Set according to the value pulled from the stack
INSTRUCTION DESCRIPTIONS RTS RTS Return from Subroutine Operation: SSH ➞ PC; SP–1 ➞ SP Assembler Syntax: RTS Description: Pull the program counter (PC) from the system stack. The previous program counter is lost. The status register (SR) is not affected.
INSTRUCTION DESCRIPTIONS RTS RTS Return from Subroutine Instruction Format: RTI Opcode: 23 0 16 15 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 7 0 0 0 0 0 1 1 0 0 Instruction Fields: None Timing: 4+rx oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 269
INSTRUCTION DESCRIPTIONS SBC Subtract Long with Carry Operation: D–S–C ➞ D (parallel move) SBC Assembler Syntax: SBC S,D (parallel move) Description: Subtract the source operand S and the carry bit C of the condition code register from the destination operand D and store the result in the destination accumulator. Long words (48 bits) may be subtracted from the (56-bit) destination accumulator.
INSTRUCTION DESCRIPTIONS SBC Subtract Long with Carry SBC Explanation of Example: This example illustrates long-word double-precision (96-bit) subtraction using the SBC instruction. Prior to execution of the SUB and SBC instructions, the 96-bit value $000000:000001:800000:000000 is loaded into the Y and X registers (X:Y), respectively. The other double-precision 96-bit value $000000:000003:000000:000000 is loaded into the B and A accumulators (B:A), respectively.
INSTRUCTION DESCRIPTIONS SBC SBC Subtract Long with Carry Condition Codes: 15 14 13 12 LF DM T ** MR 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS SBC SBC Subtract Long with Carry Instruction Format: SBC S,D Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 1 J 3 d 0 1 0 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S,D J d X,A X,B Y,A Y,B 00 01 10 11 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 273
INSTRUCTION DESCRIPTIONS STOP Stop Instruction Processing Operation: Enter the stop processing state and stop the clock oscillator STOP Assembler Syntax: STOP Description: Enter the STOP processing state. All activity in the processor is suspended until the RESET or IRQA pin is asserted. The clock oscillator is gated off internally. The STOP processing state is a low-power standby state. During the STOP state, port A is in an idle state with the control signals held inactive (i.e., RD=WR=VCC etc.
INSTRUCTION DESCRIPTIONS STOP STOP Stop Instruction Processing Restrictions: A STOP instruction cannot be used in a fast interrupt routine. A STOP instruction cannot be the last instruction in a DO loop (i.e., at LA). A STOP instruction cannot be repeated using the REP instruction. Example: : STOP : ;enter low-power standby mode Explanation of Example: The STOP instruction suspends all processor activity until the processor is reset or interrupted as previously described.
INSTRUCTION DESCRIPTIONS SUB SUB Subtract Operation: D–S ➞ D (parallel move) Assembler Syntax: SUB S,D (parallel move) Description: Subtract the source operand S from the destination operand D and store the result in the destination operand D. Words (24 bits), long words (48 bits), and accumulators (56 bits) may be subtracted from the destination accumulator.
INSTRUCTION DESCRIPTIONS SUB SUB Subtract Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS SUBL Shift Left and Subtract Accumulators Operation: 2∗D–S ➞ D (parallel move) SUBL Assembler Syntax: SUBL S,D (parallel move) Description: Subtract the source operand S from two times the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the left, and a zero is shifted into the LS bit of D prior to the subtraction operation.
INSTRUCTION DESCRIPTIONS SUBL SUBL Shift Left and Subtract Accumulators Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS SUBR Shift Right and Subtract Accumulators Operation: D/2–S ➞ D (parallel move) SUBR Assembler Syntax: SUBR S,D (parallel move) Description: Subtract the source operand S from one-half the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the right while the MS bit of D is held constant prior to the subtraction operation.
INSTRUCTION DESCRIPTIONS SUBR SUBR Shift Right and Subtract Accumulators Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS SWI Software Interrupt Operation: Begin SWI exception processing SWI Assembler Syntax: SWI Description: Suspend normal instruction execution and begin SWI exception processing. The interrupt priority level (I1,I0) is set to 3 in the status register (SR) if a long interrupt service routine is used. Restrictions: An SWI instruction cannot be used in a fast interrupt routine. An SWI instruction cannot be repeated using the REP instruction.
INSTRUCTION DESCRIPTIONS SWI SWI Software Interrupt Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR The condition codes are not affected by this instruction.
INSTRUCTION DESCRIPTIONS Tcc Tcc Transfer Conditionally Operation: If cc, then S1 ➞ D1 Assembler Syntax: Tcc S1,D1 If cc, then S1 ➞ D1 and S2 ➞ D2 Tcc S1,D1 S2,D2 Description: Transfer data from the specified source register S1 to the specified destination accumulator D1 if the specified condition is true. If a second source register S2 and a second destination register D2 are also specified, transfer data from address register S2 to address register D2 if the specified condition is true.
INSTRUCTION DESCRIPTIONS Tcc Tcc Transfer Conditionally tion accumulator D1. If address register S2 is used as an address pointer into an array of data, the address of the desired value is stored in the address register D2. The Tcc instruction may be used after any instruction and allows efficient searching and sorting algorithms. The Tcc instruction uses the internal data ALU paths and internal address ALU paths. The Tcc instruction does not affect the condition code bits.
INSTRUCTION DESCRIPTIONS Tcc Tcc Transfer Conditionally Instruction Format: Tcc S1,D1 Opcode: 23 0 16 15 0 0 0 0 0 1 0 C 8 C C C 0 0 0 C 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 0 7 0 0 J J J D 0 0 0 Instruction Fields: cc=4=bit condition code=CCCC S1,D1 B,A A,B X0,A X0,B X1,A X1,B Y0,A Y0,B Y1,A Y1,B J 0 0 1 1 1 1 1 1 1 1 J 0 0 0 0 1 1 0 0 1 1 J 0 0 0 0 0 0 1 1 1 1 D 0 1 0 1 0 1 0 1 0 1 Mnemonic CC (HS) GE NE PL NN EC LC GT C 0 0 0 0 0 0 0 0 C 0 0 0 0 1 1 1 1 Mnemonic C C C C
INSTRUCTION DESCRIPTIONS Tcc Tcc Transfer Conditionally Instruction Format: Tcc S1,D1 S2,D2 Opcode: 23 0 16 15 0 0 0 0 0 1 1 C 8 C C C 0 t t C 0 0 0 0 0 0 0 0 C 0 0 0 0 1 1 1 1 t 7 0 0 J J J D T T T Instruction Fields: cc=4=bit condition code=CCCC S1,D1 B,A A,B X0,A X0,B X1,A X1,B Y0,A Y0,B Y1,A Y1,B J 0 0 1 1 1 1 1 1 1 1 J 0 0 0 0 1 1 0 0 1 1 J 0 0 0 0 0 0 1 1 1 1 D 0 1 0 1 0 1 0 1 0 1 S2 t t t Rn n n n D2 T T T Rn n n n Mnemonic CC (HS) GE NE PL NN EC LC GT C 0 0 1 1
INSTRUCTION DESCRIPTIONS TFR TFR Transfer Data ALU Register Operation: S➞D (parallel move) Assembler Syntax: TFR S,D (parallel move) Description: Transfer data from the specified source data ALU register S to the specified destination data ALU accumulator D. TFR uses the internal data ALU data paths; thus, data does not pass through the data shifter/limiters.
INSTRUCTION DESCRIPTIONS TFR TFR Transfer Data ALU Register Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR S — Computed according to the definition in A.
INSTRUCTION DESCRIPTIONS TST TST Test Accumulator Operation: S–0 (parallel move) Assembler Syntax: TST S (parallel move) Description: Compare the specified source accumulator S with zero and set the condition codes accordingly. No result is stored although the condition codes are updated.
INSTRUCTION DESCRIPTIONS TST TST Test Accumulator Instruction Format: TST S Opcode: 23 8 DATA BUS MOVE FIELD 7 0 4 0 0 0 3 d 0 0 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: S d A B 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 291
INSTRUCTION DESCRIPTIONS WAIT Wait for Interrupt WAIT Operation: Assembler Syntax: Disable clocks to the processor core and WAIT enter the WAIT processing state. Description: Enter the WAIT processing state. The internal clocks to the processor core and memories are gated off, and all activity in the processor is suspended until an unmasked interrupt occurs. The clock oscillator and the internal I/O peripheral clocks remain active.
INSTRUCTION DESCRIPTIONS WAIT WAIT Wait for Interrupt Condition Codes: 15 14 13 12 LF DM T ** 11 10 9 8 7 6 5 4 S1 S0 I1 I0 S L E U MR 3 2 1 0 N Z V C CCR The condition codes are not affected by this instruction.
APPENDIX B BENCHMARK PROGRAMS T T T P1 T T P2 P4 T T MOTOROLA P3 BENCHMARK PROGRAMS T B-1
SECTION CONTENTS SECTION B.1 INTRODUCTION ........................................................................3 SECTION B.2 BENCHMARK PROGRAMS ......................................................
INTRODUCTION B.1 INTRODUCTION Table B-1 provides benchmark numbers for 18 common DSP programs implemented on the 27-MHz DSP56001. The four code examples shown in Figures B-1 to B-4 represent the benchmark programs shown in Table B-1. B.2 BENCHMARK PROGRAMS Figure B-1 is the code for the 20-tap FIR filter shown in Table B-1. Figure B-2 is the code for an FFT using a triple nested DO LOOP.
BENCHMARK PROGRAMS Table B-1 27-MHz Benchmark Results for the DSP56001R27 Benchmark Program Memory Size (Words) Number of Clock Cycles 20 - Tap FIR Filter 500.0 kHz 50 54 64 - Tap FIR Filter 190.1 kHz 138 142 67 - Tap FIR Filter 182.4 kHz 144 148 8 - Pole Cascaded Canonic Biquad IIR Filter (4x) 540.0 kHz 40 50 8 - Pole Cascaded Canonic Biquad IIR Filter (5x) 465.5 kHz 45 58 8 - Pole Cascaded Transpose Biquad IIR Filter 385.7 kHz 48 70 Dot Product 444.
BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B-5
BENCHMARK PROGRAMS page 132,66,0,6 opt rc ;******************************************************** ;Motorola Austin DSP Operation June 30, 1988 ;******************************************************** ;DSP56000/1 ;20 - tap FIR filter ;File name: 1-56.asm ;********************************************************************************************************************* ; Maximum sample rate: 379.6 kHz at 20.5 MHz/500.0 kHz at 27.
BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B-7
BENCHMARK PROGRAMS ; ; ; ;********************************************************************************************************************* ; ; initialization ;**************************************** n equ 20 start equ $40 wddr equ $0 cddr equ $0 input equ $ffe0 output equ $ffe1 ; org p:start move #wddr,r0 ;r0 ➡ samples move #cddr,r4 ;r1 ➡ coefficients move #n-1,m0 ;set modulo arithmetic move m0,m4 ;for the 2 circular buffers ; opt cc ; filter loop :8+(n-1) cycles ;************************************
BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B-9
BENCHMARK PROGRAMS ;This program originally available on the Motorola DSP bulletin board. ;It is provided under a DISCLAIMER OF WARRANTY available from ;Motorola DSP Operation, 6501 William Cannon Drive, Austin, TX, 78735 ; ;Radix-2, In-Place, Decimation-In-Time FFT (smallest code size). ; ;Last Update 30 Sep 86 Version 1.
BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B - 11
BENCHMARK PROGRAMS ;Latest Revision — September 30, 1986 ; move #points/2,n0 move #1,n2 move #points/4,n6 move #-1,m0 move m0,m1 move m0,m4 move m0,m5 move #0,m6 ;initialize butterflies per group ;initialize groups per pass ;initialize C pointer offset ;initialize A and B address modifiers ;for linear addressing ;initialize C address modifier for ;reverse carry (bit-reversed) addressing ; ;Perform all FFT passes with triple nested DO loop ; do #@cvi (@log(points)/@log(2)+0.
BENCHMARK PROGRAMS Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 2 of 8) MOTOROLA BENCHMARK PROGRAMS B - 13
BENCHMARK PROGRAMS page 132,66,0,6 opt rc ;********************************************************** ;Motorola Austin DSP Operation June 30, 1988 *********************************************************** ;DSP56000/1 ;8-pole 4-multiply cascaded canonic IIR filter ;File name: 4-56.asm ;********************************************************************************************************************** ; Maximum sample rate: 410.0 kHz at 20.5 MHz/540.0 kHz at 27.
BENCHMARK PROGRAMS Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 4 of 8) MOTOROLA BENCHMARK PROGRAMS B - 15
BENCHMARK PROGRAMS ; All coefficients are divided by 2: ; w(n)/2=x(n)/2-ai1/2*w(n-1)-ai2/2*w(n-2) ; y(n)/2=w(n)/2+bi1/2*w(n-1)+bi2/2*w(n-2) ; ; X Memory Organization Y Memory Organization ; b1N/2 Coef. + 4*nsec - 1 ; b2N/2 ; a1N/2 ; a2N/2 ; wN(n-1) Data + 2*nsec - 1 • ; wN(n-2) • ; • b11/2 ; • b21/2 ; w1(n-1) a11/2 ; R0 ➡ w1(n-2) Data R4 ➡ a21/2 Coef.
BENCHMARK PROGRAMS Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 6 of 8) MOTOROLA BENCHMARK PROGRAMS B - 17
BENCHMARK PROGRAMS page 132,60,1,1 ;newlms2n.asm ; New Implementation of the delayed LMS on the DSP56000 Revision C ;Memory map: ; Initial X H ; x(n) x(n-1) x(n-2) x(n-3) x(n-4) hx h0 h1 h2 ; ] ] ] ; r0 r5 r4 ;hx is an unused value to make the calculations faster.
BENCHMARK PROGRAMS Real input FFT based on Glenn Bergland algorithm ; ; Normal order input and normal order output. ; ; Since 56001 does not support bergland addressing, extra instruction cycles are needed ; for converting bergland order to normal order. It has been done in the last pass by ; looking at the bergtable.
BENCHMARK PROGRAMS ; Main program to call the rfft-56b macro ; Argument list ; ; Latest modifying date - 4-March-92 reset start points binlogsz idata odata bergtable twiddle equ equ equ equ equ equ equ equ bergsincos points,odata ;generate normal order twiddle factors with size of points/4 opt org jmp bergorder norm2berg order bergorder rifft 0 $40 512 9 $000 $400 $600 $800 mex p:reset start org p:start movep #0,x:$fffe ;0 wait states points/4,bergtable,odata ;generates bergland table for twiddle fa
BENCHMARK PROGRAMS count ount count count set 0 dup points/4 dc @cos(@cvf(count)*freq) set count+1 endm org x:coef set 0 dup points/4 dc @sin(@cvf(count)*freq) set count+1 endm endm ;end of bergsincos macro bergorder macro points,bergtable,offset bergorder ident 1,3 ;bergorder generates bergland order table move move #>4,a #points,r4 move move move move move move move move move move move move do move lsr move nop move lsl move move cmp jle move move move #>points/4,b ;nitial pointer #bergtable,r0
BENCHMARK PROGRAMS _loop _endl sub move move add move nop move add move move jmp move y0,a b,x1 r0,y0 y0,b b,r0 ;k-bergtabl[j] ;save b, x1=i ;y0=j=i+i ;b=j+i ;r0=j+i a,x:(r0+n0) x1,b b,x0 x1,b _star y1,a ;store bergtabl[j+i] ;b=j+i+i ;save b ;recover b=i move #>offset,a move #bergtable,r0 do #points,_add_offset move x:(r0),B add A,B move B,x:(r0)+ ;recover a ;offset is the location of output data or twiddle _add_offset endm ;end of sincos macro ;convert normal order to berglang order norm2berg ma
BENCHMARK PROGRAMS move #twiddle+1,r7 lua (r0)+n0,r1 move r0,r4 move r1,r5 move #1,r3 move x:(r0),A y:(r4),y0 do n0,pass1 ; -----------------------------------------------; First Pass -- W(n) = 1 ; ; A---\ /---A’= Re[ A + jB + (C + jD) ] = A + C ; B----\_|_/----B’= Im[ A + jB + (C + jD) ] =j(D + B) ; C----/ | \----C’= Re[ A + jB - (C + jD) ] = A - C ; D---/ \---D’= Im[-A - jB + (C + jD) ] =j(D - B) ;------------------------------------------------; sub y0,A x:(r1),x0 y:(r5),B add x0,B A,x:(r1)+ y:(r5),A su
BENCHMARK PROGRAMS lua move (r0)+n0,r1 r1,r5 ;r1 ptr to next group b ;r5 ptr to next group d ; Intermediate Passes -- W(n) < 1 ; ; A---\ /---A’= Re[ A + jC + (B - jD)W(k) ] = A+BWr+DWi=A+T1 ; B----\_|_/----B’= Im[ A + jC - (B - jD)W(k) ] = C+DWr-BWi=T2+C ; C----/ | \----C’= Re[ A + jC - (B - jD)W(k) ] = A-(BWr+DWi)=A-T1 ; D---/ \---D’= Im[-A - jC - (B - jD)W(k) ] = -C+DWr-BWi=T2-C ; ______________________________ move x:(r2)+,x0 y:(r6)+,y0 ;x0=Wi, y0=Wr move x:(r1)-,x1 y:(r5),y1 ;x1=b,y1=d move x:(r1),B
BENCHMARK PROGRAMS ; Intermediate Passes -- W(n) < 1 ; ; A---\ /---A’= Re[ A + jC + (B - jD)W(k) ] = A+BWr+DWi=A+T1 ; B----\_|_/----B’= Im[ A + jC - (B - jD)W(k) ] = C+DWr-BWi=T2+C ; C----/ | \----C’= Re[ A + jC - (B - jD)W(k) ] = A-(BWr+DWi)=A-T1 ; D---/ \---D’= Im[-A - jC - (B - jD)W(k) ] = -C+DWr-BWi=T2-C ; ______________________________ move x:(r0)+,x1 y:(r4)-,y1 ;x1=b, y1=d, r4 ptr back to c mpy x1,y0,B x:(r3)+,r7 ;A=bWr, mac x0,y1,B x:(r3)+,r1 ;B=bWr+dWi=T1, get first index sub B,A ;A=a-T1=c’, get se
BENCHMARK PROGRAMS ; 1024 49776 ;-----------------------------------------------------------------; ; Memory (word) ;---------------------------------------------------------------; P memory X memory ; 87 points/2+ (real input) ; points/4+ (SIN table) ; points/2+ (real output) ; points/2 (bergtable) ;---------------------------------------------------------------- B - 26 BENCHMARK PROGRAMS Y memory points/2+ (imaginary input ) points/4+ (COS table) points/2 (imaginary output) MOTOROLA
DSP56100 Family Manual Trouble Report DSP Applications Fax Number — (512) 891-4665 Dr. BuB Bulletin Board —891-DSP3 (8 data bits, no parity, 1 stop) We welcome your comments and suggestions. They help us provide you with better product documentation. Please send your suggestions/corrections to the Fax number or Email address above or mail this completed form to: Motorola Inc. 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Attn: Digital Signal Processing Documentation 1.
DSP56100 Family Manual Trouble Report 2. Did you find the manual clear and easy to use? Please comment on specific sections that you feel need improvement. 3. What sections of this manual do you consider most important/least important.
INDEX —A— A Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Aborted Instructions . . . . . . . . . . . . . . . . . . . . 7-25 ABS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-22 Absolute Address . . . . . . . . . . . . . . . . . . . . . . 6-14 Absolute Short . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . 3-9 Accumulators, A and B . .
Index (Continued) zero (bit 2) . . . . . . . . . . . . . . . . . . . .5-10, A-17 Condition Codes . . . . . . . . . . . . . . . . . . . . . . . .A-3 Convergent Rounding . . . . . . . . . . . . . . . . . . . . 3-6 —D— Data ALU double precision multiply mode . . . . . . . . 3-16 MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 MAC and logic unit . . . . . . . . . . . . . . . . . . 3-6 programming model . . . . . . . . . . . . . . . . 3-19 summary . . . . . . . . . . . . . . . . . . . . . . .
Index (Continued) —H— Hardware DO Loop . . . . . . . . . . . . . . . . 6-24, A-88 Hardware Interrupt . . . . . . . . . . . . . . . . . . . . . 7-11 Hardware Interrupt Sources . . . . . . . . . . . . . . 7-16 IRQA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 IRQB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Hardware Reset OnCE pins and . . . . . .
Index (Continued) Low Power Divider (LPD) . . . . . . . . . . . . . . . . . 9-5 LSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-144 LSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-146 LUA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-148 —M— MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6, 3-13 MAC Instruction . . . . . . . . . . . . . . . . . . . . . .A-150 MACR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index (Continued) PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Phase-Locked Loop (PLL) . . . . . . . . . . . . 2-6, 9-3 PINIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6, 9-3 frequency multiplier . . . . . . . . . . . . . . . . . . 9-5 hardware reset and . . . . . . . . . . . . . . . . . 9-11 introduction . . . . . . . .
Index (Continued) —S— Saturation Arithmetic . . . . . . . . . . . . . . . . . . . . 3-9 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-270 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Scaling Bit . . . . . . . . . . . . . . . . . . . . . . . 5-11, A-16 Scaling Mode Bits . . . . . . . . . . . . . . . . . . . . . . 5-12 SD Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 Short Jump . . . . . . . . . . . . . . . . . . . . . . . . . . .
