user manual

INSTRUCTION FORMATS
MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 7
6.3.2.2 AGU Registers
The 24 AGU registers are 16 bits wide. They may be accessed as word operands for
address, address modifier, and data storage. When used as a source operand, these reg-
isters occupy the low-order portion of the 24-bit word; the high-order portion is read as
zeros (see Figure 6-5). When used as a destination operand, these registers receive the
low-order portion of the word; the high-order portion is not used. The notation “Rn” desig-
nates one of the eight address registers, R0–R7; the notation “Nn” designates one of the
eight address offset registers, N0–N7; and the notation “Mn” designates one of the eight
Figure 6-4 Reading and Writing the ALU Extension Registers
23 8 7 0
23 8 7 0
23 8 7 0
BUS
NOT USED
LSB OF
WORD
A2
BUS
REGISTER A2, B2 USED
AS A DESTINATION
REGISTER A2, B2
USED AS A SOURCE
SIGN EXTENSION
OF A2
CONTENTS
OF A2
NOT USED
REGISTER A2, B2
Figure 6-5 Reading and Writing the Address ALU Registers
23 0
BUS
NOT USED
23 16 15 0
BUS
ADDRESS ALU
ADDRESS ALU REGISTERS
AS A DESTINATION
AS A SOURCE
ADDRESS ALU REGISTERS
15 0
ZERO FILL
REGISTERS
LSB OF
WORD