user manual

OnCE CONTROLLER AND SERIAL INTERFACE
10- 8 ON-CHIP EMULATION (OnCE) MOTOROLA
10.3.1.1 Register Select (RS4-RS0) Bits 0-4
The Register Select bits define which register is source (destination) for the read (write)
operation. Table 10-2 indicates the OnCE register addresses.
Table 10-2 OnCE Register Addressing
RS4-RS0 Register Selected
00000 OnCE Status and Control Register (OSCR)
00001 Memory Breakpoint Counter (OMBC)
00010 Reserved
00011 Trace Counter (OTC)
00100 Reserved
00101 Reserved
00110 Memory Upper Limit Register (OMULR)
00111 Memory Lower Limit Register (OMLLR)
01000 GDB Register (OGDBR)
01001 PDB Register (OPDBR)
01010 PAB Register for Fetch (OPABFR)
01011 PIL Register (OPILR)
01100 Clear Memory Breakpoint Counter (OMBC)
01101 Reserved
01110 Clear Trace Counter (OTC)
01111 Reserved
10000 Reserved
10001 Program Address Bus FIFO and Increment Counter
10010 Reserved
10011 PAB Register for Decode (OPABDR)
101xx Reserved
11xx0 Reserved
11x0x Reserved
110xx Reserved
11111 No Register Selected
RS0
0
RS1
1
RS2
2
RS3
3
RS4
4
EX
5
GO
6
R/W
7
Figure 10-4 OnCE Command Register