DSP56301 User’s Manual 24-Bit Digital Signal Processor DSP56301UM/AD Revision 3, March 2001
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Overview 1 Signals/Connections 2 Memory Configuration 3 Core Configuration 4 Programming the Peripherals 5 Host Interface (HI32) 6 Enhanced Synchronous Serial Interface (ESSI) 7 Serial Communications Interface (SCI) 8 Triple Timer Module 9 Bootstrap Program A Programming Reference B
1 Overview 2 Signals/Connections 3 Memory Configuration 4 Core Configuration 5 Programming the Peripherals 6 Host Interface (HI32) 7 Enhanced Synchronous Serial Interface (ESSI) 8 Serial Communications Interface (SCI) 9 Triple Timer Module A Bootstrap Program B Programming Reference
Contents Chapter 1 Overview 1.1 Manual Organization ............................................................................................................. 1-1 1.2 Manual Conventions .............................................................................................................. 1-2 1.3 DSP56300 Core Features....................................................................................................... 1-4 1.4 DSP56300 Core Functional Blocks ......................................
2.8 2.9 2.10 2.11 2.12 Enhanced Synchronous Serial Interface 0 ........................................................................... 2-22 Enhanced Synchronous Serial Interface 1 ........................................................................... 2-25 Serial Communications Interface (SCI)............................................................................... 2-27 Timers .....................................................................................................................
4.9 4.10 JTAG Identification (ID) Register ....................................................................................... 4-35 JTAG Boundary Scan Register (BSR)................................................................................. 4-35 Chapter 5 Programming the Peripherals 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 Peripheral Initialization Steps ................................................................................................
6.7.10 DSP Host Port GPIO Direction Register (DIRH)................................................................ 6-43 6.7.11 DSP Host Port GPIO Data Register (DATH) ...................................................................... 6-43 6.8 Host-Side Programming Model ........................................................................................... 6-44 6.8.1 HI32 Control Register (HCTR) ........................................................................................... 6-48 6.8.
7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.6 7.6.1 7.6.2 7.6.3 ESSI Control Register A (CRA) .......................................................................................... 7-14 ESSI Control Register B (CRB) .......................................................................................... 7-18 ESSI Status Register (SSISR).............................................................................................. 7-28 ESSI Receive Shift Register ....................
Chapter 9 Triple Timer Module 9.1 Overview................................................................................................................................ 9-1 9.1.1 Triple Timer Module Block Diagram .................................................................................... 9-2 9.1.2 Individual Timer Block Diagram........................................................................................... 9-2 9.2 Operation ..............................................................
Figures 1-1 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 4-2 4-4 4-3 4-5 4-6 4-7 4-8 4-9 4-10 4-11 5-1 5-2 5-3 5-4 5-5 5-6 6-1 6-2 6-3 6-4 6-5 6-6 6-7 DSP56301 Block Diagram ................................................................................... 1-11 Signals Identified by Functional Group ................................................................. 2-2 Host Interface/Port B Detail Signal Diagram......................................................... 2-3 Default Settings (0, 0, 0).........
6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 8-1 8-2 8-3 xii DSP PCI Address Register (DPAR)..................................................................... 6-33 DSP Status Register (DSR) .................................................................................. 6-35 DSP PCI Status Register (DPSR).........................................................................
8-4 8-5 8-6 8-7 8-8 8-9 8-10 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 SCI Clock Control Register (SCCR).................................................................... 8-19 SCI Baud Rate Generator ..................................................................................... 8-20 16 x Serial Clock ..................................................................................................
B-9 B-10 B-11 B-12 B-13 B-14 B-15 B-16 B-17 B-18 B-19 B-20 B-21 B-22 B-23 B-24 B-25 B-26 B-27 B-28 B-29 B-30 B-31 xiv DMA Control Registers 5–0 (DCR[5–0]) ............................................................B-21 DSP Control Register (DCTR).............................................................................B-22 DSP PCI Control Register (DPCR)......................................................................B-23 DSP PCI Master Control Register (DPMC).....................................
Tables 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 High True/Low True Signal Conventions ................................................................. 1-2 DSP56301 Switch Memory Configuration.............................................................. 1-10 DSP56301 Documentation ......................................................................................
6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 7-1 7-2 7-3 7-4 7-5 7-6 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 9-4 B-1 B-2 B-3 B-4 xvi DSP Control Register (DCTR) Bit Definitions ....................................................... 6-23 DSP PCI Control Register (DPCR) Bit Definitions ................................................ 6-27 DSP PCI Master Control Register (DMPC) Bit Definitions ...................................
Chapter 1 Overview This manual describes the DSP56301 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56301 is an implementation of the DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals. Use this manual in conjunction with the DSP56300 Family Manual (DSP56300FM/AD), which describes the CPU, core programming models, and instruction set details.
Manual Conventions n Chapter 6, Host Interface (HI32) HI32 features, signals, architecture, programming model, reset, interrupts, external host programming model, initialization, and a quick reference to the HI32 programming model. n Chapter 7, Enhanced Synchronous Serial Interface (ESSI) Enhancements, data and control signals, programming model, operating modes, initialization, exceptions, and GPIO.
Manual Conventions Table 1-1. High True/Low True Signal Conventions Signal/Symbol Logic State Signal State Voltage PIN True Asserted VCC3 PIN False Deasserted Ground2 1. PIN is a generic term for any pin on the chip. 2. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low). VCC is an acceptable high voltage level.
DSP56300 Core Features 1.3 DSP56300 Core Features All DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard predesigned elements, such as memories and peripherals. New modules can be added to the library to meet customer specifications. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations.
DSP56300 Core Features n Phase Lock Loop (PLL)—Allows change of low power Divide Factor (DF) without loss of lock n Output clock with skew elimination n Hardware debugging support n — On-Chip Emulation (OnCE) module — Joint Action Test Group (JTAG) Test Access Port (TAP) port — Address Trace mode reflects internal Program RAM accesses at the external port On-chip memories: — Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable: Program RAM Size Instruction Cache Size X
DSP56300 Core Functional Blocks n — Serial Communications Interface (SCI) with baud rate generator — Triple timer module — Up to forty-two programmable General Purpose Input/Output (GPIO) pins, depending on which peripherals are enabled Reduced power dissipation — — — — Very low power CMOS design Wait and Stop low-power standby modes Fully-static logic Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) 1.
DSP56300 Core Functional Blocks 1.4.1.1 Data ALU Registers The data ALU registers are read or written over the X data bus and the Y data bus as 16- or 24-bit operands. The source operands for the data ALU can be 24, 48, or 56 bits in 24-bit mode or 16, 32, or 40 bits in 16-bit mode. They always originate from data ALU registers. The results of all data ALU operations are stored in an accumulator.
DSP56300 Core Functional Blocks arithmetic used in the address register update calculation. The modifier value is decoded in the address ALU. 1.4.3 Program Control Unit (PCU) The PCU prefetches and decodes instructions, controls hardware DO loops, and processes exceptions. Its seven-stage pipeline controls the different processing states of the DSP56300 core.
DSP56300 Core Functional Blocks 1.4.4 PLL and Clock Oscillator The clock generator in the DSP56300 core comprises two main blocks: the PLL, which performs clock input division, frequency multiplication, and skew elimination; and the clock generator, which performs low-power division and clock pulse generation.
Internal Buses 1.4.6 On-Chip Memory The memory space of the DSP56300 core is partitioned into program, X data, and Y data memory space. The data memory space is divided into X and Y data memory in order to work with the two address ALUs and to feed two operands simultaneously to the data ALU. Memory space includes internal RAM and ROM and can be expanded off-chip under software control. There is an on-chip 192/3K x 24-bit bootstrap ROM. For details on internal memory, see Chapter 3, Memory Configuration.
DMA The block diagram in Figure 1-1 illustrates these buses among other components.
Peripherals 1.7 Peripherals In addition to the core features, the DSP56301 provides the following peripherals: n n n n n As many as 42 user-configurable General-Purpose Input/Output (GPIO) signals Host Interface (HI32) Dual Enhanced Synchronous Serial Interfaces (ESSI0 and ESSI1) Serial Communications Interface (SCI) Triple timer module 1.7.
Peripherals 1.7.4 Serial Communications Interface (SCI) The SCI provides a full-duplex port for serial communications with other DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without additional logic to peripherals that use TTL-level signals. With a small amount of additional logic, the SCI can connect to peripheral interfaces that have non-TTL level signals, such as the RS-232C, RS-422, and so forth.
Related Documents and Web Sites 1.8 Related Documents and Web Sites The documents listed in Table 1-3 are required for a complete description of the DSP56301 and are necessary to design properly with the part. Documentation is available from the following sources (see back cover for detailed information): n A local Motorola distributor n A Motorola semiconductor sales office n A Motorola Literature Distribution Center n The World Wide Web (WWW) Table 1-3.
Chapter 2 Signals/Connections The DSP56301 input and output signals are organized into functional groups, as shown in Table 2-1. Two different configurations are illustrated in Figure 2-1 and Figure 2-2. The difference between these two configurations is the host port functionality. Although the DSP56301 operates from a 3.3 volt supply, some of the input pins can tolerate 5 volts. A special notice for this feature is added to the description of these pins. Table 2-1.
DSP56301 VCCP VCCQ VCCA VCCD VCCC VCCH VCCS GNDP GND1P GNDQ GNDA GNDD GNDN GNDH GNDS 4 6 4 2 6 2 4 6 4 2 6 2 EXTAL XTAL Power Inputs: PLL Internal Logic Address Bus Data Bus Bus Control HI32 ESSI/SCI/Timer Grounds: PLL PLL Internal Logic Address Bus Data Bus Bus Control HI32 ESSI/SCI/Timer Clock CLKOUT PCAP PINIT D[0–23] AA[0–3]/ RAS[0–3] RD WR BS TA BR BG BB BL CAS BCLK BCLK Notes: 1. 2. 3.
PCI Bus Universal Bus Port B GPIO HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAD8 HAD9 HAD10 HAD11 HAD12 HAD13 HAD14 HAD15 HC0/HBE0 HC1/HBE1 HC2/HBE2 HC3/HBE3 HTRDY HIRDY HDEVSEL HLOCK HPAR HPERR HGNT HREQ HSERR HSTOP HIDSEL HFRAME HCLK HAD16 HAD17 HAD18 HAD19 HAD20 HAD21 HAD22 HAD23 HAD24 HAD25 HAD26 HAD27 HAD28 HAD29 HAD30 HAD31 HRST HINTA PVCL HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HA0 HA1 HA2 Tie to pull-up or VCC HDBEN HDBDR HSAK HBS HDAK HDRQ HAEN HTA HIRQ HWR/HRW HRD/HDS Ti
Power 2.1 Power Table 2-2. Power Inputs Power Name Description VCCP PLL Power—VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. VCCQL Quiet Core (Low) Power—An isolated power for the core processing logic. This input must be isolated externally from all other chip power inputs. The user must provide adequate external decoupling capacitors.
Clock 2.3 Clock Table 2-4. Clock Signals Signal Name Type State During Reset Signal Description EXTAL Input Input External Clock/Crystal Input—Interfaces the internal crystal oscillator input to an external crystal or an external clock. XTAL Output Chip-driven Crystal Output—Connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. 2.4 PLL Table 2-5.
External Memory Expansion Port (Port A) 2.5 External Memory Expansion Port (Port A) When the DSP56301 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant Port A signals: A[0–23], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK. 2.5.1 External Address Bus Table 2-6.
External Memory Expansion Port (Port A) Table 2-8. External Bus Control Signals (Continued) Signal Name Type State During Reset Signal Description RD Output Tri-stated Read—When the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0–D23). Otherwise, RD is tri-stated. WR Output Tri-stated Write—When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0–D23).
External Memory Expansion Port (Port A) Table 2-8. External Bus Control Signals (Continued) Signal Name BG Type Input State During Reset Ignored Input Signal Description Bus Grant—Asserted/deasserted synchronous to CLKOUT for proper operation, BG is asserted by an external bus arbitration circuit when the DSP56301 becomes the next bus master. When BG is asserted, the DSP56301 must wait until BB is deasserted before taking bus mastership.
Interrupt and Mode Control 2.6 Interrupt and Mode Control The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 2-9. Interrupt and Mode Control Signal Name Type State During Reset Signal Description RESET Input, Input Schmitttrigger Reset—Must be asserted at power up. Deassertion of RESET is internally synchronized to CLKOUT.
Host Interface (HI32) 2.7 Host Interface (HI32) The Host Interface (HI32) provides a fast parallel data port up to 32 bits wide that can connect directly to the host bus. The HI32 supports a variety of standard buses and provides glueless connection with the PCI bus standard and with a number of industry-standard microcomputers, microprocessors, DSPs and DMA hardware.
Host Interface (HI32) Table 2-10. Host Interface (Continued) Signal Name HC0–HC3/ HBE[3–0] HA[2–0] Type State During Reset Input/Output Tri-stated Input Signal Description Command 0–3/Byte Enable 0–3—When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines7–0 of the bidirectional, multiplexed Address/Data bus.
Host Interface (HI32) Table 2-10. Host Interface (Continued) Signal Name HLOCK Type Input/ Output State During Reset Tri-stated Signal Description Host Lock—When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Lock signal. HBS Input Host Bus Strobe—When HI32 is programmed to interface with a universal non-PCI bus and the HI function is selected, this signal is Host Bus Strobe Schmitt-trigger input.
Host Interface (HI32) Table 2-10. Host Interface (Continued) Signal Name Type HSERR Output, open drain HIRQ Output, open drain State During Reset Tri-stated Signal Description Host System Error—When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host System Error signal. Host Interrupt Request—When HI32 is programmed to interface with a universal non-PCI bus and the HI function is selected, this signal is Host Interrupt Request output.
Host Interface (HI32) Table 2-10. Host Interface (Continued) Type State During Reset HAD[31–16] Input/Output Tri-stated HD[23–8] Input/Output Signal Name Signal Description Host Address/Data 16–31—When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines 16–31 of the bidirectional, multiplexed Address/Data bus.
Host Interface (HI32) Table 2-11.
Host Interface (HI32) Table 2-11.
Host Interface (HI32) Table 2-12. Host Port Pins (HI32) (Continued) Signal Name HP[18–16] HP19 HC3/HBE3 HP20 HP21 Universal Bus Mode PCI Enhanced Universal Bus Mode HC3/HBE3–HC0/HBE0 Bus Command/Byte Enable Tri-state bidirectional bus. During the address phase of a transaction, HC3/HBE3–HC0/HBE0 define the bus command. During the data phase HC3/HBE3–HC0/HBE0 are used as byte enables. The byte enables determine which byte lanes carry meaningful data. GPIO HA[2–0] Host Address Bus Input pin.
Host Interface (HI32) Table 2-12. Host Port Pins (HI32) (Continued) Signal Name HP22 Universal Bus Mode PCI Enhanced Universal Bus Mode GPIO HDEVSEL Host Device Select Sustained tri-state bidirectional pin.2 When actively driven, indicates the driving device has decoded its address as a target of the current access. As an input it indicates whether any device on the bus is selected. HSAK Host Select Acknowledge Active low output pin.
Host Interface (HI32) Table 2-12. Host Port Pins (HI32) (Continued) Signal Name Universal Bus Mode PCI Enhanced Universal Bus Mode GPIO HP27 HREQ Bus Request Tri-state, Output pin. Indicates to the arbiter that the HI32 requires use of the bus. HREQ is deasserted in the same PCI clock that the HI32 asserts HFRAME. As during the STOP reset HREQ is high impedance; an external pull-up should be connected if it is connected to the PCI bus arbiter. HTA Host Transfer Acknowledge Tri-state, Output pin.
Host Interface (HI32) Table 2-12. Host Port Pins (HI32) (Continued) Signal Name HP29 Universal Bus Mode PCI Enhanced Universal Bus Mode HSTOP Host Stop Sustained tri-state bidirectional pin.2 Indicates that the current target is requesting the master to stop the current transaction. HWR/HRW Host Write/Read-Write Schmitt trigger input pin. When in the double-strobe mode of the HI32 (HDSM=0), this pin functions as host write input strobe (HWR). The host processor initiates a write access by asserting HWR.
Host Interface (HI32) Table 2-12. Host Port Pins (HI32) (Continued) Signal Name Universal Bus Mode PCI Enhanced Universal Bus Mode GPIO HP32 HCLK Host Bus Clock Input pin. Provides timing for all transactions on PCI. All other PCI signals are sampled on the HCLK rising edge. Reserved. Must be forced or pulled up to VCC. disconnected HP[40–33] HAD[31–16] Address/Data Multiplexed Bus Tri-state bidirectional bus.
Enhanced Synchronous Serial Interface 0 Table 2-12. Host Port Pins (HI32) (Continued) Signal Name Universal Bus Mode PCI Enhanced Universal Bus Mode GPIO HP49 HRST Hardware Reset Input pin. Forces the HI32 PCI sequencer to the initial state. All pins are forced to the disconnected state. HRST is asynchronous to HCLK. HP50 HINTA Host Interrupt A Active low, open drain output pin(3). Used by the HI32 to request service from the host processor.
Enhanced Synchronous Serial Interface 0 Table 2-13. Enhanced Synchronous Serial Interface 0 Signal Name SC00 Type Input or Output State During Reset Input Signal Description Serial Control 0—For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port C 0—The default configuration following reset is GPIO input PC0.
Enhanced Synchronous Serial Interface 0 Table 2-13. Enhanced Synchronous Serial Interface 0 (Continued) Signal Name SCK0 Type Input/ Output State During Reset Input Signal Description Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK0 is a clock input or output, used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes.
Enhanced Synchronous Serial Interface 1 2.9 Enhanced Synchronous Serial Interface 1 Table 2-14. Enhanced Serial Synchronous Interface 1 Signal Name SC10 Type Input or Output State During Reset Input Signal Description Serial Control 0—For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port D 0—The default configuration following reset is GPIO input PD0.
Enhanced Synchronous Serial Interface 1 Table 2-14. Enhanced Serial Synchronous Interface 1 (Continued) Signal Name SCK1 Type Input/ Output State During Reset Input Signal Description Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a clock input or output used by both the transmitter and receiver in synchronous modes, or by the transmitter in asynchronous modes.
Serial Communications Interface (SCI) 2.10 Serial Communications Interface (SCI) The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. All SCI pins are 5 V tolerant. Table 2-15. Serial Communication Interface Signal Name Type RXD Input PE0 Input or Output State During Reset Input Signal Description Serial Receive Data—Receives byte-oriented serial data and transfers it to the SCI receive shift register.
Timers Table 2-16. Triple Timer Signals Signal Name TIO0 Type Input or Output State During Reset Input Signal Description Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer I/O through the timer 0 control/status register (TCSR0).
JTAG and OnCE Interface 2.12 JTAG and OnCE Interface The DSP56300 family and in particular the DSP56301 support circuit-board test strategies based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module interfaces nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or on-chip peripherals.
JTAG and OnCE Interface 2-30 DSP56301 User’s Manual
Chapter 3 Memory Configuration Like all members of the DSP56300 core family, the DSP56301 addresses three sets of 16 M × 24-bit memory: program, X data, and Y data. Each of these memory spaces includes both on-chip and external memory (accessed through the external memory interface). The DSP56301 is extremely flexible because it has several modes to allocate on-chip memory between the program memory and the two data memory spaces.
Program Memory Space 3.1.1 Internal Program Memory The default on-chip program memory consists of a 24-bit-wide, high-speed, SRAM occupying the lowest 4 K (default), 3 K, 2 K, or 1 K locations in program memory space, depending on the settings of the OMR[MS] and SR[CE] bits. Section 4.3.2, Operating Mode Register (OMR), on page 4-12 provides details on the MS bit. Section 4.3.1, Status Register (SR), on page 4-6 provides details on the CE bit.
X Data Memory Space 3.1.4 Program Bootstrap ROM In the current version of the DSP56301, the program memory space occupying locations $FF0000–$FF0C00 contains the 3 K-word DSP56301 bootstrap program space. Note: In older versions of the DSP56301, the program memory space occupying locations $FF0000–$FF00BF contains the 192-word DSP56301 bootstrap program. 3.
Y Data Memory Space 3.2.3 Internal I/O Space—X Data Memory One part of the on-chip peripheral registers and some of the DSP56301 core registers occupy the top 128 locations of the X data memory ($FFFF80–$FFFFFF). This area is referred to as the internal X I/O space and it can be accessed by MOVE, MOVEP instructions and by bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR and JSSET). The contents of the internal X I/O memory space are listed in Section B.
Dynamic Memory Configuration Switching 3.3.3 External I/O Space—Y Data Memory The off-chip peripheral registers should be mapped into the top 128 locations of Y data memory ($FFFF80–$FFFFFF in the 24-bit Address mode or $FF80–$FFFF in the 16-bit Address mode) to take advantage of the Move Peripheral Data (MOVEP) instruction and the bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). 3.
Sixteen-Bit Compatibility Mode Configuration 3.5 Sixteen-Bit Compatibility Mode Configuration The sixteen-bit compatibility (SC) mode allows the DSP56301 to use DSP56000 object code without change. The SC bit (Bit 13 in the SR) is used to switch from the default 24-bit mode to this special 16-bit mode. SC is cleared by reset. You must set this bit to select the SC mode.
Memory Maps 3.7 Memory Maps The figures in this section show the memory space and RAM configurations defined by the settings of the SR[CE], SR[SC], and OMR[MS] bits. The figures show the configuration, and the accompanying tables describe the bit settings, memory sizes, and memory locations. Note that when the Sixteen-Bit Compatibility mode bit SR[SC] is set, the DSP56301 memory map is changed to enable 16-bit wide address access to the memory mapped X-I/O.
Memory Maps Program X Data $FFFF $FFFF $FF80 External Y Data Internal I/O (128 words) $FFFF $FF80 External I/O (128 words) External External $1000 $0800 $0800 Internal Program RAM (4K) Internal X Data RAM (2K) $0000 $0000 Bit Settings Internal Y Data RAM (2K) $0000 Memory Configuration CE MS SC 0 0 1 Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 4K $000–$FFF 2K $000–$7FF 2K $000–$7FF None 64K Figure 3-2.
Memory Maps Program X Data $FFFFFF $FFFFFF $FFFF80 Internal— Reserved Y Data Internal I/O (128 words) External I/O (128 words) $FFFF80 External External $FFF000 $FF00C0 1 Bootstrap ROM $FF0000 $FFFFFF $FF0000 $FFF000 Internal— Reserved Internal— Reserved $FF0000 External External External $000C00 $000C00 $000800 Internal Program RAM (2K) $000000 $000000 $000000 Bit Settings Memory Configuration CE MS SC 0 1 0 Note: 1.
Memory Maps Program X Data $FFFF $FFFF $FF80 External Y Data Internal I/O (128 words) $FFFF $FF80 External I/O (128 words) External External $0C00 $0C00 $0800 Internal Program RAM (2K) $0000 Internal X Data RAM (3K) $0000 Bit Settings Internal Y Data RAM (3K) $0000 Memory Configuration CE MS SC 0 1 1 Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 2K $000–$7FF 3K $000–$BFF 3K $000–$BFF None 64K Figure 3-4.
Memory Maps Program $FFFFFF X Data $FFFFFF Internal— Reserved $FFFF80 Internal I/O (128 words) $FF00C0 $FF0000 Bootstrap $FFFFFF $FFFF80 External I/O (128 words) External $FFF000 ROM1 Y Data $FF0000 External $FFF000 Internal— Reserved Internal— Reserved $FF0000 External External External $000C00 $000800 $000800 Internal Program RAM (3K) $000000 Internal Y Data RAM (2K) Internal X Data RAM (2K) $000000 $000000 NOTE: External program memory begins immediately after the internal progr
Memory Maps Program $FFFF X Data $FFFF $FF80 Internal I/O (128 words) External Y Data $FFFF $FF80 External I/O (128 words) External External $0C00 $0800 $0800 Internal Program RAM (2K) $0000 Internal X Data RAM (2K) $0000 Internal Y Data RAM (2K) $0000 NOTE: External program memory begins immediately after the internal program memory.
Memory Maps Program $FFFFFF Internal— Reserved X Data $FFFFFF $FFFF80 Internal I/O (128 words) Y Data $FFFFFF $FFFF80 External I/O (128 words) External $FFF000 $FF00C0 Bootstrap ROM1 $FF0000 $FF0000 External $FFF000 Internal— Reserved External Internal— Reserved $FF0000 External External $000C00 $000C00 $000400 Internal Program RAM (1K) $000000 Internal Y Data RAM (3K) Internal X Data RAM (3K) $000000 $000000 NOTE: External program memory begins immediately after the internal prog
Memory Maps Program X Data $FFFF $FFFF $FF80 Y Data Internal I/O (128 words) $FFFF $FF80 External External I/O (128 words) External External $0C00 $0C00 Internal X Data RAM (3K) $0400 $0000 Internal Program RAM (1K) $0000 Internal Y Data RAM (3K) $0000 NOTE: External program memory begins immediately after the internal program memory.
Chapter 4 Core Configuration This chapter presents DSP56300 core configuration details specific to the DSP56301.
Operating Modes 4.1 Operating Modes The operating modes govern not only how the DSP56301 operates but also the start-up procedure location when the DSP56301 leaves the reset state. The MODA–MODD pins are sampled as the DSP56301 exits the reset state. Table 4-1 depicts the mode assignments and Table 4-2 defines the modes. Table 4-1.
Operating Modes Table 4-2. Operating Mode Definitions Mode Description 0 Expanded mode—Bypasses the bootstrap ROM. The DSP56301 begins fetching instructions, starting at $C00000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected (default). 1 Bootstrap from byte-wide memory—Loads a program memory segment from consecutive byte-wide P memory locations, starting at P:$D00000 (bits 7-0).
Operating Modes Table 4-2. Operating Mode Definitions (Continued) Mode Description 6 Host bootstrap 8-bit wide UB mode in double-strobe pin configuration—The hardware reset vector is located at address $FF0000 in the bootstrap ROM. The program bootstraps through HI32 in UB slave double-strobe (HWR, HRD) configuration. The DSP56301 is written with 24-bit wide words broken into 8-bit wide host bus transfers.
Bootstrap Program Table 4-2. Operating Mode Definitions (Continued) Mode Description D Host bootstrap 16-bit wide ISA slave glueless interface in UB mode—Loads the program memory from the Host Interface programmed to operate in the Universal Bus mode supporting ISA (slave) glueless connection. Using Self-Configuration mode, the base address in the CBMA is initially written with $2F, which corresponds to an ISA HTXR address of $2FE (Serial Port 2 Modem Status read-only register).
Central Processor Unit (CPU) Registers You can invoke the bootstrap program options (except modes 0 and 8) at any time by setting the MA, MB, MC, and MD bits in the OMR and jumping to the bootstrap program entry point, $FF0000. Software can set the mode selection bits directly in the OMR. Bootstrap modes 1–7 and 9–F select different specific bootstrap loading source devices.
Central Processor Unit (CPU) Registers n Condition Code Register (CCR) (SR[7–0])—Defines the results of previous arithmetic computations. The CCR bits are affected by Data Arithmetic Logic Unit (Data ALU) operations, parallel move operations, instructions that directly reference the CCR (for example, ORI and ANDI), and instructions that specify SR as a destination (for example, MOVEC). Parallel move operations affect only the S and L bits of the CCR. During processor reset, all CCR bits are cleared.
Central Processor Unit (CPU) Registers Table 4-3. Status Register Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 20 SM 0 Arithmetic Saturation Mode Selects automatic saturation on 48 bits for the results going to the accumulator. This saturation is performed by a special circuit inside the MAC unit. The purpose of this bit is to provide an Arithmetic Saturation mode for algorithms that do not recognize or cannot take advantage of the extension accumulator.
Central Processor Unit (CPU) Registers Table 4-3. Status Register Bit Definitions (Continued) Bit Number Bit Name Reset Value 14 DM 0 Description Double-Precision Multiply Mode Enables four multiply/MAC operations to implement a double-precision algorithm that multiplies two 48-bit operands with a 96-bit result. Clearing the DM bit disables the mode. Note: The Double-Precision Multiply mode is supported to maintain object code compatibility with devices in the DSP56000 family.
Central Processor Unit (CPU) Registers Table 4-3. Status Register Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 11–10 S[1–0] 0 Scaling Mode Specify the scaling to be performed in the Data ALU shifter/limiter and the rounding position in the Data ALU MAC unit. The Shifter/limiter Scaling mode affects data read from the A or B accumulator registers out to the X-data bus (XDB) and Y-data bus (YDB).
Central Processor Unit (CPU) Registers Table 4-3. Status Register Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 6 L 0 Limit Set if the overflow bit is set or if the data shifter/limiter circuits perform a limiting operation. In Arithmetic Saturation mode, the L bit is also set when an arithmetic saturation occurs in the Data ALU result; otherwise, it is not affected.
Central Processor Unit (CPU) Registers 4.3.2 Operating Mode Register (OMR) The OMR is a read/write register divided into three byte-sized units. The lowest two bytes (EOM and COM) control the chip’s operating mode. The high byte (SCS) controls and monitors the stack extension. The OMR control bits are shown in Figure 4-2.
Central Processor Unit (CPU) Registers Table 4-4. Operating Mode Register (OMR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 18 EOV 0 Stack Extension Overflow Flag Set when a stack overflow occurs in Stack Extended mode. Extended stack overflow is recognized when a push operation is requested while SP = SZ (Stack Size register), and the Extended mode is enabled by the SEN bit.
Central Processor Unit (CPU) Registers Table 4-4. Operating Mode Register (OMR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 12 BRT 0 Bus Release Timing Selects between fast or slow bus release. If BRT is cleared, a Fast Bus Release mode is selected (that is, no additional cycles are added to the access and BB is not guaranteed to be the last Port A pin that is tri-stated at the end of the access).
Configuring Interrupts Table 4-4. Operating Mode Register (OMR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 6 SD 0 Stop Delay Mode Determines the length of the delay invoked when the core exits the Stop state. The STOP instruction suspends core processing indefinitely until a defined event occurs to restart it. If SD is cleared, a 128K clock cycle delay is invoked before a STOP instruction cycle continues.
Configuring Interrupts 4.4.1 Interrupt Priority Registers (IPRC and IPRP) There are two interrupt priority registers in the DSP56301. The IPRC (Figure 4-3) is dedicated to DSP56300 core interrupt sources, and IPRP (Figure 4-4) is dedicated to DSP56301 peripheral interrupt sources.
Configuring Interrupts The DSP56301 has a four-level interrupt priority structure. Each interrupt has two interrupt priority level bits (IPL[1–0]) that determine its interrupt priority level. Level 0 is the lowest priority; Level 3 is the highest-level priority and is non-maskable. Table 4-5 defines the IPL bits. Table 4-5.
Configuring Interrupts Table 4-6.
Configuring Interrupts Table 4-6.
Configuring Interrupts Table 4-7.
PLL Control Register (PCTL) 4.5 PLL Control Register (PCTL) The bootstrap program must initialize the system Phase-Lock Loop (PLL) circuit by configuring the PLL Control Register (PCTL). The PCTL is an X-I/O mapped, read/write register that directs the on-chip PLL operation. (See Figure 4-5.
Bus Interface Unit (BIU) Registers 4.6 Bus Interface Unit (BIU) Registers The three Bus Interface Unit (BIU) registers configure the external memory expansion port (Port A). They include the following: n Bus Control Register (BCR) n DRAM Control Register (DCR) n Address Attribute Registers (AAR[3–0]) To use Port A correctly, configure these registers as part of the bootstrap process. The following subsections describe these registers. 4.6.
Bus Interface Unit (BIU) Registers Table 4-9. Bus Control Register (BCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 20–16 BDFW[4–0] 11111 (31 wait states) Bus Default Area Wait State Control Defines the number of wait states (one through 31) inserted into each external access to an area that is not defined by any of the AAR registers. The access type for this area is SRAM only.
Bus Interface Unit (BIU) Registers Table 4-9. Bus Control Register (BCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 4–0 BA0W[4–0] 11111 (31 wait states) Bus Area 0 Wait State Control Defines the number of wait states (one through 31) inserted in each external SRAM access to Area 0 (DRAM accesses are not affected by these bits). Area 0 is the area defined by AAR0.
Bus Interface Unit (BIU) Registers Table 4-10. DRAM Control Register (DCR) Bit Definitions Bit Number Bit Name Reset Value 23 BRP 0 Description Bus Refresh Prescaler Controls a prescaler in series with the refresh clock divider. If BPR is set, a divide-by-64 prescaler is connected in series with the refresh clock divider. If BPR is cleared, the prescaler is bypassed.
Bus Interface Unit (BIU) Registers Table 4-10. DRAM Control Register (DCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 11 BPLE 0 Bus Page Logic Enable Enables/disables the in-page identifying logic. When BPLE is set, it enables the page logic (the page size is defined by BPS[1–0] bits). Each in-page identification causes the DRAM controller to drive only the column address (and the associated CAS signal).
Bus Interface Unit (BIU) Registers 4.6.3 Address Attribute Registers (AAR[0–3]) The Address Attribute Registers (AAR[0–3]) are read/write registers that control the activity of the AA0/RAS0–AA3/RAS3 pins. The associated AAn/RASn pin is asserted if the address defined by the BAC bits in the associated AAR matches the exact number of external address bits defined by the BNC bits, and the external address space (X data, Y data, or program) is enabled by the AAR.
Bus Interface Unit (BIU) Registers Table 4-11. Address Attribute Registers (AAR[0–3]) Bit Definitions (Continued) Bit Number Bit Name Reset Value 7 BPAC 0 Description Bus Packing Enable Enables/disables the internal packing/unpacking logic. When BPAC is set, packing is enabled. In this mode each DMA external access initiates three external accesses to an 8-bit wide external memory (the addresses for these accesses are DAB, then DAB + 1 and then DAB + 2).
DMA Control Registers 5–0 (DCR[5–0]) Table 4-11. Address Attribute Registers (AAR[0–3]) Bit Definitions (Continued) Bit Number Bit Name Reset Value 1–0 BAT[1–0] 0 Description Bus Access Type Read/write bits that define the type of external memory (DRAM or SRAM) to access for the area defined by the BAC[11–0],BYEN, BXEN, and BPEN bits.
DMA Control Registers 5–0 (DCR[5–0]) Table 4-12. DMA Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value Description 22 DIE 0 DMA Interrupt Enable Generates a DMA interrupt at the end of a DMA block transfer after the counter is loaded with its preloaded value. A DMA interrupt is also generated when software explicitly clears DE during a DMA operation. Once asserted, a DMA interrupt request can be cleared only by the service of a DMA interrupt routine.
DMA Control Registers 5–0 (DCR[5–0]) Table 4-12. DMA Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value 18–17 DPR[1–0] 0 Description DMA Channel Priority Define the DMA channel priority relative to the other DMA channels and to the core priority if an external bus access is required. For pending DMA transfers, the DMA controller compares channel priority levels to determine which channel can activate the next word transfer.
DMA Control Registers 5–0 (DCR[5–0]) Table 4-12. DMA Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value 18–17 cont.
DMA Control Registers 5–0 (DCR[5–0]) Table 4-12. DMA Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value 15–11 DRS[4–0] 0 Description DMA Request Source Encodes the source of DMA requests that trigger the DMA transfers. The DMA request sources may be external devices requesting service through the IRQA, IRQB, IRQC and IRQD pins, triggering by transfers done from a DMA channel, or transfers from the internal peripherals.
Device Identification Register (IDR) Table 4-12. DMA Control Register (DCR) Bit Definitions (Continued) Bit Reset Bit Name Number Value Description 9–4 DAM[5–0] 0 DMA Address Mode Defines the address generation mode for the DMA transfer. These bits are encoded in two different ways according to the D3D bit. 3–2 DDS[1–0] 0 DMA Destination Space Specify the memory space referenced as a destination by the DMA.
JTAG Identification (ID) Register 4.9 JTAG Identification (ID) Register The JTAG ID register is a 32-bit read-only factory-programmed register that distinguishes the component on a board according to the IEEE 1149.1 standard. Figure 4-11 shows the JTAG ID register configuration. Version information corresponds to the revision number ($0 for revision 0, $1 for revision A, and so forth).
JTAG Boundary Scan Register (BSR) 4-36 DSP56301 User’s Manual
Chapter 5 Programming the Peripherals When the DSP56301 peripherals (HI32, ESSI, SCI, and Timers) are programmed in a given application, a number of possible modes and options are available for use. Chapters 6–9 describe in detail the possible modes and configurations for peripheral registers and ports. This chapter presents general guidelines for initializing the peripherals.
Mapping the Control Registers 5.2 Mapping the Control Registers The I/O peripherals are controlled through registers mapped to the top 128 words of X-data memory ($FFFF80–$FFFFFF). Referred to as the internal I/O space, the control registers are accessed by move (MOVE, MOVEP) instructions and bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, AND JSSET). The contents of the internal X I/O memory space are listed in Appendix B, Programming Reference, Table B-2.
Data Transfer Methods DSP56300 core does not execute any other code. Polling is the easiest transfer method since it does not require register initializations, but it is also the least efficient use of the DSP core. Each peripheral has its own set of flags that can be polled to determine when data is ready to be transferred. For example, the ESSI control registers provide bits that tell the core when data is ready to be transferred to or from the peripheral.
General-Purpose Input/Output (GPIO) 5.3.3 DMA The Direct Memory Access (DMA) controller permits data transfers between internal/ external memory and/or internal/external I/O in any combination without the intervention of the core. Dedicated DMA address and data buses and internal memory partitioning ensure achievement of high-level isolation so the DMA operation does not interfere with or slow down core operation. The DMA moves data to/from the peripheral transmit/receive registers.
General-Purpose Input/Output (GPIO) 5.4.1 Port B Signals and Registers As shown in Figure 5-2, you can configure twenty-four Port B signals as GPIO signals. DSP56301 Host Interface (HI32)/ Port B Signals Note: HPxx is a reference only and is not a signal name. GPIO references formerly designated as HIOxx have been renamed PBxx for consistency with other Motorola DSPs.
General-Purpose Input/Output (GPIO) 5.4.2 Port C Signals and Registers Each of the six Port C signals not used as an ESSI0 signal can be configured as a GPIO signal. Three registers control the GPIO functionality of Port C: Port C control register (PCRC), Port C direction register (PRRC), and Port C data register (PDRC). Chapter 7, Enhanced Synchronous Serial Interface (ESSI) discusses these registers.
General-Purpose Input/Output (GPIO) 5.4.5 Triple Timer Signals and Registers Each of the three triple timer interface signals (TIO0–TIO2) not used as a timer signal can be configured as a GPIO signal. Each signal is controlled by the appropriate timer control status register (TCSR[0–2]). Chapter 9, Triple Timer Module discusses these registers. Timer GPIO DSP56301 TIO0 Timers TIO1 TIO0 TIO1 TIO2 TIO2 Figure 5-6.
General-Purpose Input/Output (GPIO) 5-8 DSP56301 User’s Manual
Chapter 6 Host Interface (HI32) The Host Interface (HI32) is a fast parallel host port up to 32 bits wide that can directly connect to the host bus. The HI32 supports a variety of standard buses and provides glueless connection with a number of industry-standard microcomputers, microprocessors, DSPs, and DMA controllers. The DSP56300 core controls host port pin functionality and polarity.
Features Table 6-1.
Features Table 6-1.
Overview Table 6-2.
Overview DSP-Side Registers DCTR DSP Control Register DPSR DSP PCI Status Register DPCR DSP PCI Control Register DRXR DSP Receive Data Register DSP PCI Master Control Register DTXM DSP Master Transmit Data Register DPAR DSP PCI Address Register DTXS DSP Slave Transmit Data Register DSR DSP Status Register DIRH DSP Host Port GPIO Direction Register DATH DSP Host Port GPIO Data Register DPMC DSP DMA Data Bus DSP Global Data Bus DPCR DPMC 24 24 24 24 24 DPAR DCTR DSR HSTR HCTR
Data Transfer Paths DMA controllers, or standard peripheral buses (for example, ISA/EISA) because the interface appears to the host as static RAM. A host command feature enables the host processor to issue vectored interrupt requests to the DSP56300 core. Writing to a vector address register in the HI32, the host can select any one of 128 DSP56300 core interrupt routines to execute. This flexibility allows the host programmer to execute up to 128 pre-programmed functions inside the DSP.
Data Transfer Paths In PCI mode data transfers in which the HI32 is the target (DCTR[HM] = $1) with HCTR[HTF]≠$0, the host-to-DSP data path is a six word deep, 24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the DSP56300 core reads 24-bit words from the DRXR. In Universal Bus mode data transfers, the host-to-DSP data path is a five word deep, 24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the DSP56300 core reads 24-bit words from the DRXR.
Data Transfer Paths HRXS. Each time the host reads a 32-bit word from the HRXS, the 32-bits of significant data located in two locations of the slave DSP-to-host data path (DTXS and HRXS) are output. The DSP side of the DSP-to-host data FIFOs is described in the following pages. For a detailed description of the host side, see Section 6.8.4, Host Master Receive Data Register (HRXM), on page 6-61 and Section 6.8.5, Host Slave Receive Data Register (HRXS), on page 6-61. Table 6-3.
Data Transfer Paths Table 6-3. HI32 (PCI Master Data Transfer Formats (Continued) DPMC Register FC1 FC0 1 1 DSP-to-PCI Host Data Transfer Format The three least significant HRXM bytes are output left aligned and zero filled. PCI Host-to-DSP Data Transfer Format The three most significant PCI data bytes are written to the HTXR. GDB/MDDB HI32 GDB/MDDB HI32 DTXM DRXR HRXM HTXR $0 HDTFC HDTFC $0 PCI bus X PCI bus Table 6-4.
Data Transfer Paths Table 6-4. Transmit Data Transfer Format (Continued) HCTR Host-to-DSP Data Transfer Format HTF1 HTF0 1 0 PCI mode The three least significant PCI data bytes are written HD[15–0] are written to the HTXR, right aligned to the HTXR. and sign extended.
Data Transfer Paths Table 6-5. Receive Transfer Data Formats HCTR HRF 1 HRF 0 0 1 DSP to Host Data Transfer Format PCI mode The three least significant HRXS bytes are output right aligned and zero extended. GDB/MDDB HI32 1 0 1 The two least significant HRXS bytes are output to HD[15–0]. X GDB/MDDB DTXS X DTXS HRXS X HRXS HI32 $0 HDTFC HDTFC $0 PCI bus Host bus The three least significant HRXS bytes are output right aligned and sign extended.
Reset States 6.4 Reset States Table 6-6 describes the various HI32 reset states. Table 6-6. HI32 Reset Type Hardware Reset HS Initiated by the Host Initiated by the DSP56300 Core Software Reset Entered when Description The DSP56300 core RESET pin is asserted. These resets force the HI32 DSP side state machines, control registers, and status registers to their initial states. These resets also activate the Personal Software (PS) reset. The RESET instruction is executed.
DSP-Side Operating Modes Table 6-7. HI32 Modes HM[2–0] HI32 Mode 000 Terminate and Reset 001 PCI 010 Universal Bus 011 Enhanced Universal Bus 100 GPIO 101 Self-Configuration 110 Reserved 111 Reserved 6.5.1 Terminate and Reset (DCTR[HM] = $0) When DCTR[HM2–0] is written with a value of $0 and the HI32 is in PCI mode (DCTR[HM] = $1), the HI32 is an active PCI master. The HI32 generates a master-initiated termination.
DSP-Side Operating Modes Example 6-1. PCI /DMA Throughput (32-Bit) PCI clock = 33 MHz 56301 core clock = 66 MHz 33-bit PCI mode 1 wait state SRAM DMA transfers: SRAM -> host transmit FIFO (master or slave) Best throughput rate is 14.14 Mwords/sec. Here’s why... 1: HI32 max transfer rate (32-bit) (pci_cyc + pci_w.s) x multfactor 1 + 1.33 x 2 multfactor = 2 because f_core = = = tot_cyc 4.67 66 MHz and f_pci = 33 MHz. Since 4 2/3 (HI32) > 2 (core), this dominates, so the answer is 66/4.67 = 14.
DSP-Side Operating Modes (pci_cyc + pci_w.s) x multfactor 1 + 0 x 2 multfactor = 2 because f_core = = = tot_cyc 2 66 MHz and f_pci = 33 MHz. Since 4 2/3 (HI32) > 2 (core), this dominates, so the answer is 66/2 = 33 Mwords. 2: (DMA transfer internal memory) DRXR --> (DMA) --> internal X: ( 1 (src) + 1 (dest) + 0 (w.s.
DSP-Side Operating Modes In addition, for Universal Bus mode, pins HP[22–20] are GPI/O. For Enhanced Universal Bus mode, two control signals (data direction and data output enable) are output to an optional external data buffer. Also, there is host select acknowledge output. 6.5.4 GPIO Mode (DCTR[HM] = $4) n General-purpose I/O (GPIO) port, pins HP[23–0]. n Pins HP[48–33], HP[30–24] are disconnected. n HP31 and HP32 are unused and must be forced or pulled up to VCC. n Minimum current consumption.
DSP-Side Operating Modes never changed. Therefore the upper 16 bits of the base address are written to every register location, in this example. Example 6-3.
Host Port Pins 6.6 Host Port Pins The HI32 signals are discussed in Chapter 2. In this section, Table 6-8 summarizes the pin functionality in the different HI32 operating modes. Examples of host-to-HI32 connections are given in Figure 6-2, Figure 6-3, and Figure 6-4. Table 6-8.
Host Port Pins PCI Bus DSP56301 (initiator/target) (target/initiator) HI32 AD[31–0] HAD[31–0] C3/BE3–C0/BE0 HC3/HBE3–HC0/HBE0 PAR HPAR FRAME HFRAME IRDY HIRDY TRDY HTRDY DEVSEL HDEVSEL STOP HSTOP PERR HPERR SERR HSERR REQ HREQ GNT HGNT IDSEL HIDSEL RST HRST CLK HCLK LOCK HLOCK INTA HINTA Figure 6-2.
Host Port Pins Host DSP56301 (master) (slave) ISA HI32 AEN HAEN SBHE HA10 SA[0] HA9 SA[9–4] HA[8–3] SA[3–1] HA[2–0] HDBEN HDBDR D[15–0] BUF CHRDY * HD[15–0] HTA IOWC HWR IORC HRD * IO16 HSAK * IRQ HIRQ DRQ HDRQ DAK HDAK RESDRV Vcc HRST Vcc HBS Vcc HP31 Vcc HP32 HP19 HD[23–16] * Open Collector Note: The HI32 can be externally buffered to drive the current required by the ISA/EISA standard.
Host Port Pins DSP56301 DSP56301 (master) (slave) Port A HI32 (master) (slave) HAEN AA0 A[10–0] HA[10–0] D[23–0] HD[23–0] TA HTA WR HWR RD HRD IRQA HIRQ BS HBS Vcc HDAK Vcc Vcc HP31 HP32 Vcc HP19 Note: If the HI32 DSP and the host DSP use the same EXTAL clock, the HI32 can operate synchronously at its maximum throughput of three clock cycles/word. (For example, for a 6 MHz clock (CLKOUT )the HI32 throughput is 22 Mwords/sec = 66 Mbytes/sec. Figure 6-4.
HI32 DSP-Side Programming Model 6.7 HI32 DSP-Side Programming Model The DSP56300 core views the HI32 as a memory-mapped peripheral occupying eleven 24-bit words in data memory space. Table 6-9 shows the HI32 DSP-side programming model. Table 6-9.
HI32 DSP-Side Programming Model 6.7.1 DSP Control Register (DCTR) The DCTR is a 24-bit read/write control register by which the core controls the HI32 interrupts, flags, and host port pin functionality. The host processor cannot access the DCTR. To access individual DCTR bits, use the bit manipulation instructions. .
HI32 DSP-Side Programming Model Table 6-10. DSP Control Register (DCTR) Bit Definitions (Continued) Bit Number Bit Name 19 HIRD Reset Value Mode Description 0 UB Host Interrupt Request Drive Control Controls the output drive of the HIRQ pin when the HI32 is in a Universal Bus mode (DCTR[HM] = $2 or $3). When HIRD is cleared, the HIRQ pin is an open-drain output—that is, driven low when asserted, released (high impedance) when deasserted. When HIRD is set, the HIRQ pin is always driven.
HI32 DSP-Side Programming Model Table 6-10. DSP Control Register (DCTR) Bit Definitions (Continued) Bit Number Bit Name 15 HTAP Reset Value Mode Description 0 UB Host Transfer Acknowledge Polarity Controls the polarity of the HTA pin when the HI32 is in a Universal Bus mode (DCTR[HM] = $2 or $3). If HTAP is cleared, the HTA pin is active high and the HI32 requests to extend the access by driving the HTA pin low (that is, deasserted).
HI32 DSP-Side Programming Model Table 6-10. DSP Control Register (DCTR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Mode Description 5–3 HF[5–3] 0 UB/PCI Host Flags General-purpose flags for DSP-to-host communication. The DSP56300 core can set or clear these bits. HF[5–3] are visible to the external host in the HSTR. There are six host flags: three by which the host signals the DSP56300 core (HF[2–0]) and three by which the DSP56300 core signals the host processor (HF[5–3]).
HI32 DSP-Side Programming Model Table 6-11. DSP PCI Control Register (DPCR) Bit Definitions Bit Number Bit Name 23–22 21 IAE Reset Value Description 0 Reserved. Write to 0 for future compatibility. 0 Insert Address Enable In PCI mode (DCTR[HM] = $1), inserts the PCI transaction address at the head of the incoming data stream in accordance with the value of the host data transfer format (HTF) bits in the HCTR.
HI32 DSP-Side Programming Model Table 6-11. DSP PCI Control Register (DPCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 19 MWSD 0 Master Wait State Disable Disables PCI wait states (inserted by deasserting HIRDY) during a data phase. When MWSD is cleared, the HI32 as the active PCI master (DCTR[HM] = $1) inserts wait states to extend the current data phase if it cannot guarantee the completion of the next data phase.
HI32 DSP-Side Programming Model Table 6-11. DSP PCI Control Register (DPCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 14 CLRT 0 Clear Transmitter Clears the HI32 master-to-host bus data path in PCI mode (DCTR[HM] = $1). When the DSP56300 core sets CLRT, the HI32 hardware clears the master DSP-to-host bus data path (that is, the DTXM-HRXM FIFO is forced empty), thus setting the PCI Master Transmit Data Request bit (MTRQ) in the DPSR. Then it clears CLRT.
HI32 DSP-Side Programming Model Table 6-11. DSP PCI Control Register (DPCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 4 MAIE 0 Master Address Interrupt Enable Enables/disables a DSP56300 core interrupt request when the HI32 is not the PCI transaction initiator in the PCI mode (DCTR[HM] = $1). If MAIE is cleared, master address interrupt requests are disabled.
HI32 DSP-Side Programming Model Table 6-12. DSP PCI Master Control Register (DMPC) Bit Definitions Bit Number Bit Name Reset Value Description 23–22 FC[1–0] 0 Data Transfer Format Control In PCI mode (DCTR[HM] = $1), define data transfer formats between the HI32 and a PCI agent when the HI32 is a bus master. The data transfer format converter) operates according to the specified FC[1–0].
HI32 DSP-Side Programming Model Table 6-12. DSP PCI Master Control Register (DMPC) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 23–22 Cont. FC[1–0] Cont. 0 DPMC[FC] = $1 or $2 The three least significant PCI data bytes from the HAD[23–0] pins are transferred to the DRXR to be read by the DSP56300 core. DPMC[FC] = $3 6-32 The three most significant PCI data bytes from the HAD[31–8] pins are transferred to the DRXR to be read by the DSP56300 core.
HI32 DSP-Side Programming Model 6.7.4 DSP PCI Address Register (DPAR) 23 22 21 20 19 18 17 16 BE3 BE2 BE1 BE0 C3 C2 C1 C0 15 14 13 12 11 10 9 8 AR15 AR14 AR13 AR12 AR11 AR10 AR9 AR8 7 6 5 4 3 2 1 0 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 Figure 6-8. DSP PCI Address Register (DPAR) A 24-bit read/write register by which the DSP56300 core generates the two least significant bytes of the 32-bit PCI transaction address, the PCI bus command and the PCI bus byte enables.
HI32 DSP-Side Programming Model Table 6-13. DSP PCI Address Register (DPAR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 19–16 C[3–0] 0 PCI Bus Command Defines the PCI bus command. When the DSP56300 core writes to the DPAR and the HI32 is in PCI mode (DCTR[HM] = $1), ownership of the PCI bus is requested. When the request is granted, the address is driven to the HAD[31–0] pins and the bus command is driven to the HC[3–0]/HBE[3–0] pins during the PCI address phase.
HI32 DSP-Side Programming Model 6.7.5 DSP Status Register (DSR) . 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HF2 UBM PCI HF1 UBM PCI HF0 UBM PCI SRRQ UBM PCI STRQ UBM PCI HCP UBM PCI HACT UBM PCI SC Reserved. Write to 0 for future compatibility UBM = Universal Bus mode PCI = PCI mode SC = Self-Configuration mode Figure 6-9. DSP Status Register (DSR) A 24-bit read-only status register by which the DSP56300 core examines the HI32 status and flags.
HI32 DSP-Side Programming Model Table 6-14. DSP Status Register (DSR) Bit Definitions (Continued) Bit Bit Name Number 5–3 HF[2–0] Reset Value 0 Mode Description UBM PCI Host Flags Indicate the state of host flags HF[2–0], respectively, in the Host Control Register (HCTR) on the host side. Only the host processor can change HF[2–0]. In PCI mode (DCTR[HM] = $1), the HF[2–0] bits are updated at the end of a transaction. Personal hardware reset clears HF[2–0].
HI32 DSP-Side Programming Model Table 6-14. DSP Status Register (DSR) Bit Definitions (Continued) Bit Bit Name Number 1 STRQ Reset Value 1 Mode Description UBM PCI Slave Transmit Data Request Indicates that the slave transmit data FIFO (DTXS) is not full and the DSP56300 core can write to it. STRQ functions in accordance with the value of the slave fetch type (SFT) bit in the Host Control Register (HCTR).
HI32 DSP-Side Programming Model 6.7.6 DSP PCI Status Register (DPSR) . 23 22 21 20 19 18 17 16 RDC5 RDC4 RDC3 RDC2 RDC1 RDC0 13 12 11 10 9 8 HDTC TO TRTY TDIS TAB 3 2 1 0 MRRQ MTRQ MWS 15 14 RDCQ MDT 7 6 5 4 MAB DPER APER MARQ Reserved. Write to 0 for future compatibility Figure 6-10. DSP PCI Status Register (DPSR) A 24-bit read-only status register by which the DSP56300 core examines the status and flags of the HI32 in PCI mode (DCTR[HM] = $1).
HI32 DSP-Side Programming Model Table 6-15. DSP PCI Status Register (DPSR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 14 MDT 0 Master Data Transferred Indicates the status of the latest completed PCI transaction to which the HI32 was a PCI master. MDT is set at the end of a transaction (MARQ = 1) if the HI32 successfully transferred the master data, as defined by the DPMC[BL] bits. Otherwise, MDT is cleared.
HI32 DSP-Side Programming Model Table 6-15. DSP PCI Status Register (DPSR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 9 TDIS 0 PCI Target Disconnect Indicates that an HI32-initiated PCI transaction has terminated with a target-initiated disconnect. When TDIS is set and, if DPCR[TTIE] is set, a transaction termination interrupt request is generated. TDIS is cleared when the DSP56300 core writes a value of one to it.
HI32 DSP-Side Programming Model Table 6-15. DSP PCI Status Register (DPSR) Bit Definitions (Continued) Bit Number Bit Name 3 Reset Value Description 0 Reserved. Write to 0 for future compatibility. 2 MRRQ 0 PCI Master Receive Data Request Indicates that the DSP receive data FIFO (DRXR) contains data read from the host bus by the HI32 master. When the HI32, as master, reads data from the host bus to the host-to-DSP FIFO (HTXR-DRXR), MRRQ is set.
HI32 DSP-Side Programming Model when the host-to-DSP data path FIFO is emptied by DSP56300 core reads. The DSP56300 core can set the SRIE bit to cause a host receive data interrupt when SRRQ is set. In 32-bit mode (DCTR[HM] = $1 with DPMC[FC] = $0 or HCTR[HTF] = $0), only the two least significant bytes contain data. The most significant byte is read as zeroes. (See Table 6-3). Hardware, software, and personal software resets empty the host-to-DSP data path FIFO (SRRQ and MRRQ are cleared). 6.7.
HI32 DSP-Side Programming Model 6.7.10 DSP Host Port GPIO Direction Register (DIRH) 23 22 21 20 19 18 17 16 DIR23 DIR22 DIR21 DIR20 DIR19 DIR18 DIR17 DIR16 15 14 13 12 11 10 9 8 DIR15 DIR14 DIR13 DIR12 DIR11 DIR10 DIR9 DIR8 7 6 5 4 3 2 1 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 Figure 6-11. DSP Host Port Direction Register (DIRH) A 24-bit read/write register by which the DSP56300 core controls the direction of the host port pins in GPIO mode.
Host-Side Programming Model 6.8 Host-Side Programming Model The HI32 appears to the host processor as a bank of registers, listed in Table 6-17. Table 6-17.
Host-Side Programming Model hardware can be used with the handshake flags to transfer data without host processor intervention. n When a host bus is less than 24 bits wide, the unused data pins must be forced or pulled up or down to VCC or to GND, respectively. For example, for a 16-bit bus (such as an ISA bus), HP[48–41] must be forced or pulled up to VCC or pulled down to GND. In PCI mode: n In memory space read/write transactions, the HI32 occupies 16384 Dwords.
Host-Side Programming Model Table 6-18. PCI Bus Commands HC3/HBE3-HC0/HBE0 Note: n 6-46 Executed as Command Type 0000 ignored1 0001 ignored1 0010 ignored1 0011 ignored1 0100 ignored1 0101 ignored1 0110 Memory Read 0111 Memory Write 1000 ignored1 1001 ignored1 1010 Configuration Read 1011 Configuration Write 1100 Memory Read 1101 ignored1 1110 Memory Read 1111 Memory Write All internal address decoding is ignored and DEVSEL is not asserted.
Host-Side Programming Model Table 6-19. Host-Side Registers (PCI Memory Address Space1) Base Address: $0000 Reserved (4 Dwords) Base Address:$000C Base Address: $0010 HI32 Control Register (HCTR) Base Address: $0014 HI32 Status Register (HSTR) Base Address: $0018 Host Command Vector Register (HCVR) Base Address:$001C Host Transmit/Slave Receive Data Register (HTXR/HRXS) (16377 Dwords) Base Address:$FFFC Note: Addresses are shown in bytes. Table 6-20.
Host-Side Programming Model 6.8.1 HI32 Control Register (HCTR) 31 30 29 13 28 12 27 11 26 9 24 8 23 21 6 5 20 18 17 HS2 PCI UBM PCI HS0 HRF1 HRF0 HTF1 HTF0 SFT DMAE HF2 HF1 HF0 RREQ TREQ UBM PCI UBM PCI UBM PCI UBM PCI UBM PCI UBM PCI UBM PCI UBM PCI Reserved. Read as zero. Write to zero for future compatibility. 16 TWSD HS1 UBM 4 19 14 UBM PCI 7 22 15 UBM PCI 10 25 3 2 UBM PCI 1 0 UBM PCI UB = Universal Bus mode PCI = PCI mode Figure 6-13.
Host-Side Programming Model Table 6-22. Host Interface Control Register (HCTR) Bit Definitions Bit Number Bit Name 31–20 19 Reset Value Mode 0 TWSD 0 Description Reserved. Write to zero for future compatibility. PCI Target Wait State Disable Note: Do not set the TWSD bit. This bit is reserved. The HI32 may operate improperly in PCI mode when the Target Wait State Disable (TWSD) bit is set. Disables PCI wait states (which are inserted by deasserting HTRDY) during a data phase.
Host-Side Programming Model Table 6-22. Host Interface Control Register (HCTR) Bit Definitions (Continued) Bit Number Bit Name 13 12–11 Reset Value Mode 0 HRF[1–0] 0 Description Reserved. Write to zero for future compatibility. UBM PCI Host Receive Data Transfer Format Define data transfer formats for DSP-to-host communication. The data transfer format converter (HDTFC) operates according to the specified HRF[1–0] (See Table 6-5, Receive Transfer Data Formats, on page 6-10).
Host-Side Programming Model Table 6-22. Host Interface Control Register (HCTR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Mode Description 9–8 HTF[1–0] 0 UBM PCI Host Transmit Data Transfer Format Define data transfer formats for host-to-DSP communication. The data transfer format converter (HDTFC) operates according to the specified HTF[1–0] (see Table Table 6-4, Transmit Data Transfer Format, on page 6-9). The personal hardware reset clears HTF[1–0].
Host-Side Programming Model Table 6-22. Host Interface Control Register (HCTR) Bit Definitions (Continued) Bit Number 9–8 cont. Bit Name Reset Value Mode HTF[1–0] 0 UBM PCI Description Host Transmit Data Transfer Format (cont.) Note: When the HI32 is in PCI mode, the HTF control bits affect the address insertion (the IAE bit is set in the DPCR) in the same way they affect the transferred data.
Host-Side Programming Model Table 6-22. Host Interface Control Register (HCTR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Mode 7 Cont. SFT Cont. 0 UBM PCI Description Universal Bus mode (DCTR[HM] = $2 or $3) Fetch (SFT = 1): There is no FIFO buffering of the DSP-to-host data path. Writing SFT = 1 resets the DSP-to-host data path and clears the STRQ and the HSTR[HRRQ]. At the beginning of a read data transfer from the HRXS, STRQ is set.
Host-Side Programming Model Table 6-22. Host Interface Control Register (HCTR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Mode Description 6 DMAE 0 UBM DMA Enable (ISA/EISA) Used by the host processor to enable the HI32 ISA/EISA DMA-type accesses in a Universal Bus mode (DCTR[HM] = $2 or $3). If the host drives the HAEN pin low, the HI32 responds when it identifies its address (such as ISA/EISA I/O-type accesses). The HI32 does not respond to ISA/EISA DMA-type accesses.
Host-Side Programming Model Table 6-22. Host Interface Control Register (HCTR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Mode 2 RREQ 0 UBM Description Receive Request Enable Controls the HIRQ and HDRQ pins for DSP-to-host data transfers in a Universal Bus mode (DCTR[HM] = $2 or $3). When DMAE is cleared, RREQ enables the host interrupt request (HIRQ) pin if the host receive data request (HRRQ) status bit in the HSTR is set.
Host-Side Programming Model Table 6-22. Host Interface Control Register (HCTR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Mode Description 1 TREQ 0 UBM Transmit Request Enable Controls the HIRQ and HDRQ pins for host transmit data transfers in a Universal Bus mode (DCTR[HM] = $2 or $3). When the DMA enable bit (DMAE) is cleared, TREQ (when set) enables the Host Interrupt Request HIRQ pin if the host transmit data request (HTRQ) status bit in the HI32 Status Register (HSTR) is set.
Host-Side Programming Model n In a 16-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HCTR[HRF]≠$0), the HD[15–0] pins are driven with the two least significant bytes of the HSTR in a read access. n In PCI mode (DCTR[HM] = $1) memory space transactions, the HSTR is accessed if the PCI address is HI32_base_address: $014. n In a Universal Bus mode (DCTR[HM] = $2 or $3), the HSTR is accessed if the HA[10–3] value matches the HI32 base address (see Section 6.8.
Host-Side Programming Model Table 6-23. Host Interface Status Register (HSTR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 2 HRRQ 0 Mode Description UBM PCI Host Receive Data Request Indicates that the host slave receive data FIFO (HRXS) contains data from the DSP56300 core and can be read by the host processor. In PCI mode, as a target in a read data phase from the HRXS, the HI32 deasserts HTRDY and inserts up to eight PCI wait cycles, if HRRQ is cleared.
Host-Side Programming Model 6.8.3 Host Command Vector Register (HCVR) ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HV6 HV5 HV4 HV3 HV2 HV1 HV0 HC UBM PCI UBM PCI UBM PCI UBM PCI UBM PCI UBM PCI UBM PCI UBM PCI HNMI Reserved. Read as zero. Write to zero for future compatibility. PCI = PCI mode UBM = Universal Bus mode Figure 6-15.
Host-Side Programming Model If TWSD is cleared, the HI32 is the selected PCI target (DCTR[HM] = $1) in a write data phase to the HCVR. It inserts PCI wait states if a host command is pending (HC = 1). Wait states are inserted until the pending host command is serviced. Up to eight wait states can be inserted before a target-initiated transaction termination (disconnect-C/Retry) is generated. In a Universal Bus mode write to the HCVR, the HI32 inserts wait states if a host command is pending (HC = 1).
Host-Side Programming Model Table 6-24. Host Command Vector Register (HCVR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Mode Description 0 HC 0 UBM PCI Host Command Used by the host processor to handshake the execution of host command interrupt requests. Normally, the host processor sets HC to request a host command interrupt from the DSP56300 core. When the DSP56300 core acknowledges the host command interrupt request, HI32 hardware clears the HC bit.
Host-Side Programming Model the pins and their alignment. (See Section 6.3.2, DSP-To-Host Data Path, on page 6-7 and Section 6.3.1, Host-to-DSP Data Path, on page 6-6). In a PCI mode (DCTR[HM] = $1) memory space read transaction, the HRXS is accessed if the PCI address is between HI32_base_address: $01C and HI32_base_address: $FFFC. The host processor views HRXS as a 16377 Dword read-only memory.
Host-Side Programming Model The HTXR receives data from the HI32 data pins via the data transfer format converter (HDTFC). The value of the HCTR[FC] bits or the HCTR[HTF] bits define which bytes of the PCI bus are written to the HTXR and their alignment. (See Table 6-3, HI32 (PCI Master Data Transfer Formats, on page 6-8, Section 6.3.1, Host-to-DSP Data Path, on page 6-6 and Table 6-4, Transmit Data Transfer Format, on page 6-9).
Host-Side Programming Model 6.8.7 Device ID/Vendor ID Configuration Register (CDID/CVID) r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8 DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0 15 14 13 12 11 10 9 VID15 VID14 VID13 VID12 VID11 VID10 VID9 8 7 6 5 4 3 2 1 0 VID8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Figure 6-16.
Host-Side Programming Model read/write command is in progress and the PCI address is $04. In Self-Configuration mode (DCTR[DCTR[HM]] = $5), the DSP56300 core can indirectly access the CCMR (see Section 6.5.5, Self-Configuration Mode (DCTR[HM] = $5), on page 6-16). The host writes to CSTR/CCMR in accordance with the byte enables. Byte lanes that are not enabled are not written, and the corresponding bits remain unchanged. The host can access CSTR/CCMR only in PCI mode (DCTR[HM]≠$1). Table 6-26.
Host-Side Programming Model Table 6-26. Status/Command Configuration Register (CSTR/CCMR) Bit Definitions Bit Number Bit Name Reset Value Description 23 FBBC 0 Fast Back-to-Back Capable (hardwired to one) Indicates that the HI32 supports fast back-to-back transactions as a target in PCI mode (DCTR[HM] = $1). This bit is hardwired to one. 22–10 0 Reserved. Write to zero for future compatibility. 9 0 Not implemented. Write to zero for future compatibility.
Host-Side Programming Model 6.8.9 Class Code/Revision ID Configuration Register (CCCR/CRID) r( 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 Figure 6-18.
Host-Side Programming Model 6.8.10 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS) r( 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 LT7 LT6 LT5 LT4 LT3 LT2 LT1 LT0 23 22 21 20 19 18 17 16 HT7 HT6 HT5 HT4 HT3 HT2 HT1 HT0 7 6 5 4 3 2 1 0 CLS7 CLS6 CLS5 CLS4 CLS3 CLS2 CLS2 CLS0 Not implemented. Read and write as zero for future compatibility. Figure 6-19.
Host-Side Programming Model Table 6-28. Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 15–8 LT[7–0] 0 Latency Timer (High) In PCI mode (HM = $1), specify the value of the latency timer for this PCI bus master in units of PCI bus clock cycles. In the Universal Bus modes (HM = $2,$3) with HIRH cleared, LT[7–0] specify the duration of the HIRQ pulse in units of DSP56300 core clock cycles.
Host-Side Programming Model 6.8.11 Memory Space Base Address Configuration Register (CBMA) r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PM31 PM30 PM29 PM28 PM27 PM26 PM25 PM24 PM23/ PM22/ PM21/ PM20/ PM19/ PM18/ PM17/ PM16/ GB10 GB9 GB98 GB7 GB6 GB5 GB4 GB3 15 14 13 12 11 10 9 PM15 PM14 PM13 PM12 PM11 PM10 PM9 8 7 6 5 4 3 2 1 0 PM8 PM7 PM6 PM5 PM4 PF MS1 MS0 MSI Hardwired to zero Figure 6-20.
Host-Side Programming Model Table 6-29. Memory Space Base Address Configuration Register (CBMA) Bit Definitions (Continued) Bit Number Bit Name Reset Value 15–4 PM[15–4] 0 3 PF 2–1 MS[1 –0] 0 MSI Description Memory Base Address Low (Hardwired to zeros) 0 (Hardwired) Pre-Fetch (Hardwired to zero) Indicates whether the data is pre-fetchable. PF is hardwired to zero and is unaffected by any type of reset.
Host-Side Programming Model Use the following procedure for writing to the CSID: 1. Power up the DSP56301. The default CSID value is $00000000. The HI32 is in the Personal Software Reset state (HM = $0) and responds to memory and configuration space PCI transactions with a retry event. 2. Boot the DSP56301through the EPROM or SCI. a. The program downloaded to the DSP56301 should do the following: — Enter the Self-Configuration mode (HM = $5) and write the CSID.
Host-Side Programming Model 6.8.13 Interrupt Line-Interrupt Pin Configuration Register(CILP) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 MG7 MG6 MG5 MG4 MG3 MG2 MG1 MG0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 IL7 IL6 IL5 IL4 IL3 IL2 IL1 IL0 Hardwired to zero Hardwired to one Figure 6-22.
HI32 Programming Model/Quick Reference 6.
HI32 Programming Model/Quick Reference HI32 Registers—Quick Reference Bit Reset Type Reg Comments Num Mnemonic DCTR cont.
HI32 Programming Model/Quick Reference HI32 Registers—Quick Reference Bit Reset Type Reg Comments Num Mnemonic DPMC 15-0 21-16 Name Val HS PH PS written only if MARQ = 1 $0000 - - written only if MARQ = 1 $0 - - Transmit Receive written only if 32 bit mode 32 bit mode MARQ = 1 3 Right, zero ext .3 LSBs 3 Right, sign ext .
HI32 Programming Model/Quick Reference HI32 Registers—Quick Reference Bit Reset Type Reg Comments Num Mnemonic DPSR cont.
HI32 Programming Model/Quick Reference HI32 Registers—Quick Reference Bit Reset Type Reg Comments Num Mnemonic Name Val Function HS PH PS Host Side HCTR 1 2 5-3 TREQ Transmit Request Enable 0 1 HTRQ interrupt disabled HTRQ interrupt enabled - 0 - RREQ Receive Request Enable 0 1 HRRQ interrupt disabled HRRQ interrupt enabled - 0 - - 0 - DMA Enable (ISA/EISA) 0 1 HI32 does not support DMA transfers HI32 supports ISA-DMA type transfers - 0 - Slave Fetch Type 0 1 Pre-fetch
HI32 Programming Model/Quick Reference HI32 Registers—Quick Reference Bit Reset Type Reg Comments Num Mnemonic HCVR HC Name Host Command 0 7-1 HV[6–0] HNMI 15 HRXM HRXS HTXR CVID CDID 0 1 Function no host command pending host command pending Host Command Vector Host Non Maskable Interrupt Request 0 1 HS PH PS cleared when the HC interrupt request is serviced - - 0 default vector - a maskable interrupt request a non-maskable interrupt request - default vector 0 31-0 Host Master
HI32 Programming Model/Quick Reference HI32 Registers—Quick Reference Bit Reset Type Reg Comments Num Mnemonic CCMR CSTR cont.
Chapter 7 Enhanced Synchronous Serial Interface (ESSI) The ESSI provides a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals. The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator. There are two independent and identical ESSIs in the DSP56301: ESSI0 and ESSI1. For simplicity, a single generic ESSI is described here.
ESSI Enhancements Note: This synchronous interface should not be confused with the asynchronous channels mode of the ESSI, in which separate clocks are used for the receiver and transmitter. In that mode, the ESSI is still a synchronous device because all transfers are synchronized to these clocks. Pin notations for the generic ESSI refer to the analogous pin of ESSI0 (PCx) and ESSI1 (PDx). Additional synchronization signals delineate the word frames.
ESSI Data and Control Signals 7.2 ESSI Data and Control Signals Three to six signals are required for ESSI operation, depending on the operating mode selected. The serial transmit data (STD) signal and serial control (SC0 and SC1) signals are fully synchronized to the clock if they are programmed as transmit-data signals. 7.2.1 Serial Transmit Data Signal (STD) The STD signal transmits data from the serial transmit shift register. STD is an output when data is transmitted from the TX0 shift register.
ESSI Data and Control Signals 7.2.4 Serial Control Signal (SC0) ESSI0: SC00; ESSI1: SC10 To determine the function of the SC0 signal, select either Synchronous or Asynchronous mode, according to Table 7-2. In Asynchronous mode, this signal is used for the receive clock I/O. In Synchronous mode, this signal is the transmitter data out signal for transmit shift register TX1 or for serial flag I/O. A typical application of serial flag I/O would be multiple device selection for addressing in codec systems.
ESSI Data and Control Signals Table 7-2.
Operation 7.2.6 Serial Control Signal (SC2) ESSI0:SC02; ESSI1:SC12 SC2 is a frame sync I/O signal for both the transmitter and receiver in Synchronous mode and for the transmitter only in Asynchronous mode. The direction of this signal is determined by the SCD2 bit in the CRB. When configured as an output, this signal outputs the internally generated frame sync signal.
Operation ESSI, use an ESSI individual reset when you change the ESSI control registers (except for bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE). Here is an example of how to initialize the ESSI. 1. Put the ESSI in its individual reset state by clearing the PCR bits. 2. Configure the control registers (CRA, CRB) to set the operating mode. Disable the transmitters and receiver by clearing the TE[2–0] and RE bits. Set the interrupt enable bits for the operating mode chosen. 3.
Operation n Note: The maximum time it takes to service a receive last slot interrupt should not exceed N – 1 ESSI bits service time (where N is the number of bits the ESSI can transmit per time slot). n ESSI transmit data with exception status: Occurs when the transmit exception interrupt is enabled, at least one transmit data register of the enabled transmitters is empty, and a transmitter underrun error has occurred. This exception sets the SSISR[TUE] bit.
Operation To configure an ESSI exception, perform the following steps: 1. Configure the interrupt service routine (ISR): a. Load vector base address register VBA (b23:8) b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined, I_VEC must be defined for the assembler before the interrupt equate file is included. c. Load the exception vector table entry: two-word fast interrupt, or jump/branch to p:I_SI0TD subroutine (long interrupt). 2.
Operating Modes: Normal, Network, and On-Demand 7.4 Operating Modes: Normal, Network, and On-Demand The ESSI has three basic operating modes and several data and operation formats. These modes are programmed via the ESSI control registers. The data and operation formats available to the ESSI are selected when you set or clear control bits in the CRA and CRB. These control bits are WL[2–1], MOD, SYN, FSL[1–0], FSR, FSP, CKP, and SHFD. 7.4.
Operating Modes: Normal, Network, and On-Demand 7.4.2 Synchronous/Asynchronous Operating Modes The transmit and receive sections of the ESSI interface are synchronous or asynchronous. The transmitter and receiver use common clock and synchronization signals in Synchronous mode; they use separate clock and sync signals in Asynchronous mode. The CRB[SYN] bit selects synchronous or asynchronous operation. When the SYN bit is cleared, the ESSI TX and RX clocks and frame sync sources are independent.
Operating Modes: Normal, Network, and On-Demand 7.4.5 Frame Sync Length for Multiple Devices The ability to mix frame sync lengths is useful to configure systems in which data is received from one type of device (for example, codec) and transmitted to a different type of device. CRB[FSL0] controls whether RX and TX have the same frame sync length. n If CRB[FSL0] is cleared, both RX and TX have the same frame sync length. n If CRB[FSL0] is set, RX and TX have different frame sync lengths.
Operating Modes: Normal, Network, and On-Demand 7.4.8 Byte Format (LSB/MSB) for the Transmitter Some devices, such as CODECs, require a MSB-first data format. Other devices, such as those that use the AES–EBU digital audio format, require the LSB first. To be compatible with all formats, the shift registers in the ESSI are bidirectional. You select either MSB or LSB by programming CRB[SHFD].
ESSI Programming Model 7.
ESSI Programming Model Table 7-3. ESSI Control Register A (CRA) Bit Definitions Bit Number Bit Name 23 Reset Value Description 0 Reserved. Write to 0 for future compatibility. 22 SSC1 0 Select SC1 Controls the functionality of the SC1 signal.
ESSI Programming Model Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 18 ALC 0 Alignment Control The ESSI handles 24-bit fractional data. Shorter data words are left-aligned to the MSB, bit 23. For applications that use 16-bit fractional data, shorter data words are left-aligned to bit 15. The ALC bit supports shorter data words. If ALC is set, received words are left-aligned to bit 15 in the receive shift register.
ESSI Programming Model TX 1 or Flag0 Out Flag0 In CRB(TE1) CRB(OF0) SSISR(IF0) (Sync Mode) (Sync Mode) CRA(WL2–0) RX Word Clock /8, /12, /16, /24, /32 Sync: TX 1, or Flag0 Async: RX clk 0 SCD0 = 0 SYN = 0 CRB(SYN) = SCn0 1 2 3 4,5 RX Shift Register SYN = 0 SCD0 = 1 RCLOCK SYN = 1 CRB(SCD0) CRA(WL2–0) TCLOCK 0 1 Internal Bit Clock TX Word Clock /8, /12, /16, /24, /32 2 3 4,5 SCKn Sync: TX/RX clk Async: TX clk TX Shift Register CRB(SCKD) /2 CRA(PSR) CRA(PM7:0) /1 or /8 /1 to /25
ESSI Programming Model 7.5.2 ESSI Control Register B (CRB) CRB is one of two read/write control registers that direct the operation of the ESSI (see Figure 7-5). The CRB bit definitions are presented in Table 7-4. CRB controls the ESSI multifunction signals, SC[2–0], which can be used as clock inputs or outputs, frame synchronization signals, transmit data signals, or serial I/O flag signals.
ESSI Programming Model Enable (TEIE) bits. In Network mode, if you clear the appropriate TE bit and set it again, then you disable the corresponding transmitter (0, 1, or 2) after transmission of the current data word. The transmitter remains disabled until the beginning of the next frame. During that time period, the corresponding SC (or STD in the case of TX0) signal remains in a high-impedance state. The CRB bits are cleared by either a hardware RESET signal or a software RESET instruction. Table 7-4.
ESSI Programming Model Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 18 TIE 0 Transmit Interrupt Enable Enables/disables a DSP transmit interrupt; the interrupt is generated when both the TIE and the TDE bits in the ESSI status register are set. When TIE is cleared, the transmit interrupt is disabled. The transmit interrupt is documented in Section 7.3.3.
ESSI Programming Model Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 15 TE1 0 Transmit 1 Enable Enables the transfer of data from TX1 to Transmit Shift Register 1. TE1 is functional only when the ESSI is in Synchronous mode and is ignored when the ESSI is in Asynchronous mode. When TE1 is set and a frame sync is detected, transmitter 1 is enabled for that frame.
ESSI Programming Model Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 11 CKP 0 Clock Polarity Controls which bit clock edge data and frame sync are clocked out and latched in. If CKP is cleared, the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock.
ESSI Programming Model Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 4 SCD2 0 Serial Control Direction 2 Controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is an output; when SCD2 is cleared, SC2 is an input. Note: Programming the ESSI to use an internal frame sync (that is, SCD2 = 1 in CRB) causes the SC2 and SC1 signals to be programmed as outputs.
ESSI Programming Model Word Length: FSL1 = 0, FSL0 = 0 Serial Clock RX, TX Frame SYNC RX, TX Serial Data Note: Data Data Frame sync occurs while data is valid. One Bit Length: FSL1 = 1, FSL0 = 0 Serial Clock RX, TX Frame SYNC RX, TX Serial Data Note: Data Data Frame sync occurs for one bit time preceding the data.
ESSI Programming Model Asynchronous (SYN = 0) Transmitter Clock SCK ESSI Bit Clock STD Frame SYNC External Transmit Clock External Transmit Frame SYNC SC2 Internal Clock Internal Frame SYNC External Receive Clock External Receive Frame SYNC SC0 SC1 Clock Frame SYNC SRD Receiver Note: Transmitter and receiver may have different clocks and frame syncs.
Serial Clock SSI Control Register B (CRB) (READ/WRITE) Frame SYNC DSP56301 User’s Manual Figure 7-8. CRB MOD Bit Operation Transmitter Interrupt (or DMA Request) and Serial Data Data Data Receiver Interrupt (or DMA Request) and Flags Note: Interrupts occur and data is transferred once per frame sync.
ESSI Programming Model Frame SYNC (FSL0 = 0, FSL1 = 0) Frame SYNC (FSL0 = 0, FSL1 = 1) Data Out Flags Slot 0 Wait Slot 0 Figure 7-9. Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) Frame SYNC (FSL0 = 0, FSL1 = 0) Frame SYNC (FSL0 = 0, FSL1 = 1) Data Flags SLOT 0 SLOT 1 SLOT 0 SLOT 1 Figure 7-10.
ESSI Programming Model 7.5.3 ESSI Status Register (SSISR) The SSISR is a read-only status register by which the DSP reads the ESSI status and serial input flags. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDF TDE ROE TUE RFS TFS IF1 IF0 —Reserved bit; read as 0; write to 0 0 for future compatibility. (ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7) Figure 7-11. ESSI Status Register (SSISR) Table 7-5.
ESSI Programming Model Table 7-5. ESSI Status Register (SSISR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 3 RFS 0 Receive Frame Sync Flag When set, the RFS bit indicates that a receive frame sync occurred during the reception of a word in the serial receive data register. In other words, the data word is from the first time slot in the frame.
ESSI Programming Model 7.5.5 ESSI Receive Data Register (RX) The Receive Data Register (RX) is a 24-bit read-only register that accepts data from the receive shift register as it becomes full, according to Figure 7-12 and Figure 7-13. The data read is aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB is bit 23, and the least significant byte is unused. When the ALC bit is set, the MSB is bit 15, and the most significant byte is unused. Unused bits are read as 0.
ESSI Programming Model 23 87 16 15 Receive High Byte 7 Receive Middle Byte 0 ESSI Receive Data Register Receive Low Byte 07 0 7 0 87 16 15 Serial 23 Receive Receive High Byte Receive Middle Byte Receive Low Byte Shift 0 7 07 Register 7 0 0 24 Bit 16 Bit SRD 12 Bit 8 Bit WL1, WL0 MSB LSB 8-bit Data 0 MSB 0 Least Significant Zero Fill 0 LSB 12-bit Data LSB MSB 16-bit Data MSB LSB 24-bit Data Note: (a) Receive Registers 23 16 15 Transmit High Byte Data is received MSB first if SHF
ESSI Programming Model 23 87 16 15 Receive High Byte Receive Middle Byte 0 ESSI Receive Data Register (Read Only) Receive Low Byte 7 0 7 07 0 23 16 15 07 0 Receive High Byte SRD Receive Middle Byte 7 0 7 MSB ESSI Receive Shift Register Receive Low Byte 07 0 LSB 8-bit Data 0 MSB 0 Least Significant Zero Fill 0 LSB 12-bit Data LSB MSB 16-bit Data MSB LSB 24-bit Data (a) Receive Registers Data is received MSB first if SHFD = 0. 24-bit fractional format (ALC = 0).
ESSI Programming Model 7.5.7 ESSI Transmit Data Registers (TX[2–0]) ESSI0:TX20, TX10, TX00; ESSI1:TX21, TX11, TX01 TX2, TX1, and TX0 are 24-bit write-only registers. Data written into these registers automatically transfers to the transmit shift registers. (See Figure 7-12 and Figure 7-13.) The data transmitted (8, 12, 16, or 24 bits) is aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB is Bit 23. When ALC is set, the MSB is Bit 15.
ESSI Programming Model 23 22 21 20 19 18 17 16 15 14 13 12 TS31 TS30 TS29 TS28 11 10 9 8 7 6 5 4 3 2 1 0 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16 —Reserved bit; read as 0; write to 0 0 for future compatibility. (ESSI0 X:$FFFFB3, ESSI1 X:$FFFFA3) Figure 7-15. ESSI Transmit Slot Mask Register B (TSMB) TSMA and TSMB (as in Figure 7-12 and Figure 7-13) can be seen as a single 32-bit register, TSM.
ESSI Programming Model 7.5.10 Receive Slot Mask Registers (RSMA, RSMB) Both receive slot mask registers are read/write registers. In Network mode, the receiver(s) use these registers to determine which action to take in the current time slot. Depending on the setting of the bits, the receiver(s) either tri-state the receiver(s) data signal(s) or receive a data word and generate a receiver full condition.
GPIO Signals and Registers 7.6 GPIO Signals and Registers The functionality of each ESSI port is controlled by three registers: port control register (PCRC, PCRD), port direction register (PRRC, PRRD), and port data register (PDRC, PDRD). 7.6.1 Port Control Registers (PCRC and PCRD) The read/write 24-bit PCRs control the functionality of the signal lines for ESSI0 and ESSI1. Each of the PCR bits 5–0 controls the functionality of the corresponding signal line.
GPIO Signals and Registers 7.6.2 Port Direction Registers (PRRC and PRRD) The read/write PRRC and PRRD control the data direction of the ESSI0 and ESSI1 GPIO signals when they are enabled by the associated Port Control Register (PCRC or PCRD, respectively). When PRRC[i] or PRRD[i] is set, the corresponding signal is an output (GPO) signal. When PRRC[i] or PRRD[i] is cleared, the corresponding signal is an input (GPI) signal.
GPIO Signals and Registers 7.6.3 Port Data Registers (PDRC and PDRD) Bits 5–0 of the read/write PDRs write data to or read data from the associated ESSI GPIO signal lines if they are configured as GPIO signals. If a port signal PC[i] or PD[i] is configured as an input (GPI), the corresponding PDRC[i] pr PDRD[i] bit reflects the value present on the input signal line.
Chapter 8 Serial Communication Interface (SCI) The DSP56301 Serial Communication Interface (SCI) provides a full-duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without additional logic to peripherals that use TTL-level signals. With a small amount of additional logic, the SCI can connect to peripheral interfaces that have non-TTL level signals, such as RS-232, RS-422, and so on.
Operating Modes transmit and receive clock compatible with the Intel 8051 serial interface mode 0 synchronizes data. Asynchronous modes are compatible with most UART-type serial devices. Standard RS-232 communication links are supported by these modes. Multidrop Asynchronous mode is compatible with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial interface. 8.1.
I/O Signals message and optionally transmit an acknowledgment to the sender. The particular message format and protocol used are determined by the user’s software. 8.1.3.1 Transmitting Data and Address Characters To send data, the 8-bit data character must be written to the STX register. Writing the data character to the STX register sets the ninth bit in the frame to zero, which indicates that this frame contains data.
I/O Signals However, at least one of the three signals must be selected as an SCI signal to release the SCI from reset. To enable SCI interrupts, program the SCI control registers before any of the SCI signals are programmed as SCI functions. In this case, only one transmit interrupt can be generated because the Transmit Data Register is empty. The timer and timer interrupt operate regardless of how the SCI pins are configured, either as SCI or GPIO. 8.2.
SCI After Reset 8.3 SCI After Reset There are several different ways to reset the SCI: n n n n Hardware RESET signal Software RESET instruction: Both hardware and software resets clear the port control register bits, which configure all I/O as GPIO input. The SCI remains in the Reset state as long as all SCI signals are programmed as GPIO (PC2, PC1, and PC0 all are cleared); the SCI becomes active only when at least one of the SCI I/O signals is not programmed as GPIO.
SCI Initialization Table 8-1.
SCI Initialization There are two workarounds for this issue: n Enable an SCI pin other than SCLK. n In the next instruction, enable the remaining SCI pins, including the SCLK pin. Following is an example of one way to initialize the SCI: 1. Ensure that the SCI is in its individual reset state (PCRE = $0). 2. Configure the control registers (SCR, SCCR) according to the operating mode, but do not enable transmitter (TE = 0) or receiver (RE = 0).
Exceptions After the current character transmission, if two or more of these commands are set, the transmitter executes them in the following order: preamble, break, data. 8.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A) When the DSP comes out of reset, it checks the MODD, MODC, MODB, and MODA pins and sets the corresponding mode bits in the Operating Mode Register (OMR). If the mode bits are write to 0010 or 1010, respectively, the DSP loads the program RAM from the SCI.
SCI Programming Model 4. SCI idle line occurs when the receive line enters the idle state (10 or 11 bits of ones). This interrupt is latched and then automatically reset when the interrupt is accepted. This interrupt is enabled by SCR[10] (ILIE). 5. SCI timer occurs when the baud rate counter reaches zero. This interrupt is automatically reset when the interrupt is accepted. This interrupt is enabled by SCR[13] (TMIE). 8.
SCI Programming Model Mode 0 0 0 0 8-bit Synchronous Data (Shift Register Mode) WDS2 WDS1 WDS0 TX (SSFTD = 1) D7 D6 D5 D4 D3 D2 D1 D0 One Byte From Shift Register Mode 2 0 1 0 10-bit Asynchronous (1 Start, 8 Data, 1 Stop) WDS2 WDS1 WDS0 TX (SSFTD = 1) Start Bit D7 D6 D5 D4 D3 D2 D1 D0 or Data Type Stop Bit Mode 4 1 0 0 11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop) WDS2 WDS1 WDS0 TX (SSFTD = 1) Start Bit D7 D6 D5 D4 D3 D2 D1 D0 or Data Type Even P
SCI Programming Model Mode 0 0 0 0 8-bit Synchronous Data (Shift Register Mode) WDS2 WDS1 WDS0 TX (SSFTD = 0) D0 D1 D2 D3 D4 D5 D6 D7 One Byte From Shift Register Mode 2 0 1 0 10-bit Asynchronous (1 Start, 8 Data, 1 Stop) WDS2 WDS1 WDS0 TX (SSFTD = 0) Start Bit D0 D1 D2 D3 D4 D5 D6 D7 or Data Type Stop Bit Mode 4 1 0 0 11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop) WDS2 WDS1 WDS0 TX (SSFTD = 0) Start Bit D0 D1 D2 D3 D4 D5 D6 D7 or Data Type Even Pa
SCI Programming Model 8.6.1 SCI Control Register (SCR) The SCR is a read/write register that controls the serial interface operation. Seventeen of its 24 bits are defined. . 23 22 21 20 19 18 17 16 REIE 15 14 13 12 11 10 9 8 SCKP STIR TMIE TIE RIE ILIE TE RE 7 6 5 4 3 2 1 0 WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDS0 —Reserved bit; read as 0; write to 0 for future compatibility. Figure 8-3. SCI Control Register (SCR) Table 8-2.
SCI Programming Model Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 13 TMIE 0 Timer Interrupt Enable Enables/disables the SCI timer interrupt. If TMIE is set, timer interrupt requests are sent to the interrupt controller at the rate set by the SCI clock register. The timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller.
SCI Programming Model Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 9 TE 0 Description Transmitter Enable When TE is set, the transmitter is enabled. When TE is cleared, the transmitter completes transmission of data in the SCI transmit data shift register, and then the serial output is forced high (that is, idle). Data present in the SCI transmit data register (STX) is not transmitted.
SCI Programming Model Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 6 RWU 0 Description Receiver Wakeup Enable When RWU is set and the SCI is in Asynchronous mode, the wakeup function is enabled; i. e., the SCI is asleep and can be awakened by the event defined by the WAKE bit. In Sleep state, all interrupts and all receive flags except IDLE are disabled. When the receiver wakes up, RWU is cleared by the wakeup hardware.
SCI Programming Model Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 2–0 WDS[2–0] 0 8-16 Description Word Select Select the format of transmitted and received data. Asynchronous modes are compatible with most UART-type serial devices, and they support standard RS-232 communication links. Multidrop Asynchronous mode is compatible with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial interface.
SCI Programming Model 8.6.2 SCI Status Register (SSR) The SSR is a read-only register that indicates the status of the SCI. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R8 FE PE OR IDLE RDRF TDRE TRNE —Reserved bit; read as 0; write to 0 for future compatibility. Table 8-3. SCI Status Register Table 8-4. SCI Status Register (SSR) Bit Definitions Bit Number Bit Name 23–8 Reset Value Description 0 Reserved. Write to 0 for future compatibility.
SCI Programming Model Table 8-4. SCI Status Register (SSR) Bit Definitions (Continued) Bit Number Bit Name Reset Value 4 OR 0 Overrun Error Flag Set when a byte is ready to be transferred from the receive shift register to the receive data register (SRX) that is already full (RDRF = 1). The receive shift register data is not transferred to the SRX. The OR flag indicates that character(s) in the received data stream may have been lost. The only valid data is located in the SRX.
SCI Programming Model 8.6.3 SCI Clock Control Register (SCCR) The SCCR is a read/write register that controls the selection of clock modes and baud rates for the transmit and receive sections of the SCI interface. The SCCR is cleared by a hardware RESET signal. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TCM RCM SCP COD CD11 CD10 CD9 CD8 7 6 5 4 3 2 1 0 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 Reserved. Read as 0. Write to 0 for future compatibility. Figure 8-4.
SCI Programming Model Table 8-5. SCI Clock Control Register (SCCR) Bit Definitions (Continued) Bit Bit Name Number 11–0 Reset Value CD[11–0] 0 Description Clock Divider Specifies the divide ratio of the prescale divider in the SCI clock generator. A divide ratio from 1 to 4096 (CD[11–0] = $000 to $FFF) can be selected. The SCI clock determines the data transmission (baud) rate and can also establish a periodic interrupt that can act as an event timer or be used in any other timing function.
SCI Programming Model As noted in Section 8.6.1, the SCI can be configured to operate in a single Synchronous mode or one of five Asynchronous modes. Synchronous mode requires that the TX and RX clocks use the same source, but that source may be the internal SCI clock if the SCI is configured as a master device or an external clock if the SCI is configured as a slave device. Asynchronous modes may use clocks from the same source (internal or external) or different sources for the TX clock and the RX clock.
SCI Programming Model 8.6.4 SCI Data Registers The SCI data registers are divided into two groups: receive and transmit, as shown in Figure 8-7. There are two receive registers: a Receive Data Register (SRX) and a serial-to-parallel Receive Shift Register. There are also two transmit registers: a Transmit Data Register (called either STX or STXA) and a parallel-to-serial Transmit Shift Register.
SCI Programming Model the data bus are read as zeros. Similarly, when SRXM is read, the contents of SRX are placed into the middle byte of the bus, and when SRXH is read, the contents of SRX are placed into the high byte with the remaining bits are read as 0s. This way of mapping SRX efficiently packs three bytes into one 24-bit word by ORing three data bytes read from the three addresses. The SCR WDS0, WDS1, and WDS2 control bits define the length and format of the serial word.
GPIO Signals and Registers prevent overruns unless transmit interrupts are enabled. Either STX or STXA is usually written as part of the interrupt service routine. An interrupt is generated only if TDRE is set. The transmit shift register is indirectly visible via the SSR[TRNE] bit. In Synchronous mode, data is synchronized with the transmit clock. That clock can have either an internal or external source, as defined by the TCM bit in the SCCR.
GPIO Signals and Registers 8.7.2 Port E Direction Register (PRRE) The read/write PRRE controls the direction of SCI GPIO signals. When port signal[i] is configured as GPIO, PRRE[i] controls the port signal direction. When PRRE[i] is set, the GPIO port signal[i] is configured as output. When PRRE[i] is cleared, the GPIO port signal[i] is configured as input. A hardware RESET signal or a software RESET instruction clears all PRRE bits.
GPIO Signals and Registers 8-26 DSP56301 User’s Manual
Chapter 9 Triple Timer Module The timers in the DSP56301 internal triple timer module act as timed pulse generators or as pulse-width modulators. Each timer has a single signal that can function as a GPIO signal or as a timer signal. Each timer can also function as an event counter to capture an event or to measure the width or period of a signal. 9.
Overview 9.1.1 Triple Timer Module Block Diagram Figure 9-1 shows a block diagram of the triple timer module. This module includes a 24-bit Timer Prescaler Load Register (TPLR), a 24-bit Timer Prescaler Count Register (TPCR), and three timers. Each timer can use the prescaler clock as its clock source. GDB 24 24 24 TPLR TPCR 24 Timer Prescaler Load Register Timer Prescaler Count Register Timer 0 Timer 1 24-bit Counter Timer 2 CLK/2 TIO0 TIO1 TIO2 Figure 9-1.
Operation The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a listing of the timer modes and descriptions of their operations, see Section 9.3, Operating Modes, on page 9-5. . GDB 24 24 24 TCSR Control/Status Register 24 Count Register Compare Register 24 24 24 2 Timer Control Logic TIO CLK/2 Prescaler CLK TCPR TCR TLR Load Register 9 24 24 Counter = Timer interrupt/DMA request Figure 9-2. Timer Module Block Diagram 9.
Operation 9.2.2 Timer Initialization To initialize a timer, do the following: 1. Ensure that the timer is not active either by sending a reset or clearing the TCSR[TE] bit. 2. Configure the control register (TCSR) to set the timer operating mode. Set the interrupt enable bits as needed for the application. 3. Configure other registers: Timer Prescaler Load Register (TPLR), Timer Load Register (TLR), and Timer Compare Register (TCPR) as needed for the application. 4.
Operating Modes 2. Configure the interrupt trigger: a. Enable and prioritize overall peripheral interrupt functionality. IPRP (TOL[1–0]) b. Enable a specific peripheral interrupt. TCSR0 (TCIE) c. Unmask interrupts at the global level. SR (I[1–0]) d. Configure a peripheral interrupt-generating function. TCSR0 (TC[7–4]) e. Enable peripheral and associated signals. TCSR0 (TE) 9.
Operating Modes 9.3.1 Triple Timer Modes For all triple timer modes, the following points are true: n The TCSR[TE] bit is set to clear the counter and enable the timer. Clearing TCSR[TE] disables the timer. n The value to which the timer is to count is loaded into the TCPR. (This is true for all modes except the measurement modes (modes 4 through 6). n The counter is loaded with the TLR value on the first clock.
Operating Modes Mode 0 (internal clock, no timer output): TRM = 1 N = write preload M = write compare first event last event TE Clock (CLK/2 or prescale CLK) TLR N 0 Counter (TCR) TCPR N N+1 M N N+1 M TCF (Compare Interrupt if TCIE = 1) Figure 9-3.
Operating Modes 9.3.1.2 Timer Pulse (Mode 1) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Function TIO Clock 0 0 0 1 1 Timer Pulse Timer Output Internal In Mode 1, the timer generates an external pulse on its TIO signal when the timer count reaches a pre-set value. The TIO signal is loaded with the value of the TCSR[INV] bit. When the counter matches the TCPR value, TCSR[TCF] is set and a compare interrupt is generated if the TCSR[TCIE] bit is set.
Operating Modes Mode 1 (internal clock): TRM = 0 first event N = write preload M = write compare TE Clock (CLK/2 or prescale CLK) TLR N 0 Counter (TCR) TCPR N N+1 M M+1 0 1 M TCF (Compare Interrupt if TCIE = 1) TIO pin (INV = 0) pulse width = timer clock period TIO pin (INV = 1) TOF (Overflow Interrupt if TCIE = 1) Figure 9-6.
Operating Modes 9.3.1.3 Timer Toggle (Mode 2) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Function TIO Clock 0 0 1 0 2 Toggle Timer Output Internal In Mode 2, the timer periodically toggles the polarity of the TIO signal. When the timer is enabled, the TIO signal is loaded with the value of the TCSR[INV] bit. When the counter value matches the value in the TCPR, the polarity of the TIO output signal is inverted.
Operating Modes Mode 2 (internal clock): TRM = 0 first event N = write preload M = write compare TE Clock (CLK/2 or prescale CLK) TLR N 0 Counter (TCR) TCPR N N+1 M M+1 0 1 M TCF (Compare Interrupt if TCIE = 1) TIO pin (INV = 0) First toggle = M - N clock periods Second and later toggles = 2 24 clock periods TIO pin (INV = 1) TOF (Overflow Interrupt if TCIE = 1) Figure 9-8.
Operating Modes 9.3.1.4 Timer Event Counter (Mode 3) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Function TIO Clock 0 0 1 1 3 Event Counter Timer Input External In Mode 3, the timer counts external events and issues an interrupt (if interrupt enable bits are set) when the timer counts a preset number of events. The timer clock signal can be taken from either the TIO input signal or the prescaler clock output.
Operating Modes Mode 3 (internal clock): TRM = 0 N = write preload M = write compare if clock source is from TIO pin, TIO < CPUCLK + 4 first event TE Clock (TIO pin or prescale CLK) TLR N 0 Counter (TCR) TCPR N N+1 M M+1 0 1 M TCF (Compare Interrupt if TCIE = 1) TOF (Overflow Interrupt if TCIE = 1) NOTE: If INV = 1, counter is clocked on 1-to-0 clock transitions, instead of 0-to-1 transitions. Figure 9-10.
Operating Modes 9.3.2 Signal Measurement Modes The following signal measurement and pulse width modulation modes are provided: n Measurement input width (Mode 4) n Measurement input period (Mode 5) n Measurement capture (Mode 6) n Pulse width modulation (PWM) mode (Mode 7) The external signal synchronizes with the internal clock that increments the counter.
Operating Modes Mode 4 (internal clock): TRM = 1 first event N = write preload M = write compare TE Clock (CLK/2 or prescale CLK) N TLR 0 Counter N N+1 M N+1 Next 0-to-1 edge on TIO loads counter and process repeats M TCR width being measured TIO pin Interrupt Service reads TCR; width = M - N clock periods TCF (Compare Interrupt if TCIE = 1) NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO stops the counter and loads TCR with the count. Figure 9-11.
Operating Modes 9.3.2.2 Measurement Input Period (Mode 5) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Function TIO Clock 0 1 0 1 5 Input period Measurement Input Internal In Mode 5, the timer counts the period between the reception of signal edges of the same polarity across the TIO signal.
Operating Modes Mode 5 (internal clock): TRM = 0 first event N = write preload M = write compare TE Clock (CLK/2 or prescale CLK) TLR Counter N 0 N N+1 M+1 M TCR TIO pin M Counter continues counting, N +does 1 not stop. Overflow may occur (TOF=1). period being measured Interrupt Service reads TCR; period = M - N clock periods TCF (Compare Interrupt if TCIE = 1) NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO loads TCR with count and the counter with N.
Operating Modes 9.3.2.3 Measurement Capture (Mode 6) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Function TIO Clock 0 1 1 0 6 Capture Measurement Input Internal In Mode 6, the timer counts the number of clocks that elapse between when the timer starts and when an external signal is received. At the first appropriate transition of the external clock detected on the TIO signal, TCSR[TCF] is set and, if the TCSR[TCIE] bit is set, a compare interrupt is generated.
Operating Modes 9.3.3 Pulse Width Modulation (PWM, Mode 7) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Function TIO Clock 0 1 1 1 7 Pulse width modulation PWM Output Internal In Mode 7, the timer generates periodic pulses of a preset width. When the counter equals the value in the TCPR, the TIO output signal is toggled and TCSR[TCF] is set. The contents of the counter are placed into the TCR. If the TCSR[TCIE] bit is set, a compare interrupt is generated.
Operating Modes Period = $FFFFFF - TLR + 1 Duty cycle = ($FFFFFF - TCPR) Ensure that TCPR > TLR for correct functionality Mode 7 (internal clock): TRM = 1 N = write preload M = write compare first event TE Clock (CLK/2 or prescale CLK) N TLR 0 Counter (TCR) M N M+1 0 N M TCPR TCF (Compare Interrupt if TCIE = 1) TCF (Overflow Interrupt if TDIE = 1) TIO pin (INV = 0) TIO pin (INV = 1) Pulse width Period Figure 9-16.
Operating Modes Period = $FFFFFF - TLR + 1 Duty cycle = ($FFFFFF - TCPR) Ensure that TCPR > TLR for correct functionality Mode 7 (internal clock): TRM = 0 N = write preload M = write compare first event TE Clock (CLK/2 or prescale CLK) N TLR 0 Counter (TCR) M N M+1 0 1 2 M TCPR TCF (Compare Interrupt if TCIE = 1) TCF (Overflow Interrupt if TDIE = 1) TIO pin (INV = 0) TIO pin (INV = 1) Pulse width Period NOTE: On overflow, TCR is loaded with the value of TLR. Figure 9-17.
Operating Modes 9.3.4 Watchdog Modes The following watchdog timer modes are provided: n Watchdog Pulse n Watchdog Toggle 9.3.4.1 Watchdog Pulse (Mode 9) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Function TIO Clock 1 0 0 1 9 Pulse Watchdog Output Internal In Mode 9, the timer generates an external signal at a preset rate. The signal period is equal to the period of one timer clock.
Operating Modes Mode 9 (internal clock): TRM = 0 N = write preload M = write compare (Software does not reset watchdog timer; watchdog times out) first event TRM = 1 is not useful for watchdog function TE Clock (CLK/2 or prescale CLK) N TLR 0 Counter (TCR) N N+1 M M+1 0 1 M TCPR TCF (Compare Interrupt if TCIE = 1) TOF (Overflow Interrupt if TOIE = 1) float TIO pin (INV = 0) float TIO pin (INV = 1) pulse width = timer clock period low high TIO can connect to the RESET pin, internal hardw
Operating Modes 9.3.4.2 Watchdog Toggle (Mode 10) Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Function TIO Clock 1 0 1 0 10 Toggle Watchdog Output Internal In Mode 10, the timer toggles an external signal after a preset period. The TIO signal is set to the value of the INV bit.When the counter equals the value in the TCPR, TCSR[TCF] is set, and a compare interrupt is generated if the TCSR[TCIE] bit is also set.
Triple Timer Module Programming Model 9.3.4.3 Reserved Modes Modes 8, 11, 12, 13, 14, and 15 are reserved. 9.3.5 Special Cases The following special cases apply during wait and stop state. n Timer behavior during wait — Timer clocks are active during the execution of the WAIT instruction and timer activity is undisturbed. If a timer interrupt is generated, the DSP56301 leaves the wait state and services the interrupt.
Triple Timer Module Programming Model 23 0 Timer Prescaler Load Register (TPLR) TPLR = $FFFF83 23 0 Timer Prescaler Count Register (TPCR) TPLR = $FFFF82 23 22 21 20 19 18 17 16 Timer Control/Status Register (TCSR) TCF TOF 15 14 PCE 7 6 TC3 23 13 12 11 DO DI DIR 5 4 3 TC2 TC1 TC0 10 9 8 TRM INV 2 1 TCIE TOIE TCSR0 = $FFFF8F TCSR1 = $FFFF8B TCSR2 = $FFFF87 0 TE 0 Timer Load Register (TLR) TLR0 = $FFFF8E TLR1 = $FFFF8A TLR2 = $FFFF86 23 0 Timer Compare Register (TCPR) T
Triple Timer Module Programming Model 9.4.2 Timer Prescaler Load Register (TPLR) The TPLR is a read/write register that controls the prescaler divide factor (that is, the number that the prescaler counter loads and begins counting from) and the source for the prescaler input clock. 23 22 21 20 19 18 17 16 15 14 13 12 PS1 PS0 PL20 PL19 PL18 PL17 PL16 PL15 PL14 PL13 PL12 11 10 9 8 7 6 5 4 3 2 1 0 PL11 PL10 PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 — Reserved bit.
Triple Timer Module Programming Model 9.4.3 Timer Prescaler Count Register (TPCR) The TPCR is a read-only register that reflects the current value in the prescaler counter. 23 22 21 20 19 18 17 16 15 14 13 12 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12 11 10 9 8 7 6 5 4 3 2 1 0 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Reserved bit; read as 0; write to 0 for future compatibility Figure 9-22. Timer Prescaler Count Register (TPCR) Table 9-2.
Triple Timer Module Programming Model Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 21 TCF 0 Timer Compare Flag Indicate that the event count is complete. In timer, PWM, and watchdog modes, the TCF bit is set after (M – N + 1) events are counted. (M is the value in the compare register and N is the TLR value.) In measurement modes, the TCF bit is set when the measurement completes. Writing a one to the TCF bit clears it.
Triple Timer Module Programming Model Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 11 DIR 0 Direction Determines the behavior of the TIO signal when it functions as a GPIO signal. When DIR is set, the TIO signal is an output; when DIR is cleared, the TIO signal is an input. The TIO signal functions as a GPIO signal only when the TC[3–0] bits are cleared.
Triple Timer Module Programming Model Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 7–4 TC[3–0] 0 Timer Control Control the source of the timer clock, the behavior of the TIO signal, and the Timer mode of operation. Section 9.3, Operating Modes, on page 9-5 describes the timer operating modes in detail.
Triple Timer Module Programming Model Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued) Bit Number Bit Name Reset Value Description 2 TCIE 0 Timer Compare Interrupt Enable Enables/disables the timer compare interrupts. When set, TCIE enables the compare interrupts. In the timer, pulse width modulation (PWM), or watchdog modes, a compare interrupt is generated after the counter value matches the value of the TCPR.
Triple Timer Module Programming Model Table 9-4. Inverter (INV) Bit Operation (Continued) TIO Programmed as Input TIO Programmed as Output Mode INV = 0 4 5 6 INV = 1 Width of the high input pulse is measured. Width of the low input pulse is measured. Period is measured between the rising edges of the input signal. Period is measured between the falling edges of the input signal. Event is captured on the rising edge of the signal from the TIO signal.
Triple Timer Module Programming Model 9.4.6 Timer Compare Register (TCPR) The TCPR is a 24-bit read/write register that contains the value to be compared to the counter value. These two values are compared every timer clock after TCSR[TE] is set. When the values match, the timer compare flag bit is set and an interrupt is generated if interrupts are enabled (that is, the timer compare interrupt enable bit in the TCSR is set). The TCPR is ignored in measurement modes. 9.4.
Appendix A Bootstrap Program This appendix lists the bootstrap program for the DSP56301. ; BOOTSTRAP CODE FOR DSP56301 - (C) Copyright 1996,1999 Motorola Inc. ; Original June 18, 1996. ; Revised Februaury 1999 to add burnin and serial eprom. ; ; Bootstrap through the Host Interface, External EPROM or SCI. ; ; This is the Bootstrap program contained in the DSP56301 ; ; 3K Boot ROM (K30A only).
; 7-0). The memory is selected by the Address Attribute AA1 and is ; accessed with 31 wait states. ; ; The EPROM bootstrap code expects first to read 3 bytes specifying the ; number of program words, then 3 bytes specifying the address to ; start loading the program words, and then 3 bytes for each program word ; to be loaded. The number of words, the starting address, and the program ; words are read least significant byte first followed by the mid and ; then by the most significant byte.
; Host boot program verify that the HI32 is operational by reading ; the status register (HSTR) and confirming that its value is $3.
; correspondingly drive the 24-bit data mapped into the 32-bit PCI bus word. ; ; Note that for the synchronization purposes, the DSP-to-PCI clock ratio ; should be more than 5/3. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=x101, then it loads the program RAM from the Host ; Interface programmed to operate in the Universal Bus mode supporting ; ISA (slave) glue less connection.
; HA[10] <- SBHE_ ; selects HI32 (base address 10011111) ; HA[9] <- SA[0] ; selects HI32 (base address 10011111) ; HA[8:3] <- SA[9:4] ; selects HI32 (base address 10011111) ; HA[2:0] <- SA[3:1] ; selects HTXR registers ; HD[15:0] - SD[15:0] ; Data bus ; HD[23:16] - Not connected ; High Data Bus - Should be pulled up or down ; HDBEN_ -> OE_ ; Output enable of transcievers ; HDBDR -> DIR ; Direction of transcievers ; HSAK_ -> IO16_ ; 16 bit data word ; HBS_ <- Vcc ; Bus Strobe disabled ; HAEN <- AEN ; DMA cyc
; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=0100, then it loads the program RAM from a SPI ; compatible Serial EPROM connected to the SCI interface as in the scheme ; below: ; ; ; ___________ __________ ; DSP56301 | | SEEPROM ; | | ; SCI(SCLK)|-----------------------|SCK ; | | ; SCI(TXD)|-----------------------|SIN ; | | ; SCI(RXD)|-----------------------|SOUT ; | | ; | | ; | |__ ; AA1 |-----------------------|CS ; | | ; ___________| |__________ ; ; The S
M_SCTE EQU M_TDRE EQU M_RDRF EQU M_PCRE M_DCTR M_DPMC M_DPAR M_DSR M_DRXR M_AAR1 M_PDRC M_PRRC SCK0 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 9 1 2 ; SCI Transmitter Enable ; Transmit Data Register Empty ; Receive Data Register Full $FFFF9F $FFFFC5 $FFFFC7 $FFFFC8 $FFFFC9 $FFFFCB $FFFFF8 $FFFFBD $FFFFBE $3 ; Port E Control register ; DSP CONTROL REGISTER (DCTR) ; DSP PCI MASTER CONTROL REGISTER (DPMC) ; DSP PCI ADDRESS REGISTER (DPAR) ; DSP STATUS REGISTER (DSR) ; DSP RECEIVE DATA FIFO (DRXR) ; Address At
bra
; Switch to ISA mode movep X0,X:M_DCTR move #$010020,y1 ; Software personal reset ; width 16, offset 32 ; (also used as replacment to needed NOP after sw reset!) movep #$3a0000,X:M_DCTR ; ; ; ; ; ; ; HM=$3 (UB) HIRD=1 (HIRQ_ pin - drive high enabled) HIRH=0 (HIRQ_ pin - handshake disabled) HRSP=1 (HRST pin - active low) HDRP=0 (HDRQ pin - active high) HTAP=0 (HTA pin - active high) HDSM=0 (Data-strob pin mode enabled) ; read the "magic sequence" 32 consecutive words with value $37 _LBLC do #32,_LOOP3 ;
movep X:M_DRXR,y0 insert x1,x0,a insert y1,y0,a move a1,r0 move a0,a1 ; Download P memory through UB lsr a r0,r1 ; ; ; ; ; Store starting address concatenate next 16-bit word concatenate next 16-bit word start to p-mem number of words to transfer ; divide loop count by 2 and save r0 do a1,_LOOP4 ; Load instruction words jset #2,X:M_DSR,_LBLF jclr #3,X:M_DSR,_LBLE bra
bra
do #6,_LOOP9 movem p:(r2)+,a2 asr #8,a,a _LOOP9 move a1,r0 move a1,r1 do a0,_LOOP10 do #3,_LOOP11 movem p:(r2)+,a2 asr #8,a,a _LOOP11 movem a1,p:(r0)+ nop _LOOP10 bra
rep n0 mac x0,x1,a x,l:(r0)+ else ;; exercise mac, write x/y ram ;; x/y ram not symmetrical ;; write x memory clr a #start_xram,r0 move #>length_xram,n0 rep n0 mac x0,y0,a x1,x:(r0)+ ;; write y memory clr a #start_yram,r1 move #>length_yram,n1 rep n1 mac x1,y0,a x0,y:(r1)+ ;; start of xram ;; length of xram ;; exercise mac, write xram ;; start of yram ;; length of yram ;; exercise mac, write yram endif ;; write p memory clr a #start_pram,r2 move #>length_pram,n2 rep n2 move y0,p:(r2)+ if ;; check mem
;; check pram clr a #start_pram,r2 do n2,_loopp move p:(r2)+,a1 eor y0,a add a,b ;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b _loopp label1 ;;--------------------------------------------------;; toggle pin if no errors, stop execution otherwise.
bset #M_BAAP,x:M_AAR1 ; change AA1 polarity, in order to set ; it high ; (5) ACTIVATE SERIAL INTERFACE and SYNCHRONIZE movep #3,x:M_STXL ; load TX byte (READ opcode, B0) bset #M_SCTE,x:M_SCR ; activate SCI’s TX ; (6) TRANSMIT OPCODE and ADDRESS jclr #M_TDRE,x:M_SSR,* ; wait until byte is TXed (opcode, B0) movep #0,x:M_STXL ; load TX byte (address, B1) jclr #M_RDRF,x:M_SSR,* ; wait until byte is RXed (garbage, B2-) movep x:M_SRXL,a2 ; read garbage jclr #M_TDRE,x:M_SSR,* ; wait until byte is TXed (address,
A-16 DSP56301 User’s Manual
Chapter B Programming Reference This reference for programmers includes a table showing the addresses of all DSP memory-mapped peripherals, an exception priority table, and programming sheets for the major programmable DSP registers. The programming sheets are grouped in the following order: central processor, Phase Lock Loop, (PLL), Enhanced Synchronous Serial Interface (ESSI), Serial Communication Interface (SCI), Timer, and GPIO.
Table B-1.
Internal I/O Memory Map B.1 Internal I/O Memory Map Table B-2.
Internal I/O Memory Map Table B-2.
Internal I/O Memory Map Table B-2.
Internal I/O Memory Map Table B-2.
Internal I/O Memory Map Table B-2.
Internal I/O Memory Map Table B-2.
Interrupt Sources and Priorities B.2 Interrupt Sources and Priorities Table B-3.
Interrupt Sources and Priorities Table B-3.
Interrupt Sources and Priorities Table B-4.
Interrupt Sources and Priorities Table B-4.
Programming Sheets B.
Programming Sheets Date: Application: Programmer: Sheet 2 of 2 Central Processor Chip Operating Modes MOD(D:A) Mode Reset Vector 0000 0 $C00000 0001 1 $FF0000 0010 2 $FF0000 0011 3 — 0100 4 $FF0000 0101 5 $FF0000 0110 6 $FF0000 0111 7 $FF0000 1000 8 $008000 1001 9 $FF0000 1010 A $FF0000 1011 B $FF0000 1100 C $FF0000 1101 D $FF0000 1110 E $FF0000 1111 F $FF0000 External Bus Disable 0 = enable 1 = disable Stop Delay 0 = 128 K clocks 1 = 16 clocks Memory Switch Mode 0 = disable 1 = enable Core-DMA Pr
Programming Sheets Date: Application: Programmer: Sheet 1 of 2 Interrupt Priority DMA5 IPL D5L1 0 0 1 1 D5L0 0 1 0 1 Enabled No Yes Yes Yes IRQD Mode IPL — 0 1 2 IDL2 0 1 Trigger Level Neg. Edge ICL2 0 1 Trigger Level Neg. Edge IBL2 0 1 Trigger Level Neg. Edge IAL2 0 1 Trigger Level Neg.
Programming Sheets Date: Application: Programmer: Sheet 2 of 2 Interrupt Priority Triple Timer IPL TOL1 0 0 1 1 TOL0 0 1 0 1 Enabled No Yes Yes Yes IPL — 0 1 2 ESSI1 IPL S1L1 0 0 1 1 SCI IPL SCL1 0 0 1 1 SCL0 0 1 0 1 Enabled No Yes Yes Yes IPL — 0 1 2 S1L0 0 1 0 1 Enabled No Yes Yes Yes IPL — 0 1 2 ESSI0 IPL S0L1 0 0 1 1 S0L0 0 1 0 1 Enabled No Yes Yes Yes HPL1 0 0 1 1 HPL0 0 1 0 1 IPL — 0 1 2 Host IPL 23 22 21 20 19 18 17 16 15 14 13 12 11 10 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *
Programming Sheets Date: Application: Programmer: Sheet 1 of 1 PLL XTAL Disable Bit (XTLD) Predivision Factor Bits (PD0–PD3) PD3–PD0 Predivision Factor PDF $0 1 $1 2 $2 3 • • • • • • $F 16 0 = Enable Xtal Oscillator 1 = EXTAL Driven From An External Source Crystal Range Bit (XTLR) 0 = External Xtal Freq > 200KHz 1 = External Xtal Freq < 200KHz Clock Output Disable (COD) 0 = 50% Duty Cycle Clock 1 = Pin Held In High State PSTP 0 1 1 Division Factor Bits (DF0–DF2) DF2–DF0 Division Factor DF $0 20 21
Programming Sheets Date: Application: Programmer: Sheet 1 of 3 Bus Interface Unit NOTE: All BCR bits are read/write control bits.
Programming Sheets Date: Application: Programmer: Sheet 2 of 3 Bus Interface Unit NOTE: All DCR bits are read/write control bits. Refresh Prescaler, Bit 23 0 = Prescaler bypassed 1 = Divide-by-64 prescaler used Bus Software Triggered Refresh, Bit 14 0 = Refresh complete/reset 1 = Software triggered refresh request Refresh Request Rate, Bits 22–15 These read/write control bits define the refresh request rate. The bits specify a divide from 1–256 (BRF[7–0] = $00–$FF).
Programming Sheets Date: Application: Programmer: Sheet 3 of 3 Bus Interface Unit Bus Packing Enable, Bit 7 0 = Disable internal packing/unpacking logic 1 = Enable internal packing/unpacking logic Bus Y Data Memory Enable, Bit 5 0 = Disable AA pin and logic during external Y data space accesses 1 = Enable AA pin and logic during external Y data space accesses Bus Address to Compare, Bits 23–12 Bus X Data Memory Enable, Bit 4 0 = Disable AA pin and logic during external X data space accesses 1 = Enable
Programming Sheets Date: Programmer: Application: Sheet 1 of 1 DMA Address Mode, Bits 9–4 Non-Three-Dimensional Addressing Modes (D3D=0) DAM[2–0] = source DAM[5–3] = Destination DMA Interrupt Enable, Bit 22 0 = Disables DMA Interrupt 1 = Enables DMA interrupt DMA Transfer Mode, Bits 21–19 DTM[2:0] 000 001 010 011 100 101 110 111 Triggered By request request request DE request request reserved reserved DE Cleared yes yes yes yes no no Transfer Mode block transfer word transfer line transfer block tra
Programming Sheets Date: Application: Programmer: Sheet 1 of 10 Host Processor (HI32) Host Transfer Acknowledge Polarity, Bit 15 0 = HTA is active high 1 = HTA is active low HI32 Mode, Bits 22–20 Control HI32 operating modes, as follows: 000 Terminate and Reset 001 PCI 010 Universal Bus 011 Enhanced Universal Bus 100 GPIO 101 Self-Configuration 110 Reserved 111 Reserved Host Read/Write Polarity, Bit 14 0 = Host-to-DSP direction is low HRW 1 = Host-to-DSP direction is high HRW Host Data
Programming Sheets Date: Application: Programmer: Sheet 2 of 10 Host Processor (HI32) Clear Transmitter, Bit 14 0 = No data transaction pending. 1 = Clears HI32 master-to-host bus data path. Insert Address Enable, Bit 21 0 = Does not write PCI transaction address. 1 = Writes PCI transaction address to HTXR. (Ignored when HI32 is not in PCI mode. Can be set only when DPCR[RBLE]] = 1.) Transfer Complete Interrupt Enable, Bit 12 0 = Disables transfer complete interrupt requests.
Programming Sheets Date: Application: Programmer: Sheet 3 of 10 Host Processor (HI32) Data Transfer Format Control, Bits 23–22 HI32-PCI data transfer formats, as follows: PCI DSP-to-Host (data in DTXM) 00 32-bit data mode 01 Data to HAD[31–0] right-aligned and zero extended in MSB 10 Data to HAD[31–0] right-aligned and sign extended in MSB 11 Data to HAD[31–0] left-aligned and zero filled in LSB PCI Data Burst Length, Bits 21–16 The value is the desired number of burst accesses – 1.
Programming Sheets Date: Application: Programmer: Sheet 4 of 10 Host Processor (HI32) PCI Byte Enables, Bits 23–20 BE[3–0] enable byte lanes 3–0, respectively.
Programming Sheets Date: Application: Programmer: Sheet 5 of 10 Host Processor (HI32) Host Transmit Data Transfer Format, Bits 9–8 HI32 bus data transfer formats, as follows: PCI Host-to-DSP (DCTR[HM] = $1) Target Wait State Disable, Bit 19 0 = PCI wait states enabled 1 = PCI wait states disabled Modes: PCI only 00 32-bit data mode 01 3 LSBs from HAD[23–0] to HTXR/DRXR LSBs 10 3 LSBs from HAD[23–0] to HTXR/DRXR LSBs 11 3 MSBs from HAD[31–8] to HTXR/DRXR LSBs Note: Address insertion is affected
Programming Sheets Date: Application: Programmer: Sheet 6 of 10 Host Processor (HI32) Host Non-Maskable Interrupt, Bit 15 0 = Host Command Interrupt normal priority 1 = Host Command Interrupt highest priority Modes: UBM and PCI Host Command Vector, Bits 7–1 Selects host command interrupt address. Caution: Never use the reset location $0.
Programming Sheets Date: Application: Programmer: Sheet 7 of 10 Host Processor (HI32) Data Parity Reported, Bit 24 0 = No parity error reported 1 = HI32 (as master) reported data parity error Modes: PCI only Detected Parity Error, Bit 31 0 = No parity error detected 1 = Parity error detected Modes: PCI only Signaled System Error, Bit 30 0 = No signaled system error detected 1 = Signaled system error detected Modes: PCI only Fast Back-to-Back Capable, Bit 23 Always 1 (hardwired) Modes: PCI only System
Programming Sheets Date: Application: Programmer: Sheet 8 of 10 Host Processor (HI32) Header Type, Bits 23–16 Read-only; hardwired to $00 Modes: PCI only Latency Timer (High), Bits 15–8 PCI: Specifies the latency timer in PCI bus cycles UBM: Specifies duration of HIRQ pulse Modes: UBM and PCI Cache Line Size, Bits 7–0 CCLS Register Specifies cache line size (32-bit words) Modes: UBM and PCI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 *0 *0 *0 *0 *0 *0 *0 *0
Programming Sheets Date: Application: Programmer: Sheet 9 of 10 Host Processor (HI32) Memory Base Address Low, Bits 15–4 Hardwired to $000 Modes: PCI PCI Mode Base Address High, Bits 31–16 Specifies the HI32 base address in PCI mode Modes: PCI only Pre-fetch, Bit 3 Hardwired to 0 Data is not pre-fetchable Modes: PCI Memory Space, Bits 2–1 Hardwired to 00 CBMA register is 32 bits wide Modes: PCI Universal Bus Mode Base Address, Bits 23–16 Specifies the HI32 base address in UBM Modes: UBM only Memory S
Programming Sheets Date: Application: Programmer: Sheet 10 of 10 Host Processor (HI32) Subsystem ID Register, Bits 31–16 Specifies the subsystem ID Modes: PCI mode only Subsystem Vendor ID Register, Bits 31–16 Specifies the subsystem vendor ID Modes: PCI mode only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SVID[15–0] SID[15–0] HI32 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID) Reset = $00000000 Read/Write Figure B-19.
Programming Sheets Date: Application: Programmer: Sheet 1 of 3 ESSI Select SC1 as Tx#0 drive enable 0 = SC1 functions as serial I/O flag 1 = functions as driver enable of Tx#0 external buffer WL2 0 0 0 0 1 1 1 1 WL1 0 0 1 1 0 0 1 1 Word Length Control WL0 Number of bits/word 0 8 1 12 0 16 1 24 0 32 (data in first 24 bits) 1 32 (data in last 24 bits) 0 Reserved 1 Reserved Alignment Control 0 = 16-bit data left aligned to bit 23 1 = 16-bit data left aligned to bit 15 Frame Rate Divider Control DC4:0
Programming Sheets Date: Application: Programmer: Sheet 2 of 3 ESSI Clock Polarity (clk edge data & Frame Sync clocked out/in) 0 = out on rising/in on falling 1 = in on rising/out on falling Receive Exception Interrupt Enable 0 = Disable 1 = Enable Transmit Exception Interrupt Enable 0 = Disable 1 = Enable Frame Sync Polarity 0 = high level (positive) 1 = low level (negative) Receive Last Slot Interrupt Enable 0 = Disable 1 = Enable Frame Sync Relative Timing (WL Frame Sync only) 0 = with first data
Programming Sheets Date: Application: Programmer: Sheet 3 of 3 ESSI 23 SSI Transmit Slot Mask 0 = IgnoreTime Slot 1 = Active Time Slot 16 15 14 13 12 11 10 9 *0 *0 TS15 TS14 TS13 TS12 TS11 TS10 TS9 ESSI Transmit Slot Mask A (TSMA[0–1]) Reset = $FFFF 23 SSI Transmit Slot Mask 0 = IgnoreTime Slot 1 = Active Time Slot SSI Receive Slot Mask 0 = IgnoreTime Slot 1 = Active Time Slot RS15 RS14 RS13 RS12 RS11 RS10 RS9 ESSI Receive Slot Mask A (RSMA[0–1] Reset = $FFFF 23 SSI Receive Slot Mask 0 = Ignore
Programming Sheets Date: Application: Programmer: Sheet 1 of 2 SCI Word Select Bits 0 0 0 = 8-bit Synchronous Data (Shift Register Mode) 0 0 1 = Reserved 0 1 0 = 10-bit Asynchronous (1 Start, 8 Data, 1 Stop) 0 1 1 = Reserved 1 0 0 = 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop) 1 0 1 = 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop) 1 1 0 = 11-bit Multidrop (1 Start, 8 Data, Data Type, 1 Stop) 1 1 1 = Reserved Transmitter Enable 0 = Transmitter Disable 1 = Transmitter Enable Idle
Programming Sheets Date: Application: Programmer: Sheet 2 of 2 SCI TCM 0 0 1 1 RCM 0 1 0 1 TX Clock Internal Internal External External RX Clock Internal External Internal External Transmitter Clock Mode/Source 0 = Internal clock for Transmitter 1 = External clock from SCLK SCLK Pin Output Input Input Input Clock Divider Bits (CD11–CD0) CD11–CD0 Icyc Rate $000 Icyc/1 $001 Icyc/2 $002 Icyc/3 • • • • • • $FFE Icyc/4095 $FFF Icyc/4096 Mode Synchronous/Asynchronous Asynchronous only Asynchronous only
Programming Sheets Date: Application: Programmer: Sheet 1 of 3 Timers PS (1–0) 00 01 10 11 Prescaler Clock Source Internal CLK/2 TIO0 TIO1 TIO2 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 *0 PS1 8 7 6 5 4 3 2 1 0 PS0 Prescaler Preload Value (PL [20–0]) Timer Prescaler Load Register (TPLR) Reset = $000000 X:$FFFF83 Read/Write *= Reserved, Program as 0 Figure B-25.
Programming Sheets Date: Application: Programmer: Sheet 2 of 3 Inverter Bit 8 0 = 0- to-1 transitions on TIO input increment the counter, or high pulse width measured, or high pulse output on TIO Timers 1 = 1-to-0 transitions on TIO input increment the counter, or low pulse width measured, or low pulse output on TIO Timer Reload Mode Bit 9 0 = Timer operates as a free running counter 1 = Timer is reloaded when selected condition occurs Timer Control Bits 4–7 (TC[3–0]) TIO Clock Mode GPIO Internal Time
Programming Sheets Date: Application: Programmer: Sheet 3 of 3 Timers 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Timer Reload Value Timer Load Register (TLR[0–2]) Reset = $000000 TLR0—X:$FFFF8E Write Only TLR1—X:$FFFF8A Write Only TLR2—X:$FFFF86 Write Only Figure B-27.
Programming Sheets Date: Application: Programmer: Sheet 1 of 4 GPIO Port B (HI08) DRx = 1 → HIx is Output DRx = 0 → HIx is Input 15 DR15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR14 DR13 DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 Host Data Direction Register (HDDR) Reset = $00 X:$FFFFC8 Write DRx holds value of corresponding HI08 GPIO pin. Function depends on HDDR.
Programming Sheets Date: Application: Programmer: Sheet 2 of 4 GPIO Port C (ESSI0) PCn = 1 → Port Pin configured as ESSI PCn = 0 → Port Pin configured as GPIO 23 6 5 4 3 2 1 0 *0 *0 PCC5 PCC4 PCC3 PCC2 PCC1 Port C Control Register (PCRC) Reset = $000000 PDCn = 1 → Port Pin is Output PDCn = 0 → Port Pin is Input 23 6 5 4 3 2 1 *0 *0 PRC5 PRC4 PRC3 PRC2 PRC1 Port C Direction Register (PRRC) Reset = $000000 PCC0 X:$FFFFBF Read/Write 0 PRC0 X:$FFFFBE Read/Write if port pin n is GPIO inp
Programming Sheets Date: Application: Programmer: Sheet 3 of 4 GPIO Port D (ESSI1) PCn = 1 → Port Pin configured as ESSI PCn = 0 → Port Pin configured as GPIO 23 6 5 4 3 2 1 0 *0 *0 PCD5 PCD4 PCD3 PCD2 PCD1 Port D Control Register (PCRD) Reset = $000000 PDCn = 1 → Port Pin is Output PDCn = 0 → Port Pin is Input 23 6 5 4 3 2 1 *0 *0 PRD5 PRD4 PRD3 PRD2 PRD1 Port D Direction Register (PRRD) Reset = $000000 PCD0 X:$FFFFAF Read/Write 0 PRD0 X:$FFFFAE Read/Write if port pin n is GPIO inp
Programming Sheets Date: Application: Programmer: Sheet 4 of 4 GPIO Port E (SCI) PCn = 1 → Port Pin configured as ESSI PCn = 0 → Port Pin configured as GPIO 23 6 5 4 3 2 1 0 *0 *0 *0 *0 *0 PCE2 PCE1 Port E Control Register (PCRE) Reset = $000000 PDCn = 1 → Port Pin is Output PDCn = 0 → Port Pin is Input 23 6 5 4 3 2 1 *0 *0 *0 *0 *0 PRE2 PRE1 Port E Direction Register (PRRE) Reset = $000000 PCE0 X:$FFFF9F Read/Write 0 PRE0 X:$FFFF9E Read/Write if port pin n is GPIO input, then PDn reflect
Programming Sheets B-44 DSP56301 User’s Manual
Index A adder modulo 1-7 offset 1-7 reverse-carry 1-7 Address Arithmetic Logic Unit (Address ALU) 1-7 Address Attribute 0–3 (AA[0–3]) 2-6 Address Attribute Priority Disable (APD) bit 4-13 Address Attribute Registers (AAR) 4-22, 4-27 Bus Access Type (BAT) 4-29 Bus Address Attribute Polarity (BAAP) 4-28 Bus Address to Compare (BAC) 4-27 Bus Number of Address Bits to Compare (BNC) 4-27 Bus Packing Enable (BPAC) 4-28 Bus Program Memory Enable (BPEN) 4-28 Bus X Data Memory Enable (BXEN) 4-28 Bus Y Data Memory En
Bus Row Out-of-Page Wait States (BRW) bit 4-26 Bus Software Triggered Reset (BSTR) bit 4-25 Bus Strobe (BS) 2-7 Bus X Data Memory Enable (BXEN) bit 4-28 Bus Y Data Memory Enable (BYEN) bit 4-28 C Cache Burst Mode Enable (BE) bit 4-14 Cache Enable (CE) bit 3-7, 4-7, 4-8 Cache Line Size (CLS[7–0]) bits 6-69 Cache Line Size Configuraiton Register (CCLS) 6-34 Carry (C) bit 4-11 Central Processing Unit (CPU) 1-1 Chip Operating Mode (MD–MA) bits 4-15 Class Code/Revision ID Configuration Register (CCCR/CRID) 6-67
Debug mode entering 2-29 external indication 2-29 Debug support 1-5 Detected Parity Error (DPE) bit 6-65 Device/Vendor ID Configuration Register (CDID/CVID) 6-64 DEVSEL Timing (DST[1–0]) bits 6-65 Direct Memory Access (DMA) ISA/EISA bus 6-15 ISA/EISA bus enable 6-54 Request Source bits 4-29 techniques 6-22 transfers 5-2, 5-4 triggered by timer 9-25 Direction (DIR) bit 9-30 Division Factor (DF) bits 4-21 DMA Address Mode (DAM) bit 4-34 DMA Channel Enable (DE) bit 4-29 DMA Channel Priority (DPR) bit 4-31 DMA
PCI Host Data Transfer Complete (HDTC) 6-39 PCI Master Abort (MAB) 6-40 PCI Master Address Request (MARQ) 6-40 PCI Master Receive Data Request (MRRQ) 6-41 PCI Master Transmit Data Request (MTRQ) 6-41 PCI Master Wait States (MWS) 6-41 PCI Target Abort (TAB) 6-40 PCI Target Disconnect (TDIS) 6-40 PCI Target Retry (TRTY) 6-39 PCI Time Out Termination (TO) 6-39 Remaining Data Count (RDC[5–0]) 6-38 Remaining Data Count Qualifier (RDCQ) 6-38 DSP PCI Transaction Address (High) (AR[31–16]) bits 6-32 DSP PCI Transac
network enhancements 7-2 Network mode 7-2, 7-8, 7-10, 7-21 Normal mode 7-2, 7-10, 7-20, 7-21 On-Demand mode 7-10, 7-15, 7-20, 7-21 operating mode 7-6, 7-10, 7-21 polling 7-7 Port Control Register (PCR) 7-6, 7-36 Port Control Register C (PCRC) 7-36 Port Control Register D (PCRD) 7-36 Port Data Register (PDR) 7-38 Port Data Register C (PDRC) 7-38 Port Data Register D (PDRD) 7-38 Port Direction Register (PRR) 7-37 Port Direction Register C (PRRC) 7-37 Port Direction Register D (PRRD) 7-37 prescale divider 7-16
G General-Purpose Input/Output (GPIO) 1-5, 1-6, 2-2, 5-4 data register 6-43 direction register 6-43 ESSI0 5-6 ESSI1 5-6 HI08 5-5 Port B 2-3, 5-5 Port C 5-6 Port D 5-6 Port E 5-6 SCI 5-6 timer 5-7 GPIO mode 6-13 ground (GND) 2-1, 2-4 H handshake flags 6-44 hardware stack 1-8 Header Type (HT[7–0]) bits 6-68 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS) Cache Line Size (CLS[7–0]) 6-69 Latency Timer (High) (LT[7–0]) 6-69 HI32 Active (HACT) bit 6-35 HI32 Control Register (HCTR) DMA Enable (D
DSP PCI Transaction Address (High) (AR[31–16]) 6-32 PCI Data Burst Length (BL[5–0]) 6-32 DSP PCI Port Control Register (DPCR) 6-26 Clear Transmitter (CLRT) 6-29 HSERR Force (SERF) 6-28 Insert Address Enable (IAE) 6-27 Master Access Counter Enable (MACE) 6-28 Master Address Interrupt Enable (MAIE) 6-30 Master Receive Interrupt Enable (MRIE) 6-30 Master Transfer Terminate (MTT) 6-28 Master Transmit Interrupt Enable (MTIE) 6-30 Master Wait State Disable (MWSD) 6-28 Parity Error Interrupt Enable (PEIE) 6-29 Rec
initializing configuration registers 6-4 input and output data transfers 6-4 interrupt 6-22 Interrupt Line-Interrupt Pin Configuration Register (CILP) 6-73 Interrupt Line (IL[7–0]) 6-73 Interrupt Pin (IP[7–0]) 6-73 MAX_LAT (ML[7–0] 6-73 MIN_GNT (MG[7–0]) 6-73 interrupt requests 6-4 low power state 6-13 Memory Space Base Address Configuration Register (CBMA) 6-70 Memory Base Address High/Low (PM[31–16]) 6-70 Memory Base Address Low (PM[15–4]) 6-71 Memory Space (MS[1–0]) 6-71 Memory Space Indicator (MSI) 6-71
I I/O space X data memory 3-4 Y data memory 3-5 Idle Line Flag (IDLE) bit 8-18 Idle Line Interrupt Enable (ILIE) bit 8-13 Idle Line Wakeup mode 8-3 illegal PCI events 6-46 initialization system 5-1 initializing the timer 9-3 input data alignment 6-3 Insert Address Enable (IAE) bit 6-27 instruction cache 1-5, 3-2 location 3-6 instruction cache controller 1-4 internal buses 1-10 internal memory configuration summary 3-6 internal program memory 3-1, 3-2 interrupt 1-8 configuring 4-15 source priorities 4-19 sou
Memory Base Address Low (PM[15–4]) 6-71 Memory Space (MS[1–0]) 6-71 Memory Space Indicator (MSI) 6-71 Pre-Fetch (PF) 6-71 Universal Bus Mode Base Address (GB[10–3]) 6-70 Memory Space Indicator (MSI) 6-71 Memory Switch (MS) bit 3-7 Memory Switch mode 3-2 X data Memory 3-3 Y data memory 3-4 Memory Switch Mode (MS) bit 4-14 MIN_GNT (MG[7–0]) bits 6-73 MODA–MODD pins 4-2, 8-8 mode control 2-9 Mode Register (MR) 4-7 Do Loop Flag (LF) 4-8 Double-Precision Multiply Mode (DM) 4-9 Interrupt Mask (I) 4-10 Scaling (S)
PCI-only registers DSP PCI Address Register (DPAR) 6-33 DSP PCI Master Control Register (DPMC) 6-30 DSP PCI Port Control Register (DPCR) 6-26 DSP PCI Status Register (DPSR) 6-38 Peripheral Component Interconnect (PCI) 1-5 configuration registers 6-44 illegal events 6-46 PCI Specification Revision 2.
Receive Slot Mask Registers (RSMA and RSMB) 7-14, 7-35 Receive with Exception Interrupt Enable (REIE) bit 8-12 Received Bit 8 (R8) bit 8-17 Received Master Abort (RMA) bit 6-65 Received Target Abort (RTA) 6-65 Receiver Enable (RE) bit 8-14 Receiver Overrun Error Flag (ROE) 7-28 Receiver Wakeup Enable (RWU) bit 8-15 Related Documents and Web Sites 1-14 Remaining Data Count (RDC[5–0]) bits 6-38 Remaining Data Count Qualifier (RDCQ) bit 6-38 RESET 2-9 reset STOP 6-12 reset state 4-2, 4-5 HI32 6-12 reverse-carr
Asynchronous 8-1 Synchronous 8-1 programming model 8-9 data registers 8-22 Receive Data (RXD) 8-4 recover synchronization 8-2 reset 8-5 RXD, TXD, SCLK 8-3 SCI Clock Control Register (SCCR) 8-7, 8-8, 8-9, 8-19 bit definitions 8-19 Clock Divider (CD) 8-20 Clock Out Divider (COD) 8-19 Clock Prescaler (SCP) 8-19 programming sheet B-36 Receive Clock Mode Source (RCM) 8-19 Transmit Clock Source (TCM) 8-19 SCI Control Register (SCR) 8-7, 8-8, 8-9, 8-12 bit defintions 8-12 Idle Line Interrupt Enable (ILIE) 8-13 pro
Zero (Z) 4-11 Extended Mode Register (EMR) 4-7 Arithmetic Saturation Mode (SM) 4-7 Cache Enable (CE) 4-8 Core Priority (CP) 4-7 DO FOREVER (FV) Flag 4-8 Instruction Cache Enable (CE) 4-7 Rounding Mode (RM) 4-7 Sixteen-bit Arithmetic Mode (SA) 4-8 Mode Register (MR) 4-7 Do Loop Flag (LF) 4-8 Double-Precision Multiply Mode (DM) 4-9 Interrupt Mask (I) 4-10 Scaling (S) Mode 4-10 Sixteen-bit Compatibility (SC) Mode 4-9 programming sheet B-13 Status/Command Configuration Register (CSTR/CCMR) 6-64 Data Parity Repo
Timer Overflow Interrupt Enable (TOIE) 9-32 Timer Reload Mode (TRM) 9-30 Timer Count Register (TCR) 9-34 Timer Load Registers (TLR) 9-33 Timer Prescaler Count Register (TPCR) 9-28 Prescaler Counter Value (PC) 9-28 Timer Prescaler Load Register (TPLR) 9-27 bit definitions 9-27 Prescaler Preload Value (PL) 9-27 Prescaler Source (PS) 9-27 Timer Compare Flag (TCF) bit 9-29 Timer Compare Interrupt Enable (TCIE) bit 9-32 Timer Compare Register (TCPR) 9-4, 9-34 Timer Control (TC) bits 9-31 Timer Control/Status Reg
X I/O memory space 3-4, 5-2 X Memory Address Bus (XAB) 1-10 X Memory Data Bus (XDB) 1-10 X Memory Expansion Bus 1-10 X-data memory 1-5 XTAL Disable (XTLD) bit 4-21 Y Y data memory 3-4 Y I/O space 3-5 Y Memory Address Bus (YAB) 1-10 Y Memory Data Bus (YDB) 1-10 Y Memory Expansion Bus 1-10 Y-data memory 1-5 Z Zero (Z) bit 4-11 Index-16 DSP56301 User’s Manual
