MCPN750A CompactPCI Single Board Computer Installation and Use MCPN750A/IH5 September 2001 Edition
© Copyright 2001 Motorola, Inc. All Rights Reserved. Printed in the United States of America. Motorola and the stylized M logo are registered trademarks of Motorola, Inc. PowerPC is a registered trademark of International Business Machines and is used by Motorola Inc. under license from IBM Corporation. CompactPCI is a registered trademark of PCI Industrial Computer Manufacturers Group.
Safety Summary The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware.
Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution ! Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection. Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry.
CE Notice (European Community) ! Warning This is a Class A product. In a domestic environment, this product may cause radio interference, in which case the user may be required to take adequate measures. Motorola Computer Group products with the CE marking comply with the EMC Directive (89/336/EEC).
Limited and Restricted Rights Legend If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252.
Contents About This Manual Summary of Changes ...............................................................................................xviii Overview of Contents ..............................................................................................xviii Comments and Suggestions .....................................................................................xviii Conventions Used in This Manual.............................................................................
CHAPTER 2 Startup and Operation Introduction ............................................................................................................... 2-1 Applying Power ......................................................................................................... 2-1 Memory Maps............................................................................................................ 2-3 Processor Memory Map ...............................................................................
CHAPTER 4 CNFG and ENV Commands Overview....................................................................................................................4-1 CNFG - Configure Board Information Block ............................................................4-2 ENV - Set Environment .............................................................................................4-3 Configuring the PPCBug Parameters .................................................................
ISA DMA Channels .................................................................................. 6-10 Interval Timers .......................................................................................... 6-11 Real-Time Clock/NVRAM/Watchdog Timer Function ................................... 6-11 Replacing Lithium Batteries ..................................................................... 6-12 Hot Swap Control Circuitry .............................................................................
TMCPN710 Transition Module COM1 Connector (J6) ...................................7-19 TMCPN710 Transition Module COM2 Connector (J8) ...................................7-20 TMCPN710 Transition Module COM3 Header (J11) ......................................7-20 TMCPN710 Transition Module COM4 Header (J14) ......................................7-21 TMCPN710 Transition Module 10BaseT/100BaseTx Connector (J13) ..........7-22 TMCPN710 Transition Module USB Connectors (J10, J12) ...........................
xii
List of Figures Figure 1-1. MCPN750A Base Board Block Diagram................................................1-2 Figure 1-2. MCPN750A Switches, Headers, Connectors, Fuses, LEDs ...................1-9 Figure 1-3. TMCPN710 Connector and Header Locations .....................................1-12 Figure 1-4. MCPN750A/TMCPN710 Serial Ports 1 and 2 .....................................1-14 Figure 1-5. TMCPN710 Serial Ports 3 and 4...........................................................1-15 Figure 1-6.
xiv
List of Tables Table 1-1. Startup Overview ......................................................................................1-3 Table 1-2. Installing a PIM on the TM-PIMC-0001 Transition Module .................1-27 Table 2-1. Processor Default View of the Memory Map ...........................................2-3 Table 2-2. Classes of Reset and Effectiveness .........................................................2-10 Table 3-1. Debugger Commands .......................................................
Table 7-25. PMC I/O Modules 1 and 2 (PIM1 and PIM2) PMC I/O Connector Pin Assignments..................................................................... 7-36 Table A-1. MCPN750 Specifications ...................................................................... A-1 Table B-1. Motorola Computer Group Documents ................................................. B-1 Table B-2. Manufacturers’ Documents ................................................................... B-2 Table B-3. Related Specifications ..
About This Manual This manual, MCPN750A CompactPCI Single Board Computer Installation and Use (MCPN750A/IH5) provides general information, hardware preparation and installation instructions, operating instructions, firmware information, functional descriptions, and pin assignments for the MCPN750A family of Single Board Computers. In addition, sufficient information is also provided for the two transition modules manufactured by Motorola for use with the MCPN750A (TMCPN710 and TM-PIMC0001).
Summary of Changes The following is a list of changes made since the last release of this manual. Date Changes Replaces 09/01 Updated table of model numbers preceeding this section. Reinserted information left out of IH4 version of manual, which included information on MCPN750A, the TMCPN710 and the TM-PIMC-0001, instead of the earlier MCPN750. Also, included J8 jumper settings for StandAlone operation. Previously listed model numbers. 07/00 68-pin .08 Series Subminature D PMC I/O Connector.
Chapter 4, CNFG and ENV Commands, provides an explanation of two of the more important PPCBug configuration commands: CNFG and ENV. Includes information on how to configure the VMEbus and PCI bus environments using the ENV command. Chapter 5, Remote Start Via the PCI Bus, provides a description of the remote start capability that is available via the PCI bus using PPCBug commands. Chapter 6, Functional Description, provides a description of the major components and functionality of the MCPN750A.
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1Hardware Preparation and Installation 1 Introduction This chapter provides startup and safety instructions related to this product, hardware preparation instructions - including default jumper settings, system considerations, and installation instructions for the baseboard, as well as the PMCs and transition modules associated with this board.
Hardware Preparation and Installation DRAM (Bank 1) 16M/64M/128M Arbitration Control L2 Cache 1M Processor MPC750 66MHz PPC603 Processor Bus Debug Connector DRAM (Bank 2) 16M/64M/128M Flash (soldered) 4M Memory Controller Falcon 3 Chipset Flash (socketed) 1M SROM AT24C04 PCI Bridge & MPIC Raven 5 ASIC System Registers Interrupt Serializer Core Power 32/64-bit PMC Slot 1 Clock Generator Reset Control Hot Swap Control 33MHz 32/64-bit PCI Local Bus RS232 IOMX User I/O J3 & J5 SERIAL 1 SER
Getting Started Getting Started This section provides an overview of the steps necessary to install and power up the MCPN750A, any additional equipment requirements, and a brief section on unpacking and ESD precautions.
1 Hardware Preparation and Installation Table 1-1. Startup Overview (Continued) Task Section or Manual Reference Page Note that the debugger initializes the MCPN750A Using PPCBug 3-5 You may also wish to obtain the PPCBug Firmware Package User’s Manual, listed in Appendix B, Related Documentation. B-1 Initialize the system clock. Using the Debugger, Debugger Commands, the SET command 3-6 Examine and/or change environmental parameters.
Getting Started Unpacking Instructions Note If the shipping carton is damaged upon receipt, request that the carrier’s agent be present during the unpacking and inspection of the equipment. Unpack the equipment from the shipping carton. Refer to the packing list and verify that all items are present. Save the packing material for storing and reshipping of equipment. Avoid touching areas of integrated circuitry; static discharge can damage circuits.
1 Hardware Preparation and Installation Preparation This section discusses certain hardware and software tasks that may need to be performed prior to installing the board in a CompactPCI chassis. Hardware Configuration To produce the desired configuration and ensure proper operation of the MCPN750A, you may need to carry out certain hardware modifications before installing the module.
Preparation The MCPN750A is factory tested and shipped with the configurations described in the following sections. The MCPN750A’s required and factory-installed debug monitor, PPCBug, operates with those factory settings. Flash Bank Selection (J7) The MCPN750A baseboard has provision for 1MB of 16-bit Flash memory and 4MB of linear Flash memory. The Flash memory is organized in two banks, Bank A is 64 bits wide and Bank B is 16 bits wide. Bank B contains the onboard debugger, PPCBug.
1 Hardware Preparation and Installation Stand-Alone Operating Mode (J8) The MCPN750A has a stand-alone operating mode that allows the MCPN750A to function without the clock from the system slot controller board. Installing a jumper across pins 1 and 2 of J8 enables the stand-alone mode. The J8 jumper must be removed for normal operation.
3 1 3 1 1 2 1 1 J9 2 J7 J8 J6 15 1 J5 U1 U2 2 1 J24 64 63 2 1 2 1 J11 J12 64 63 64 63 2 1 2 1 J13 J14 64 63 64 63 J3 64 63 64 63 J4 J22 J23 U12 U13 U14 U15 U16 2 1 U6 U7 U8 U9 64 63 U5 XU2 U20 U23 J21 XU1 PCI MEZZANINE CARD 1 J2 L2 U35 J18 10/100 BASE T DS1 DS2 U31 S1 J1 J19 Q3 COM 1 DS3 Q4 2703 0002 1-9 http://www.motorola.com/computer/literature 2 16 2 PCI MEZZANINE CARD 2 BFL CPU ABT/RST Figure 1-2.
1 Hardware Preparation and Installation System Considerations The MCPN750A is designed to operate as a CompactPCI non-system slot board. Consequently, the MCPN750A must be installed in the subrack system slot marked with the circle symbol. The MCPN750A can operate properly, with or without a system slot controller board. In the standard operating mode (with a system slot board), the system slot board is used to provide clock and arbitration signals to the MCPN750A.
Preparation TMCPN710 Transition Module Preparation The TMCPN710 transition module (Figure 1-3) is used in conjunction with all models of the MCPN750A baseboard: The features of the TMCPN710 include: ❏ Two EIA-232-D asynchronous serial ports (identified as COM1 and on the transition module panel) COM2 ❏ Two USB Series A connectors for USB interface ❏ One 10/100BaseT connector for ethernet connections (requires MCPN750A Transition module/ethernet option) ❏ Two 68-pin .
7 J13 1 2 7 1 J8 7 1 2 J6 J7 (Slave) J16 PMC2 I/O J2 J3 3 COM 1 8 1 2 J11 COM 2 J4 8 1 J10 USB 0 4 1 J12 USB 1 4 J14 J5 10/100 BASE T 8 2286 9806 Hardware Preparation and Installation J1 J15 PMC1 I/O (Master) 1 Figure 1-3.
Preparation Serial Ports 1 and 2 On the TMCPN710, the asynchronous serial ports (Serial Ports 1 and 2) are configured permanently as data circuit-terminating (Figure 1-4) equipment (DTE). The COM1 port is also routed to a RJ-45 connector on the front panel of the processor board. A terminal for COM1 may be connected to either the processor board or the transition module, but not both.
1 Hardware Preparation and Installation MCPN750A RJ45 1 8 7 COM1 (front panel) 2 5 TMCPN710 4 3 J7 6 COM1 (rear panel) 16C550 SOUT 4 SIN 5 RTS 2 CTS 7 DTR 8 DCD 1 J3 DSR 3 6 RI IO MUX IO MUX 16C550 RI DSR COM2 (rear panel) DCD 1 DTR 8 CTS 7 RTS 2 SIN 5 SOUT 4 3 6 2362 9808 Figure 1-4.
Preparation COM3 and COM4 Asynchronous Serial Ports The signals for COM3 and COM4 serial ports are routed to headers on the TMCPN710 Transition Module. These headers are intended for debug purposes only. Figure 1-5 depicts this configuration. TMCPN710 MCPN750A J11 16C550 SOUT 3 SIN 5 RTS 7 CTS 9 DTR 14 DCD 15 J3 DSR Com3 Header 11 18 RI IO MUX IO MUX 16C550 13 J14 RI 18 DSR 11 DCD 15 DTR 14 CTS 9 RTS 7 SIN 5 Com4 Header 3 SOUT 13 2363 9808 Figure 1-5.
1 Hardware Preparation and Installation TM-PIMC-0001 Transition Module Preparation The TM-PIMC-0001 transition module (Figure 1-6) is used in conjunction with all models of the MCPN750A baseboard. The features of this transition module include: 1-16 ❏ Connections for two single wide, or one double wide PIM card. ❏ Two asynchronous serial ports using RJ-45 connectors labeled as COM1 and COM2. ❏ Two asynchronous serial ports using 10-pin headers labeled as COM3 and COM4.
http://www.motorola.com/computer/literature 1 2 7 8 COM 1 J9 J2 1 3 J8 7 8 J11 COM 2 1 2 1 3 J1 1 2 J7 J12 7 8 1 9 1 64 63 10/100 BASE T 2 2 J13 9 J14 PMC I/O MODULE 1 2 64 1 63 J3 J10 2 64 1 63 J4 J24 PMC I/O MODULE 2 2 64 1 63 J20 J5 2 1 8 1 J16 2694 0001 Preparation Figure 1-6.
1 Hardware Preparation and Installation COM1 and COM2 Asynchronous Serial Ports On the TM-PIMC-0001, the asynchronous serial ports (COM1 and COM2) are configured permanently as data circuit-terminating (Figure 1-7) equipment (DTE). The COM1 port is also routed to an RJ45 connector on the front panel of the processor board. A terminal for COM1 may be connected to either the processor board or the transition module, but not both.
Preparation TM-PIMC-0001 MCPN750 RJ45 1 8 7 COM1 (front panel) PIM 1 2 5 4 3 J11 6 COM1 (rear panel) 16C550 4 SOUT 5 SIN IO MUX RTS 2 CTS 7 DTR 8 1 DCD J3 DSR 3 6 RI IO MUX IO MUX 16C550 RI DSR COM2 (rear panel) DCD 1 8 DTR IO MUX CTS 7 RTS 2 SIN 5 SOUT 4 3 J2 6 PIM 2 2362 0001 Figure 1-7. MCPN750A/TM-PIMC-0001 Serial Ports 1 and 2 http://www.motorola.
1 Hardware Preparation and Installation COM3 and COM4 Asynchronous Serial Ports The signals for COM3 and COM4 serial ports are routed to 10-pin headers on the TM-PIMC-0001 Transition Module (J12 and J13). These headers function as I/O connectors for the MCPN750A and are permanently configured as DTE. Figure 1-8 depicts this configuration.
Hardware Installation Hardware Installation The following sections discuss the placement of PMC mezzanine cards on the MCPN750A baseboard and the installation of the complete MCPN750A assembly into a CompactPCI chassis. Before installing the MCPN750A, ensure that all header jumpers are configured as desired. In most cases, PMC modules ordered with the baseboard are installed on the MCPN750A at the factory and the order is shipped as a single unit.
1 Hardware Preparation and Installation 3. Remove chassis or system cover(s) as necessary for access to the CompactPCI. 2288 9806 Figure 1-9. PMC Module Placement on MCPN750A ! Caution ! Warning Inserting or removing modules in a non-hot swap chassis with power applied may result in damage to module components. The MCPN750A is a hot swappable board and may be inserted in a hot swap chassis, such as a CPX2000 or a CPX8000 series chassis with power applied.
Hardware Installation ! Caution Avoid touching areas of integrated circuitry; static discharge can damage these circuits. 5. Remove the PMC filler from the front panel of the MCPN750A. 6. Slide the edge connector of the PMC module into the front panel opening from behind and place the PMC module on top of the baseboard. The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors (J11/12/13/14) on the MCPN750A. 7.
1 Hardware Preparation and Installation Installing the MCPN750A Baseboard With mezzanine board(s) installed (if applicable) and headers properly configured, proceed as follows to install the MCPN750A in the CompactPCI chassis: 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure. 2. In a non-hot swap system, perform an operating system shutdown.
Hardware Installation ! Caution Avoid touching areas of integrated circuitry; static discharge can damage these circuits 6. Secure the MCPN750A in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions. 7. Replace the chassis or system cover(s), making sure no cables are pinched. Cable the peripherals to the panel connectors, reconnect the system to the AC or DC power source, and turn the equipment power on. http://www.motorola.
1 Hardware Preparation and Installation Installing a TMCPN710 or TM-PIMC-0001 Transition Module The TMCPN710 or TM-PIMC-0001 Transition Module may be required to complete the configuration of your particular MCPN750A system. If so, perform the following install steps to install this board. For more detailed information on the TMCPN710 or TM-PIMC-0001 Transition Module refer to the corresponding users guide, i.e.
Hardware Installation 2695 0001 Figure 1-10. Installing a PIM on the TM-PIMC-0001 Transition Module ! Caution Inserting or removing modules in a non-hot swap chassis with the power applied may result in damage to the module components. The TM-PIMC0001 is not a hot swap board, but it may be installed in a hot swap chassis with power applied, if the corresponding MCPN750A is removed before the TM-PIMC-0001 board is installed. http://www.motorola.
1 Hardware Preparation and Installation ! Warning Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. 4. Carefully remove the TM-PIMC-0001 from its CompactPCI card slot and lay it flat on a stable surface. 5. Remove the PIM filler from the front panel of the TM-PIMC-0001 transition module. 6.
Hardware Installation ! Warning ! Caution Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. Avoid touching areas of integrated circuitry; static discharge can damage these circuits. 3. With the TMCPN710 or TM-PIMC-0001 in the correct vertical position that matches the pin positioning of the corresponding MCPN750A board carefully slide the transition module into the appropriate slot and seat tightly into the backplane.
1 Hardware Preparation and Installation P5 P5 P4 P4 P3 P3 MCPN750A P2 TMCPN710 or TM-PIMC-0001 P1 Figure 1-11.
MCPN750A Module Power Requirements MCPN750A Module Power Requirements The MCPN750A board draws +5V, +3.3V and VIO power from the J1 connector. The +12V and -12V voltages are monitored by the MCPN750A hot swap controller and provided for use by the PMCs and transition modules. The MCPN750A contains an electronic circuit breaker that limits the total +5V, +3.3V, +12V and -12V current drawn by the MCPN750A.
1 Hardware Preparation and Installation 1-32 Computer Group Literature Center Web Site
2Startup and Operation 2 Introduction This chapter supplies information for use of the MCPN750A family of Single Board Computers in a system configuration. Here you will find the power-up procedure and descriptions of the switches and LEDs, memory maps, and software initialization. Applying Power After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is complete, you can power up the system.
Startup and Operation 2 STARTUP SYSTEM INITIALIZATION CONSOLE DETECTION RUN SELFTESTS (IF ENABLED) AUTOBOOT (IF ENABLED) OPERATING SYSTEM 11734.00 9702 Figure 2-1. PPCBug System Startup The MCPN750A front panel has one ABORT/RESET switch and three LED (light-emitting diode) status indicators (BFL, CPU, and HOT SWAP STATUS). For more information on front panel operation refer to Chapter 6, Functional Description.
Memory Maps Memory Maps 2 There are three points of view for memory maps: ❏ The mapping of all resources as viewed by the processor (MPU bus memory map) ❏ The mapping of onboard resources as viewed by PCI local bus masters (PCI bus memory map) ❏ The mapping of onboard resources as viewed by the CompactPCI bus. The following sections give a general description of the MCPN750A memory organization from the above three points of view.
Startup and Operation Table 2-1. Processor Default View of the Memory Map (Continued) 2 Processor Address Start Size End Definition FEF90000 FEFEFFFF 384KB Not Mapped FEFF0000 FEFFFFFF 64KB Raven Registers FF000000 FFEFFFFF 15MB Not Mapped FFF00000 FFFFFFFF 1MB ROM/Flash Bank A or Bank B Notes 2 Notes 1. Default map for PCI/ISA I/O space.
Memory Maps For detailed PCI memory maps, including suggested PREP-compatible memory maps, refer to the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG). CompactPCI Memory Map The MCPN750A uses the 21554 non-transparent PCI-to-PCI bridge to interface between the local PCI bus and the CompactPCI bus. The 21554 is different from traditional PCI-to-PCI bridges in that it uses address translation instead of a flat address map between primary and secondary PCI buses.
Startup and Operation 2 L2 Cache The MCPN750A SBC uses a backside L2 cache structure via the MPC750 processor chip. The MPC750 L2 cache is implemented with an onchip 2way set-associative tag memory and external direct-mapped synchronous SRAMs for data storage. The external SRAMs are accessed through a dedicated 72-bit wide (64 bits of data and 8 bits of parity) L2 cache port. The MPC750 will support 256KB, 512KB or 1MB of L2 cache SRAMs.
Memory Maps supported. The Raven supports PowerPC processor external bus frequencies up to 66 MHz and PCI frequencies up to 33 MHz. The Raven is connected to the processor data parity signals to provide processor data bus parity generation and checking. There are four programmable map decoders for each direction to provide flexible address mappings between the PPC/DRAM and the PCI Local Bus.
Startup and Operation 2 PCI Arbitration The MCPN750A has six potential local PCI bus masters: ❏ the Raven ASIC, ❏ the PBC device (VT82C586B), ❏ the Ethernet device (21143), ❏ the PCI-to-PCI bridge device (21554), ❏ and each of the two PMCs. The local PCI arbiter is implemented in an onboard PLD. This arbiter implements a rotating priority scheme with equal priorities. Since the PBC device does not support bus parking, the arbiter will park on the Raven when the bus is idle.
Memory Maps ❏ The Processor 0 (processor self-interrupts) ❏ Transfer Error Interrupt (from the Raven ASIC) ❏ The Falcon chip set (memory error interrupts) ❏ The PCI bus (interrupts from PCI devices) ❏ The CPCI bus (interrupts from CPCI devices) ❏ Power monitor interrupts ❏ Watchdog timer interrupt ❏ The ISA bus (interrupts from ISA devices) 2 The ISA interrupts are handled as a single 8259 interrupt from the VT82C586B PBC device.
Startup and Operation 3. CompactPCI Push Button Reset (RST#) from the CompactPCI backplane. 2 4. Watchdog timer Reset function controlled by the SGS-Thomson MK48T559 Watchdog Timer or the Raven Watchdog Timer. 5. Software Hard Reset (PBC Port 92 Register) 6. 21554 PCI-to-PCI bridge Secondary Reset Bit 7. 21554 PCI-to-PCI bridge Chip Reset Bit. The following table shows which devices are affected by the various types of resets.
Memory Maps ** If the Chip Reset Bit is set to a 1, the bit will clear itself after the chip reset is complete. Power-On Reset The MCPN750A SBC generates a hard reset at power-on. During power up, reset is maintained for 140 to 560 milliseconds after the voltages have reached the minimum threshold. Undervoltage Reset The MCPN750A SBC generates a hard reset when the Hot Swap power control chip (LTC1643) detects a supply voltage +5V, +3.3V, +12V or 12V fall below minimum thresholds of +4.75V, +3.135V, +10.
Startup and Operation 2 Software Resets The software is able to generate a 200 millisecond hard reset by programming the PBC Port92 register or a soft reset by writing to the Processor Init Register of the Raven MPIC. Note that the Port 92 reset will reset every device on the board except the 21554 bridge chip. Refer to the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG) for register details.
Memory Maps Role of the Raven ASIC 2 Because the PCI bus is little-endian, the Raven performs byte swapping in both directions (from PCI to memory and from the processor to PCI) to maintain address invariance while programmed to operate in big-endian mode with the processor and the memory subsystem. In little-endian mode, the Raven reverse-rearranges the address for PCIbound accesses and rearranges the address for memory-bound accesses (from PCI). In this case, no byte swapping is done.
Startup and Operation 2 2-14 Computer Group Literature Center Web Site
3PPCBug 3 PPCBug Overview The PPCBug firmware is the layer of software just above the hardware. The firmware provides the proper initialization for the devices on the MCPN750A motherboard upon power-up or reset. This chapter describes the basics of PPCBug and its architecture. It also describes the monitor (interactive command portion of the firmware) in detail, and gives information on actually using the PPCBug debugger and the special commands.
PPCBug ❏ Breakpoint and tracing capabilities ❏ A powerful assembler and disassembler useful for patching programs ❏ A self-test at power-up feature which verifies the integrity of the system 3 PPCBug consists of three parts: ❏ A command-driven, user-interactive software debugger, described in the PPCBug Firmware Package User’s Manual. It is hereafter referred to as “the debugger” or “PPCBug”.
MPU, Hardware, and Firmware Initialization Memory Requirements PPCBug requires a maximum of 768KB of read/write memory (i.e., DRAM). The debugger allocates this space from the top of memory. For example, a system containing 64MB ($04000000) of read/write memory will place the PPCBug memory page at locations $03F80000 to $03FFFFFF. PPCBug Implementation PPCBug is written largely in the C programming language, providing benefits of portability and maintainability.
PPCBug 7. Calculate the external bus clock speed of the MPU. 8. Delays for 750 milliseconds. 3 9. Determines the CPU board type. 10. Sizes the local read/write memory (i.e., DRAM). 11. Initializes the read/write memory controller. 12. Sets base address of memory to $00000000. 13. Retrieves the speed of read/write memory. 14. Initializes the read/write memory controller with the speed of read/write memory. 15. Retrieves the speed of read only memory (i.e., Flash) from NVRAM. 16.
Using PPCBug 26. Verifies the configuration data that is resident in NVRAM, and displays a warning message if the verification failed. 27. Calculates and displays the MPU clock speed, verifies that the MPU clock speed matches the configuration data, and displays a warning message if the verification fails. 28. Displays the BUS clock speed, verifies that the BUS clock speed matches the configuration data, and displays a warning message if the verification fails. 29.
PPCBug What you key in is stored in an internal buffer. Execution begins only after you press the Return or Enter key. This allows you to correct entry errors, if necessary, with the control characters described in the PPCBug Firmware Package User’s Manual, Chapter 2. 3 After the debugger executes the command, the prompt reappears. However, if the command causes execution of user target code (for example GO) then control may or may not return to the debugger, depending on what the user program does.
Using PPCBug followed by the particular command mnemonic, as listed below, followed by a carriage return. Keep in mind that help is now available on both the BUG and DIAG side. In addition, issuing help on a DIAG test category will give more information about the tests in that category. The later is accomplished by entering HE, followed by a space, followed by the test category description (e.g., UART), followed by a carriage return. 3 Table 3-1.
PPCBug Table 3-1.
Using PPCBug Table 3-1.
PPCBug Table 3-1.
Using PPCBug If you are in the debugger directory, the debugger prompt PPC1-Bug> displays, and all of the debugger commands are available. Diagnostics commands cannot be entered at the PPC1-Bug> prompt. If you are in the diagnostic directory, the diagnostic prompt PPC1-Diag> displays, and all of the debugger and diagnostic commands are available. Note that not all tests are valid for the MCPN750A. Using the HE command, you can list the diagnostic routines available in each test group.
PPCBug Notes You may enter command names in either uppercase or lowercase. Some diagnostics depend on restart defaults that are set up only in a particular restart mode. Refer to the documentation on a particular diagnostic for the correct mode. 3 Test Sets marked with an asterisk (*) are not available on the MCPN750A, unless SCSI or Video PMCs are installed.
4CNFG and ENV Commands 4 Overview You can use the factory-installed debug monitor, PPCBug, to modify certain parameters contained in the PowerPC board’s Non-Volatile RAM (NVRAM), also known as Battery Backed-up RAM (BBRAM). ❏ The Board Information Block in NVRAM contains various elements concerning operating parameters of the hardware. Use the PPCBug command CNFG to change those parameters. ❏ Use the PPCBug command ENV to change configured PPCBug parameters in NVRAM.
CNFG and ENV Commands CNFG - Configure Board Information Block Use this command to display and configure the Board Information Block, which is stored in the NVRAM. The Board Information Block lists details of your specific board, such as the Board Serial Number, the Board Identifier, the Bus Clock Speed, and other operational or ID characteristics.
ENV - Set Environment ENV - Set Environment Use the ENV command to view and/or configure interactively all PPCBug operational parameters that are kept in Non-Volatile RAM (NVRAM). Refer to the PPCBug Firmware Package User’s Manual (PPCBUGA1/UM) for a description of the use of ENV. 4 Listed and described below are the parameters that you can configure using ENV. The default values shown were those in effect when this publication went to print.
CNFG and ENV Commands Auto-Initialize of NVRAM Header Enable [Y/N] = Y? 4 Y NVRAM (PReP partition) header space will be initialized automatically during board initialization, but only if the PReP partition fails a sanity check. (Default) N NVRAM header space will not be initialized automatically during board initialization. Network PReP-Boot Mode Enable [Y/N] = N? Y Enable PReP-style network booting (same boot image from a network interface as from a mass storage device).
ENV - Set Environment NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N? Note Y Give boot priority to devices defined in the fw-bootpath global environment variable (GEV). N Do not give boot priority to devices listed in the fwboot-path GEV. (Default) 4 When enabled, the GEV (Global Environment Variable) boot takes priority over all other boots, including Autoboot and Network Boot. NVRAM Bootlist (GEV.
CNFG and ENV Commands Auto Boot Scan Enable [Y/N] = Y? Y If Autoboot is enabled, the Autoboot process attempts to boot from devices specified in the scan list (e.g., FDISK/CDROM/TAPE/HDISK). (Default) N If Autoboot is enabled, the Autoboot process uses the Controller LUN and Device LUN to boot. 4 Auto Boot Scan Device Type List = FDISK/CDROM/TAPE/HDISK? This is the listing of boot devices displayed if the Autoboot Scan option is enabled.
ENV - Set Environment You may specify a string (filename) which is passed on to the code being booted. The maximum length of this string is 16 characters. (Default = null string) ROM Boot Enable [Y/N] = N? Y The ROMboot function is enabled. N The ROMboot function is disabled. (Default) 4 ROM Boot at power-up only [Y/N] = Y? Y ROMboot is attempted at power-up only. (Default) N ROMboot is attempted at any reset.
CNFG and ENV Commands Network Auto Boot Controller LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of network controller modules currently supported by PPCBug. (Default = $00) Network Auto Boot Device LUN = 00? 4 Refer to the PPCBug Firmware Package User’s Manual for a listing of network controller modules currently supported by PPCBug. (Default = $00) Network Auto Boot Abort Delay = 5? The time in seconds that the NETboot sequence will delay before starting the boot.
ENV - Set Environment Memory Size Enable [Y/N] = Y? Y Memory will be sized for Self Test diagnostics. (Default) N Memory will not be sized for Self Test diagnostics. 4 Memory Size Starting Address = 00000000? The default Starting Address is $00000000. Memory Size Ending Address = 02000000? The default Ending Address is the calculated size of local memory. If the memory start is changed from $00000000, this value will also need to be adjusted.
CNFG and ENV Commands allowable ROMNAL setting is $0; the highest allowable is $F. The value to enter depends on processor speed; refer to your Processor/Memory Mezzanine Module User’s Manual for appropriate values. The default value varies according to the system’s bus clock speed. 4 Note ROM Next Access Length is not applicable to the MCPN750. The configured value is ignored by PPCBug. DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O? Note O DRAM parity is enabled upon detection.
ENV - Set Environment The Serial Startup Codes can be displayed at key points in the initialization of the hardware devices. Should the debugger fail to come up to a prompt, the last code displayed will indicate how far the initialization sequence had progressed before stalling. The codes are enabled by an ENV parameter. Serial Startup Code LF Enable [Y/N]= N? A line feed can be inserted after each code is displayed to prevent it from being overwritten by the next code.
CNFG and ENV Commands Firmware Command Buffer [‘NULL’ terminates entry]? The Firmware Command Buffer contents contain the BUG commands which are executed upon firmware startup. BUG commands you will place into the command buffer should be typed just as you enter the commands from the command line. The string ‘NULL’ on a new line terminates the command line entries. All BUG commands except for the following may be used within the command buffer: DU, ECHO, LO, TA, VE.
5Remote Start Via the PCI Bus 5 Introduction This chapter describes the remote interface provided by the firmware to the host CPU via the cPCI bus. This interface facilitates the host obtaining information about the board, downloading code and/or data, and execution of the downloaded program. Note Applications may also be downloaded to the MCPN750A via one of the PCI bus windows provided by the PCI-to-PCI bridge.
Remote Start Via the PCI Bus ❏ A command data and result field. This field provides the data, if any, needed by the command and provides the response from PPCBug upon command completion. The meaning of the bits in this field are specific to each command opcode. Additionally, certain commands require more information than can be contained within the data and result fields of the scratch pad register. To provide this information, the interface provides four ‘virtual’ registers.
Introduction Command/response Register Description The 2155x SCRATCH7 register is used as the command/response register. In this register description and the following command descriptions, references to the upper half of the register refer to bits 0 through 15, and references to the lower half of the register refer to bits 16 through 31.
Remote Start Via the PCI Bus Bits 9 to 15 Note 5 Bits 16 to 31 5-4 7 bit command option field. Each command specifies the particular meaning of each of the command option bits. Option bits which are unused are considered reserved and should be written to 0 to ensure compatibility with future implementations of this interface. For most commands, bit 9 is used to specify verbose/nonverbose mode target command processing.
Introduction Opcode 0x01: Write/Read Virtual Register This command allows the host to access the contents of any of the four virtual registers. The specific operation and register to be accessed are determined by the command options field. Write data is contained in the Command data field. Read data is returned in the result field.
Remote Start Via the PCI Bus Opcode 0x03: Write/Read Memory This command allows the host to Read or Write individual address locations on the local address bus. Data sizes of 8, 16 and 32 bits are supported. The specific operation and size are determined by the command options field. Note: Verbose mode target command processing is not available with this command; command register bit 9 is ignored. ❏ The data to be written is specified in the data field.
Introduction ❏ VR0 specifies the beginning address of the area to checksum. VR1 specifies the number of bytes to checksum. Neither register is affected by the operation. Opcode 0x05: Memory Size Query This command allows the host to determine the size of local memory present and available on the card. The result is stored in VR1 and may then be read using the read virtual register command.
Remote Start Via the PCI Bus ❏ The state of CPU registers R0 through R2, and R4 through R31 are indeterminate when control is passed to the address. ❏ Note: this command does not return. The OWN flag bit remains clear. Command/Response Channel Error Codes These are the 16 bit values that the target board returns in the Data/Result field of the Command/Response register when the target board detects an error in the processing of a host command.
Introduction Demonstration of the Host Interface The following example demonstrates the use of PPCBug’s Remote Start capability in a CPCI system. In this example, a simple program is loaded into the local memory of a (non-system) target board, the MCPN750A. The CPCI system host board (an MCP750) then uses the PCI Remote Start interface to initiate execution of the program by the target board. A simple program is loaded into the local memory of the target board. This program performs the following steps: 1.
Remote Start Via the PCI Bus 00040100 0B? . PPC1-Bug> Enter the program to be executed by the target MPU in the target board’s local memory. MCPN750A (target) Console PPC1-Bug>m 40200;di 5 00040200 39400026 syscall .pcrlf 00040208 39400024 syscall .writeln 00040210 39400026 syscall .
Introduction PPC1-Bug>m 8000EFC4 8000EFC4 08030086? 00008007= 8000EFC4 00000007? . PPC1-Bug> The result of remote program execution can be viewed on the target console: MCPN750A (target) Console PPC1-Bug> 5 Host wrote 0004 to upper half of VR0 Host wrote 0200 to lower half of VR0 Host wrote 0004 to upper half of VR2 Host wrote 0100 to lower half of VR2 GO 00040200 Effective address: 00040200 YOU_DA_MAN! PPC1-Bug> http://www.motorola.
Remote Start Via the PCI Bus Reference Function: srom_crc.c /* * srom_crc - generate CRC data for the passed buffer * description: *This function’s purpose is to generate the CRC for thepassed buffer.
Introduction crc_flipped <<= 1; dbit = crc & 1; crc >>= 1; crc_flipped += dbit; } crc = crc_flipped ^ 0xffffffff; return (crc & 0xffff); } 5 http://www.motorola.
Remote Start Via the PCI Bus 5 5-14 Computer Group Literature Center Web Site
6Functional Description 6 Introduction This chapter describes the MCPN750A single-board computer on a block diagram level. The General Description provides an overview of the MCPN750A, followed by a detailed description of several blocks of circuitry. Figure 6-1 shows a block diagram of the overall board architecture.
Functional Description Table 6-1. MCPN750A Features (Continued) Feature 6 Description Interrupts Software interrupt handling via Raven (PCI-MPU bridge) and Peripheral Bus Controller Serial I/O 1 async port (COM1) via front panel. 4 async ports via the transition module Ethernet I/O 10BaseT/100BaseTX connection via the front panel, or optionally via the transition module rear panel. PCI interface Two Single Wide, or one Double Wide IEEE P1386.
Block Diagram The MCPN750A interfaces to a CompactPCI bus using a DEC 21554 nontransparent PCI-to-PCI bridge device. This device provides a 64-bit primary and a 64-bit secondary interface allowing full 64-bit data access between CompactPCI bus devices and the host/PCI bridge. The nontransparent characteristics of this bridge allows the local MCPN750A processor to configure and control the local MCPN750A resources independently from the system host processor.
Functional Description DRAM (Bank 1) 16M/64M/128M Arbitration Control L2 Cache 1M Processor MPC750 6 66MHz PPC603 Processor Bus Debug Connector DRAM (Bank 2) 16M/64M/128M FLASH (soldered) 4M Memory Controller Falcon 3 Chipset FLASH (socketed) 1M SROM AT24C04 PCI Bridge & MPIC Raven 3 ASIC System Registers Interrupt Serializer Core Power 32/64-bit PMC Slot 1 Reset Control Hot Swap Control 33MHz 32/64-bit PCI Local Bus RS232 IOMX SERIAL 1 SERIAL 2 SERIAL 3 SERIAL 4 (OPTIONAL ROUTING TO T
Block Diagram CompactPCI Bus Interface The CompactPCI bus interface is provided using the Intel 21554 nontransparent PCI-to-PCI bridge chip. This device implements a 64-bit primary data bus and 64-bit secondary data bus interface and is PCI 2.1 compliant. The 21554 provides read/write data buffering in both directions. Unlike a transparent PCI-to-PCI bridge, such as the 21154, the 21554 is designed to bridge two processor domains.
Functional Description Ethernet Interface MCPN750A provides an Ethernet interface via the 21143 device. This device, along with an external Level One LXT970ATC device, implement a 10BaseT/100BaseTX autoselect ethernet interface. The Ethernet interface is routed to an RJ45 connector located at the front panel of the board. The MCPN750A SBC also supports optional routing of the ethernet signals to the J5 connector for ethernet connection on the transition module.
Block Diagram PCI Mezzanine Interface A key feature of the MCPN750A family is the PCI (Peripheral Component Interconnect) bus. In addition to the on-board local bus devices (Ethernet, etc.), the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PMC (PCI Mezzanine Card). This support consists of two singlewide or one double-wide PMC slots. Each slot provides four EIA-E700 AAAB connectors located on the MCPN750A board to interface to a 32/64-bit PMC to add any desirable function.
Functional Description ISA Bus Devices The MCPN750A contains a local ISA bus to provide an interface to ISA compatible devices. The following devices are located on the ISA bus: ❏ Four asynchronous serial ports ❏ Real-Time Clock & NVRAM & Watchdog Timer ❏ Configuration and Status Registers Asynchronous Serial Ports The MCPN750A SBC contains four 16C550C UART devices. Serial port 1 (COM1) is wired as an RS-232 interface to an RJ45 connector on the front panel.
Block Diagram PCI Peripheral Bus Controller (PBC) The MCPN750A uses the VIA Technologies VT82C586B Peripheral Bus Controller (PBC) to supply the interface between the PCI local bus and the ISA, EIDE and USB systems I/O bus (as shown in Figure 6-1 on page 6-4). The PBC controller provides the following functions: ❏ ISA (Industry Standard Architecture) bus arbitration for DMA devices (Note: feature not used since there are no ISADMA devices).
Functional Description EIDE Interface The PBC EIDE interface is capable of accelerated PIO transfers as well as acting as a PCI bus master on behalf of an IDE DMA slave device. The EIDE interface provides a primary and secondary IDE interface, for up to four IDE devices and supports ATAPI-compliant devices. The Primary EIDE channel is routed to the J5 User I/O connector for interfacing to two Compact FLASH cards on the transition module.
Block Diagram Interval Timers The PBC has three built-in counters that are equivalent to those found in a 82C54 programmable interval timer. Each counter output has a specific function: ❏ Counter 0 is associated with IRQ0 and can be used for system timing functions, such as timer interrupt for a time-of-day. ❏ Counter 1 is used to generate a refresh request signal for ISA memory. This timer is not used. ❏ Counter 2 provides the tone for the Speaker output function. This timer is not used.
Functional Description The clock furnishes seconds, minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day months are made automatically. Although the M48T559 is an 8-bit device, 8-, 16-, and 32-bit accesses from the ISA bus to the M48T559 are supported. Refer to the MCPN750A CompactPCI Single Board Computer Programmer’s Reference Guide (MCPN750A/PG) and to the M48T559 Data Sheet for detailed programming and battery life information.
Block Diagram ! Caution ! ❏ Do not disassemble, deform, or apply excessive pressure. ❏ Do not heat or incinerate. ❏ Do not apply solder directly. ❏ Do not use different models, or new and old batteries together. ❏ Do not charge. ❏ Always check proper polarity. Danger of explosion if battery is replaced incorrectly. 6 Replace battery only with the same or equivalent type recommended by the equipment manufacturer.
Functional Description Hot Swap Control Circuitry The MCPN750A provides CompactPCI Hot Swap capability and complies with the CompactPCI Hot Swap Specification (Rev. 1.0). The Hot Swap circuitry supports the process of installing or removing the board without adversely effecting the running system. The Hot Swap circuitry consists of the Linear Technology LTC1643 controller along with some external FETs and discrete components. The two external N-channel FETs control the +5V and +3.
Block Diagram Raven Watchdog Timers The Raven ASIC contains two Watchdog timers, WDT1 and WDT2. Each timer is functionally equivalent but independent. These timers will continuously decrement until they reach a count of 0 or are reloaded by software. The timeout period is programmable from 1 microsecond up to 1024 milliseconds. There is an additional 4.8 second delay for each timer output provided by an external PLD. If the timer count reaches 0, a timer output signal will be asserted.
Functional Description Interval Timers The PBC has three built-in counters that are equivalent to those found in an 82C54 programmable interval timer. The counters are grouped into one timer unit, Timer 1, in the PBC. Each counter output has a specific function: ❏ Counter 0 is associated with interrupt request line IRQ0. It can be used for system timing functions, such as a timer interrupt for a time-of-day function. ❏ Counter 1 generates a refresh request signal for ISA memory.
Block Diagram 2 MXDO Serial 1 4 2 MXSYNC# Serial 2 MXCLK 4 IOMX Function 2 J3 Connector 6 Serial 3 4 MXDI 2 Serial 4 4 Figure 6-2. Serial Port Signal Multiplexing I/O Signal Multiplexing (IOMX) There are four pins that are used for the IOMX function: MXCLK, MXSYNC#, MXDO, and MXDI. MXCLK is the 10 MHz bit clock for the time-multiplexed data lines MXDO and MXDI. MXSYNC# is asserted for one bit time at Time Slot 15 by the MCPN750A board.
Functional Description Table 6-2.
Block Diagram Time Slot 15 Time Slot 0 Time Slot 1 Time Slot 2 Time Slot 3 MMXDO Reserved RTS3 DTR3 RTS1 RTS2 MMXDI DCD2 CTS3 DSR3 DCD3 CTS1 MMXCLK MMXSYNC# 6 Figure 6-3.
Functional Description Front Panel Indicators (DS1 - DS3) There are three LEDs on the MCPN750A front panel: BFL, CPU, and HOT SWAP STATUS. (DS1, yellow). Board Failure; lights when the BRDFAIL∗ signal line is active. ❏ BFL (DS2, green). CPU activity; lights when the DBB∗ (Data Bus Busy) signal line on the processor bus is active. ❏ CPU ❏ HOT SWAP STATUS (DS3, blue). Lights when it is permissible to extract the board.
Block Diagram The MCPN750A also contains four 16-bit Smart Voltage FLASH SMT devices (Intel Part #E28F800CVB70) that appear as FLASH Bank A to the Falcon chipset. The FLASH size for this bank is 4MB when 8Mbit devices are used. Only 32-bit writes are supported for this bank of FLASH. There is a jumper to tell the Falcon chipset where to fetch the reset vector. When the jumper is installed, the Falcon chipset maps 0xFFF00100 to these sockets (Bank B).
Functional Description ECC Memory Controller ECC memory is provided by onboard DRAM devices. The DRAM memory size ranges from 16MB to 256MB. The DRAM memory is controlled by the Falcon chipset which performs two-way interleaving and provides single-bit error correction and double-bit error detection. ECC is calculated over 72-bits. Falcon provides single and double bit error logging by latching the address and syndrome bits associated with the data in error.
Block Diagram TMCPN710 Transition Module The TMCPN710 transition module is used in conjunction with all models of the MCPN750A base board. The transition module provides additional I/O capabilities for the board.
Functional Description ❏ One standard 50-pin CompactFlash socket for IDE Flash For additional information about this transition module, refer to the TM-PIMC-0001 Transition Module Install and Use (TMPIMCA/IH) manual.
7Connector Pin Assignments 7 MCPN750A and Transition Module Connectors This chapter summarizes the pin assignments for the following groups of interconnect signals for the MCPN750A base board, the TMCPN710 transition module, and the TM-PIMC-0001 transition module: – MCPN750A CompactPCI Bus Connectors (J1/J2) – MCPN750A CompactPCI User I/O Connector (J3) – MCPN750A CompactPCI User I/O Connector (J5) – MCPN750A PCI Mezzanine Card (PMC) Connectors (J11/J21, J12/J22, J13/J23, J14/J24) – MCPN750A 10Ba
Connector Pin Assignments MCPN750A Connector Pin Assignments The following tables describe connectors used on the MCPN750A base board. Note that the pin assignments for connectors J3, J4, and J5 apply to both transition modules, as well as the MCPN750A. MCPN750A CompactPCI Bus Connectors (J1/J2) The MCPN750A implements a 64-bit CompactPCI interface on connectors J1 and J2. J1 is a 110 pin AMP Z-pack 2mm hard metric type A connector with keying for +3.3V or +5V.
MCPN750A Connector Pin Assignments Table 7-1. MCPN750A J1 CompactPCI Connector (Continued) 10 AD21 GND +3.3V AD20 AD19 10 9 CBE3_L IDSEL AD23 GND AD22 9 8 AD26 GND VIO AD25 AD24 8 7 AD30 AD29 AD28 GND AD27 7 6 REQ_L GND +3.
Connector Pin Assignments Table 7-2.
MCPN750A Connector Pin Assignments Table 7-3. MCPN750A J3 User I/O Connector ROW A ROW B ROW C ROW D ROW E 19 COM3TD +12V -12V COM4RD UDATA1P 19 18 COM3RD GND USBV1_OK COM4TD UDATA1N 18 17 TMCOM1_L MXCLK MXDI MXSYNC_L MXDO 17 16 COM1TD GND I2CSCL I2CSDA UDATA0P 16 15 COM1RD COM2RD COM2TD USBV0_OK UDATA0N 15 14 +3.3V +3.3V +3.
Connector Pin Assignments Serial COM Ports 1-4: COMnTD - COM Port n Transmit Data Output COMnRD - COM Port n Receive Data Input Miscellaneous: TMCOM1_L - Used to select COM1 active on processor board or on Transition Module MXCLK - multiplexed I/O signal clock, 10 MHz MXSYNC_L - multiplexed I/O sync signal MXDI - multiplexed I/O data in signal from transition module MXDO - multiplexed I/O data out signal to transition module I2CSCL - I2C Serial Clock for Transition Module SROM 7 I2CSDA - I2C Serial Data
MCPN750A Connector Pin Assignments MCPN750A CompactPCI User I/O Connector (J5) Connector J5 is a 110 pin AMP Z-pack 2mm hard metric type B connector. It routes the I/O signals for the PMC2, the IDE port, and the optional ethernet port. Pin assignments (MCPN750A and transition module) are as follows (row F is assigned as ground pins but is not shown in the table): Table 7-4.
Connector Pin Assignments Signal Descriptions PMCIO: PMC2IO (1:64) - PMC 2 I/O signals 1 through 64 EIDE Primary Port (ATA-2): DMARQA - DMA request DMACKA_L - DMA acknowledge DIORA_L - I/O read DIOWA_L - I/O write DIORDYA - indicates drive ready for I/O DD (15:0) - IDE data lines 7 CS1FXA_L - chip select drive 0 or command register block select CS3FXA_L - chip select drive 1 or command register block select DA (2:0) - drive register and data port address lines DRESET_L - drive reset Ethernet: TDP - high
MCPN750A Connector Pin Assignments MCPN750A PCI Mezzanine Card Connectors (J11/21, J12/22, J13/23, J14/24) Four 64-pin connectors (J11/21, 12/22, 13/23 and 14/24 on the MCPN750A) supply the interface between the base board and an optional PCI mezzanine card (PMC). The pin assignments are listed in the tables on the next two pages. Table 7-5.
Connector Pin Assignments Table 7-5. MCPN750A PCI Mezzanine Card Connector (Continued) 47 AD12 AD11 48 47 GND AD10 48 49 AD09 +5V 50 49 AD08 +3.3V 50 51 GND C/BE0# 52 51 AD07 Not Used 52 53 AD06 AD05 54 53 +3.3V Not Used 54 55 AD04 GND 56 55 Not Used GND 56 57 +5V (Vio) AD03 58 57 Not Used Not Used 58 59 AD02 AD01 60 59 GND Not Used 60 61 AD00 +5V 62 61 ACK64# +3.3V 62 63 GND REQ64# 64 63 GND Not Used 64 7 Table 7-6.
MCPN750A Connector Pin Assignments Table 7-6.
Connector Pin Assignments MCPN750A 10BaseT/100BaseTx Connector (J18) The 10BaseT/100BaseTx Connector is an RJ45 connector located on the front panel of the MCPN750A SBC. The pin assignments for this connector are as follows: Table 7-7.
MCPN750A Connector Pin Assignments Table 7-8.
Connector Pin Assignments Table 7-8.
MCPN750A Connector Pin Assignments Table 7-8.
Connector Pin Assignments Table 7-8.
MCPN750A Connector Pin Assignments MCPN750A Processor RISCWatch Debug Connector (J6) A 15-pin header (J6) provides access to the Processor RISCWatch JTAG/COP interface. The pin assignments are listed in the following table. Table 7-9. MCPN750A RISCWatch Debug Connector (J6) 1 TDO No Connect 2 3 TDI TRST-L 4 5 No Connect Pullup 6 7 TCK No Connect 8 9 TMS No Connect 10 11 SRESET_L No Connect 12 13 CPU RESET_L No Pin 14 15 CKSTPO_L GND 16 http://www.motorola.
Connector Pin Assignments TMCPN710 Transition Module The following tables summarize the pin assignments of connectors that are specific to MCPN750A modules configured for use with TMCPN710 transition modules. TMCPN710 Transition Module CompactPCI Connectors (J3/J4/J5) Connector J3 is a 95-pin 2mm hard metric type B connector which routes I/O signals for PMC I/O and serial channels. The pinout for this connector has been described previously in Table 7-3.
TMCPN710 Transition Module TMCPN710 Transition Module COM1 Connector (J6) An RJ45 connector is located on the rear panel of the TMCPN710 Transition Module to provide the interface to the COM1 serial port. The TMCOM1 signal jumper, J7 pins 2 and 3 on the Transition Module, must be installed to enable COM1 on the Transition Module. The pin assignments for this connector is as follows: Table 7-10. TMCPN710 COM1 Connector (J6) 1 DCD 2 RTS 3 GND 4 TXD 5 RXD 6 GND 7 CTS 8 DTR http://www.motorola.
Connector Pin Assignments TMCPN710 Transition Module COM2 Connector (J8) An RJ45 connector is located on the rear panel of the TMCPN710 Transition Module to provide the interface to the COM2 serial port. The pin assignments for this connector is as follows: Table 7-11. TMCPN710 COM2 Connector (J8) 7 1 DCD 2 RTS 3 GND 4 TXD 5 RXD 6 GND 7 CTS 8 DTR TMCPN710 Transition Module COM3 Header (J11) The signals for the COM3 port are routed to a 26 pin header.
TMCPN710 Transition Module Table 7-12. TMCPN710 COM3/COM4 Headers 19 NC NC 20 21 NC NC 22 23 NC NC 24 25 NC NC 26 TMCPN710 Transition Module COM4 Header (J14) Same as above. 7 http://www.motorola.
Connector Pin Assignments TMCPN710 Transition Module 10BaseT/100BaseTx Connector (J13) The 10BaseT/100BaseTx Connector is an RJ45 connector located on the rear panel of the TMCPN710 Transition Module to support optional ethernet I/O from the Transition Module. To enable this option requires that the proper zero ohm resistors be installed on the processor board. The pin assignments for this connector are as follows: Table 7-13.
TMCPN710 Transition Module TMCPN710 Transition Module USB Connectors (J10, J12) Two USB Series A receptacles are located at the rear panel of the TMCPN710 Transition Module. The pin assignments for these connectors are as follows: Table 7-14. TMCPN710 USB 0 Connector (J10) 1 USBVOUT0 2 USB0DATA_N 3 USB0DATA_P 4 GND Table 7-15.
Connector Pin Assignments Table 7-16.
TMCPN710 Transition Module TMCPN710 Transition Module PMC I/O Connectors (J1/J2) Two 68-pin .08 Series Subminiature D connectors (J1/J2) located on the TMCPN710 Transition Module rear panel provide I/O for each of the PMCs on the processor board. The pin assignments and signal mnemonics for these connectors are listed below. Table 7-17.
Connector Pin Assignments Table 7-17.
TM-PIMC-0001 Transition Module TM-PIMC-0001 Transition Module The following tables summarize the pin assignments of connectors that are specific to MCPN750A modules configured for use with the TM-PIMC0001 transition modules. TM-PIMC-0001 CompactPCI User I/O Connector (J3, J4, & J5) Connector J3 is a 95-pin 2mm hard metric type B connector which routes I/O signals for PMC I/O and serial channels. The pinout for this connector has been described previously in Table 7-3.
Connector Pin Assignments TM-PIMC-0001 Transition Module COM1 Connector (J9) An RJ-45 connector is located on the rear panel of the TM-PIMC-0001 Transition Module to provide the interface to the COM1 serial port. The COM1DIR jumper (J11) is a two position (three pin) jumper that controls the origin of the serial port. With pins 2-3 jumpered, COM1 from the MCPN750A SBC is enabled (and thereby disables it on the MCPN750A front panel connector).
TM-PIMC-0001 Transition Module TM-PIMC-0001 Transition Module COM2 Connector (J8) An RJ-45 connector is located on the rear panel of the TM-PIMC-0001 Transition Module to provide the interface to the COM2 serial port. The COM2DIR jumper (J2) is a two position (three pin) jumper that controls the origin of the serial port. With pins 2-3 jumpered, COM2 from the MCPN750A is enabled. With pins 1-2 jumpered, the connector is redirected to the PMC I/O module 2 (PIM2).
Connector Pin Assignments TM-PIMC-0001 Transition Module COM3 and COM4 Connectors (J12 & J13) The signals for the COM3 port and the COM4 port are routed to identical 10-pin headers, which are designated as J12 and J13 respectively on the board. These connections provide rear I/O for the MCPN750A. The pin assignments for these headers are as follows: Table 7-20.
TM-PIMC-0001 Transition Module TM-PIMC-0001 Transition Module 10BaseT/100BaseTx Connector (J7) The 10BaseT/100BaseTx Connector is an RJ45 connector located on the rear panel of the TM-PIMC-0001 Transition Module to support optional ethernet I/O from the MCPN750A SBC. Appropriate zero ohm resistors must be installed on the processor board to enable this option. The pin assignments for this connector are as follows: Table 7-21.
Connector Pin Assignments connected to the Primary IDE channel. Connector J1 is configured as the Master EIDE interface. The pin assignments for these connectors are as follows: Table 7-22.
TM-PIMC-0001 Transition Module TM-PIMC-0001 Transition Module PMC I/O Connectors (J10, J20, and J14/J24) There are two pairs of 64-pin SMT connectors on the TM-PIMC-0001 to provide an interface for two optional plug-in PMC I/O modules (PIMs). Each module has an identical PMC I/O connector (J14 and J24) and a unique host I/O connector (J10 for PIM1 and J20 for PIM2). The pin assignments are as follows: Table 7-23.
Connector Pin Assignments Table 7-23. TM-PIMC-0001 PMC I/O Module 1 (PIM1) - Host I/O Connector Pin Assignments (Continued) 7 43 Reserved USB0_DATAN 44 45 GND USB0_DATAP 46 47 USB1_VOK USB0_VOK 48 49 USB1_DATAP GND 50 51 USB1_DATAN OUT_RI 52 53 +5V OUT_DCD 54 55 OUT_DTR OUT_DSR 56 57 OUT_CTS +3.3V 58 59 OUT_RTS OUT_RXD 60 61 -12V OUT_TXD 62 63 I2C_CLK I2C_DAT 64 Table 7-24.
TM-PIMC-0001 Transition Module Table 7-24. TM-PIMC-0001 PMC I/O Module 2 (PIM2) - Host I/O Connector Pin Assignments (Continued) 27 DA2 DA1 28 29 GND DA0 30 31 DASP DD0 32 33 PDIAG GND 34 35 DD1 DD8 36 37 +5V DD2 38 39 DD9 DD10 40 41 CD2_L +3.3V 42 43 RESERVED RESERVED 44 45 GND RESERVED 46 47 RESERVED RESERVED 48 49 RESERVED GND 50 51 RESERVED OUT_RI 52 53 +5V OUT_DCD 54 55 OUT_DTR OUT_DSR 56 57 OUT_CTS +3.
Connector Pin Assignments Table 7-25.
TM-PIMC-0001 Transition Module Table 7-25. PMC I/O Modules 1 and 2 (PIM1 and PIM2) PMC I/O Connector Pin Assignments (Continued) 55 PMC IO55 PMC IO56 56 57 PMC IO57 PMC IO58 58 59 PMC IO59 PMC IO60 60 61 PMC IO61 PMC IO62 62 63 PMC IO63 PMC IO64 64 Note Pin meaning for the PMC I/O connector is defined entirely by the PMC residing on the host. A host I/O module does not use any pins on this connector. 7 http://www.motorola.
Connector Pin Assignments 7 7-38 Computer Group Literature Center Web Site
ASpecifications A Specifications Table A-1 lists the general specifications for MCPN750A base boards. Subsequent sections detail cooling requirements and FCC compliance. A complete functional description of the MCPN750A base boards appears in Chapter 3. Specifications for the optional PCI mezzanines can be found in the documentation for those modules. Table A-1. MCPN750A Specifications Characteristics Specifications Power requirements (Not TMCPN710 or PMC) +5Vdc (±5%), 2.1A typical +3.3Vdc (±5%), 2.
A Specifications Cooling Requirements The Motorola MCPN750A family of Single Board Computers is specified, designed, and tested to meet thermal performance requirements when installed in a properly designed CompactPCI chassis and supplied with 55 degree C air flow at sea level. Tests were conducted with a Motorola CPX8216 system. Case temperatures of critical, high power density integrated circuits are monitored to ensure component vendors’ specifications are not exceeded.
EMC Compliance EMC Compliance The MCPN750A Single Board Computer was tested in an EMC-compliant chassis and meets the requirements for EN55022 Class B equipment. Compliance was achieved under the following conditions: ❏ Shielded cables on all external I/O ports. ❏ Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel. ❏ Conductive chassis rails connected to earth ground. This provides the path for connecting shields to earth ground.
A Specifications A-4 Computer Group Literature Center Web Site
BRelated Documentation B Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: ❏ Contacting your local Motorola sales office ❏ Visiting Motorola Computer Group’s World Wide Web literature site, http://www.motorola.com/computer/literature Table B-1.
Related Documentation B Manufacturers’ Documents For specific component or software information, refer to the following table for manufacturers’ data sheets or user’s manuals. As an additional help, a source for the listed document is also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice. Table B-2.
Manufacturers’ Documents Table B-2. Manufacturers’ Documents (Continued) Document Title and Source Intel 21143 PCI Fast Ethernet LAN Controller Hardware Reference Manual http://developer.intel.com/design/network/manuals/278074.htm Using the 21143 with External Flash ROM, Serial ROM, and Extreranl Register Application Note Intel 21554 PCI-to-PCI Bridge for Embedded Applications Data Sheet http://developer.intel.com/design/bridge/datashts B Publication Number 278074-001, Rev. 1.
Related Documentation B Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice. Table B-3.
Related Specifications Table B-3. Related Specifications (Continued) Document Title and Source B Publication Number PowerPCTM Microprocessor Common Hardware Reference Platform: A System Architecture (CHRP), Version 1.0 Literature Distribution Center for Motorola Telephone: (800) 441-2447 FAX: (602) 994-6430 or (303) 675-2150 http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com OR Morgan Kaufmann Publishers, Inc.
Related Documentation Table B-3. Related Specifications (Continued) B Document Title and Source Compact PCI Specification PCI-to-PCI Bridge Specification PCI-ISA Specification CompactPCI Hot Swap Specification (Draft) Publication Number CPCI Rev. 2.1 Dated 9/2/97 Rev. 1.02 Rev. 2.0 PICMG 2.1 DO.91 Dated 2/5/98 PCI Industrial Manufacturers Group (PICMG) http://www.picmg.
Index Numerics Abort/Reset switch 6-19 address ethernet 6-6 address decoding with 21554 2-5 arbitration PCI bus masters 2-8 PPC bus 2-6 as debugger console port 1-10 assembly 1-21 assembly language as part of PPCBug 3-3 asynchronous serial ports as ISASIO function 6-8 as transition module feature 6-23 Autoboot enable 4-5, 4-6 for timer 6-11 replacing on-board 6-12 battery backup on board 6-12 battery replacement 6-12 baud rate power up default 1-10 reconfiguring 1-10 BFL board failure light 6-20 big-endi
Index I N D E X changing 4-1 chassis rails, grounding A-3 Checksum Memory remote start 5-6 clocks for system 2-6 CNFG 4-2 CNFG board information block 4-2 COM1 1-10 jumper setting 1-18 COM1 restrictions 1-13 COM1 signal routing 1-13 COM1/COM2 on TM-PIMC-0001 transition module 1-18 COM2 jumper setting J2 on TM-PIMC-0001 1-18 command entries case requirements 3-12 Command/Response Channel Error Codes 5-8 Command/response register (SCRATCH7 register) 5-3 commands PPCBug 3-5 commands, debugger 3-6 Compact FLA
remote start 5-7 DEC21143 ethernet interface 6-6 default map PCI/ISA I/O 2-4 default memory map defined 2-3 devices affected by various resets 2-10 diagnostics directory 3-11 hardware 3-10 prompt 3-2 test groups 3-11 directories, debugger and diagnostic 3-11 DMA channels assignments 2-9 supported by PBC 2-9 documentation on line B-1 downloads to host 5-1 DRAM memory size options 6-22 DRAM speed 4-9 E ECC DRAM memory physical makeup 6-22 ECC memory source 6-22 EIDE interface use 6-10 endian issues function
Index hot swap considerations 1-24 hot swap function 6-14 hot swap removal cautions 1-22 hot swap switch 6-14 hub root to USB host controller 6-10 hubs external 6-10 I I/O I N D E X transition module 6-8 I/O connectors on TM-PIMC-0001 1-20 I/O expansion 6-7 I/O handling 1-4, 1-11, 1-16 initialization process as PPCBug function 3-3 steps 3-3 Initialize Memory remote start 5-5 initializing devices 2-1 install PMC modules on MCPN750A 1-21 installation base board 1-21 installing MCPN750A 1-24 replacement ba
J4 transition module connector 7-18 J5 connector 7-7 for TM-PIMC-0001 7-27 MCPN750A 7-7 J5 transition module connector CompactPCI 7-18 J6 connector on TMCPN710 7-19 processor RISCWatch debug 7-17 J7 connector for TM-PIMC-0001 7-31 J7 jumper use 1-7 J8 connector for TM-PIMC-0001 7-29 J8 header for TMCPN710 7-20 J9 connector for TM-PIMC-0001 7-28 jumper headers MCPN750 base board 1-6 jumper J11 on TM-PIMC-0001 1-18 jumper J2 on TM-PIMC-0001 1-18 jumper J7 configuration requirements 1-13 jumper setting (J11) C
Index N NETboot enable 4-7 Network Auto Boot enable 4-7 NIOT command restrictions 4-8 Non-Volatile RAM (NVRAM) 4-1 as containing PPCBug parameters 4-3 O on-board battery replacing 6-12 on-line documents B-1 operating modes MCPN750A 1-10 operating parameters 4-1 P I N D E X P2MX function 6-17 PBC configuration 6-9 counter function 6-16 functions 6-9 PCI bus 6-3, 6-7, 6-9 PCI expansion 6-7 PCI host bridge 2-6 PCI mezzanine install 1-21 PCI/ISA I/O default map 2-4 PCI-ISA bridge controller (PIB) functions
Auto-Initialize of NVRAM Header Enable 4-4 Bug or System explained 4-3 DRAM Parity Enable 4-10 DRAM Speed in NANO Seconds 4-9 Field Service Menu Enable explained 4-3 L2 Cache Parity Enable 4-10 Memory Size Enable 4-9 Memory Size Ending Address 4-9 Memory Size Starting Address 4-9 Network Auto Boot Abort Delay 4-8 Network Auto Boot at power-up 4-7 Network Auto Boot Configuration Parameters Offset 4-8 Network Auto Boot Controller LUN 4-8 Network Auto Boot Device LUN 4-8 Network Auto Boot Enable 4-7 Network PR
Index I N D E X RF emissions A-3 minimized on TMCPN710 1-29 proper grounding 1-25 RJ45 connector on serial ports 1 and 2 1-13 ROM/Flash Bank A or B mapping 2-4 ROMboot enable 4-7 ROMFAL 4-9 jumper setting (J8) 1-8 startup overview 1-3 switch from one PPCBug directory to another 3-5 System Call Handler PPCBug subroutine 3-6 system clocks 2-6 system startup 2-1 S T SCSI bus 4-4 SCSI bus controller 4-2 SD PPCBug switch command 3-5 SD command 3-10 use 3-2 Serial EEPROM accessing 6-8 use 6-8 set environmen
V voltage MCPN750A 1-31 VT82C586B Peripheral Bus Controller 6-9 W Watchdog timer as part of M48T559 6-15 as reset source 2-10 as type of interrupt 2-9 watchdog timer function 6-11 Watchdog Timer reset 2-11 Watchdog timers as part of Raven 6-15 WDT1 Raven Watchdog timer 6-15 WDT2 Raven Watchdog timer 6-15 World Wide Web address B-1 Write/Read memory remote start 5-6 Write/Read Virtual Register remote start 5-5 I N D E X http://www.mcg.mot.
Index I N D E X IN-10 Computer Group Literature Center Web Site
