MVME177 Single Board Computer Installation and Use Manual VME177A/IH2
Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Preface The MVME177 UserÕs Manual provides general information, hardware preparation and installation instructions, operating instructions, and functional description for the MVME177 Single Board Computer (referred to as MVME177 throughout this manual).
The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., Þrst published 1990, and may be used only under a license such as the License for Computer Programs (Article 14) contained in Motorola's Terms and Conditions of Sale, Rev. 1/79. All Motorola PWBs (printed wiring boards) are manufactured by UL-recognized manufacturers, with a ßammability rating of 94V-0. ! WARNING This equipment generates, uses, and can radiate electromagnetic energy.
Safety Summary Safety Depends On You The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with speciÞc warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the customer's failure to comply with these requirements.
Contents Introduction 1-1 Model Designations 1-1 Features 1-2 SpeciÞcations 1-3 Cooling Requirements 1-3 FCC Compliance 1-5 General Description 1-5 Equipment Required 1-8 Related Documentation 1-9 Support Information 1-11 Manual Terminology 1-12 Introduction 2-1 Unpacking Instructions 2-1 Overview of Start-up Procedure 2-2 Hardware Preparation 2-4 Setup Instructions 2-10 MVME177 Module Installation Instructions 2-12 System Considerations 2-15 Introduction 3-1 Controls and Indicators 3-1 ABORT Switch S1 3-1
SRAM 4-7 Onboard DRAM 4-9 Battery Backed Up RAM and Clock 4-10 VMEbus Interface 4-11 I/O Interfaces 4-11 Serial Port Interface 4-12 Parallel Port Interface 4-14 Ethernet Interface 4-15 SCSI Interface 4-16 SCSI Termination 4-16 Local Resources 4-16 Programmable Tick Timers 4-17 Watchdog Timer 4-17 Software-Programmable Hardware Interrupts 4-17 Local Bus Time-out 4-18 Module IdentiÞcation 4-18 Timing Performance 4-18 Local Bus to DRAM Cycle Times 4-18 ROM Cycle Times 4-19 SCSI Transfers 4-19 LAN DMA Transfers
Disk I/O Support B-13 Blocks Versus Sectors B-13 Device Probe Function B-15 Disk I/O via 177Bug Commands B-16 IOI (Input/Output Inquiry) B-16 IOP (Physical I/O to Disk) B-16 IOT (I/O Teach) B-17 IOC (I/O Control) B-17 BO (Bootstrap Operating System) B-17 BH (Bootstrap and Halt) B-17 Disk I/O via 177Bug System Calls B-17 Default 177Bug Controller and Device Parameters B-19 Disk I/O Error Codes B-19 Network I/O Support B-19 Intel 82596 LAN Coprocessor Ethernet Driver B-20 UDP/IP Protocol Modules B-20 RARP/ARP
177Bug Generalized Exception Handler B-42 Floating Point Support B-44 Single Precision Real B-45 Double Precision Real B-46 Extended Precision Real B-46 Packed Decimal Real B-46 ScientiÞc Notation B-47 Additions to FLASH Commands B-47 Flash Test ConÞguration Acceptable Entries B-48 Erase Test B-48 Flash Fill Test B-48 Flash Patterns Test B-49 Default Flash Test ConÞguration B-50 SFLASH Command B-51 The 177Bug Debugger Command Set B-53 Disk/Tape Controller Modules Supported C-1 Disk/Tape Controller Default C
List of Figures MVME177 Switches, Headers, Connectors, Polyswitches, and LEDs 2-5 MVME177 Block Diagram 4-3
List of Tables MVME177 Model Designations 1-1 MVME177 Features 1-2 MVME177 SpeciÞcations 1-4 Start-up Overview 2-2 ConÞguring MVME177 Headers 2-6 Local Bus Memory Map 3-5 Local I/O Devices Memory Map 3-6 EPROM and Flash Control and ConÞguration 4-5 Diagnostic Test Groups B-26 xii
1General Information 1 Introduction This manual provides: ❏ General information ❏ Preparation for use and installation instructions ❏ Operating instructions ❏ Functional description for the MVME177 series of Single Board Computers (referred to as the MVME177 throughout this manual). Model Designations The MVME177 is available in the models listed in Table 1 - 1. Table 1-1.
1 General Information Features Features of the MVME177 are listed in the following table: Table 1-2.
Specifications Specifications General specifications for the MVME177 are listed in Table 1-3. The following sections detail cooling requirements and FCC compliance. Cooling Requirements The Motorola MVME177 VMEmodule is specified, designed, and tested to operate reliably with an incoming air temperature range from 0û to 55û C (32û to 131û F) with forced air cooling at a velocity typically achievable by using a 100 CFM axial fan.
1 General Information more favorable thermal conditions, it may be possible to operate the module reliably at higher than 55û C with increased airflow. It is important to note that there are several factors, in addition to the rated CFM of the air mover, which determine the actual volume and speed of air flowing over a module. Forced air cooling is required for the Atlas motherboard. Additional cooling is required with the installation of the MPC604 RISC processor.
General Description FCC Compliance The MVME177 was tested in an FCC-compliant chassis, and meets the requirements for Class A equipment. FCC compliance was achieved under the following conditions: 1. Shielded cables on all external I/O ports. 2. Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel. 3. Conductive chassis rails connected to earth ground. This provides the path for connecting shields to earth ground. 4.
1 General Information ❏ One parallel port ❏ A 16/A24/A32/D8/D16/D32/D64 VMEbus master/slave interface ❏ 128KB of static RAM (with optional battery backup), and VMEbus system controller. The I/O on the MVME177 is connected to the VMEbus P2 connector. The main board is connected through a P2 transition board and cables to the transition boards.
General Description ❏ VMEbus interrupter ❏ VMEbus system controller ❏ VMEbus interrupt handler ❏ VMEbus requester Processor-to-VMEbus transfers can be: ❏ D8 ❏ D16 ❏ D32 VMEchip2 DMA transfers to the VMEbus, however, can be: ❏ D16 ❏ D32 ❏ D16/BLT ❏ D32/BLT ❏ D64/MBLT The PCCchip2 ASIC provides: ❏ Two tick timers ❏ Interface to the LAN chip ❏ SCSI chip ❏ Serial port chip ❏ Parallel (printer) port ❏ BBRAM The MCECC memory controller ASIC provides the programmable interface
1 General Information Equipment Required The following equipment is required to make a complete system using the MVME177: ❏ Terminal ❏ Disk drives and controllers ❏ One of the following Transition modules: Ð MVME712-12 Ð MVME712-13 Ð MVME712M Ð MVME712A Ð MVME712AM Ð MVME712B ❏ Connecting cables ❏ P2 adapter ❏ Operating system The MVME177Bug debug monitor firmware (177Bug) is provided in the two EPROMs in sockets on the MVME177 main module.
Related Documentation The MVME712x series of transition modules provide the interface between the MVME177 module and peripheral devices. They connect the MVME177 to: ❏ EIA-232-D serial devices ❏ Centronics-compatible parallel devices ❏ SCSI devices ❏ Ethernet devices The MVME712x series work with cables and a P2 adapter.
1 General Information Document Title Motorola Publication Number 177Bug Diagnostics UserÕs Manual V177DIAA/UM Debugging Package for Motorola 68K CISC CPUs User's Manual 68KBUG1/D and 68KBUG2/D Single Board Computers SCSI Software User's Manual SBCSCSI/D Single Board Computers Programmer's Reference Guide VMESBCA/PG1 and VMESBCA/PG2 MVME712M Transition Module and P2 Adapter Board User's Manual MVME712M/D MVME712-12, MVME712-13, MVME712A, MVME712AM, and MVME712B Transition Module and LCP2 Adapte
Support Information 82596CA Local Area Network Coprocessor Data Sheet, order number 290218; and 82596 User's Manual, order number 296853; Intel Corporation, Literature Sales, P.O. Box 58130, Santa Clara, CA 95052-8130. NCR 53C710 SCSI I/O Processor Data Manual, order number NCR53C710DM; and NCR 53C710 SCSI I/O Processor ProgrammerÕs Guide, order number NCR53C710PG; NCR Corporation, Microelectronics Products Division, Colorado Springs, CO.
1 General Information Manual Terminology Throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric format as follows: $ % & dollar speciÞes a hexadecimal character percent speciÞes a binary number ampersand speciÞes a decimal number Unless otherwise specified, all address references are in hexadecimal.
2Hardware Preparation and Installation 2 Introduction This chapter provides the following for the MVME177: ❏ Unpacking instructions ❏ Hardware preparation ❏ Installation instructions The MVME712x transition module hardware preparation is provided in separate manuals. Refer to Related Documentation in Chapter 1.
Hardware Preparation and Installation 2 Overview of Start-up Procedure The following list identifies the things you will need to do before you can use this board, and where to find the information you need to perform each step. Be sure to read this entire chapter and read all Caution notes before beginning. Table 2-1. Start-up Overview What you will need to do ... Set jumpers on your MVME177 module. Ensure that EPROM devices are properly installed in the sockets.
Overview of Start-up Procedure Table 2-1. Start-up Overview (Continued) What you will need to do ... Note that the debugger prompt appears. Initialize the clock. Examine and/or change environmental parameters. Program the PPCchip2 and VMEchip2. Refer to ... Installation Instructions Debugger General Information.
Hardware Preparation and Installation 2 Hardware Preparation To select the desired configuration and ensure proper operation of the MVME177, certain option modifications may be necessary before installation. The MVME177 provides software control for most of these options. Some options cannot be done in software, so are done by jumpers on headers. Most other modifications are done by setting bits in control registers after the MVME177 has been installed in a system.
Hardware Preparation 28 29 A1 B1 C1 J1 7 18 17 6 7 18 17 6 2 16 LAN +12V 1 15 2 XU2 1 DS1 39 40 2 DS2 XU1 1 FAIL STAT 28 29 39 40 P1 4 19 20 J6 J2 3 J7 J8 1 2 1 2 1 2 3 1 J3 A32 B32 C32 1 2 S1 F2 S2 PRIMARY SIDE RESET 60 59 P4 COMPONENTS ARE REMOVED FOR CLARITY ABORT F1 RUN SCON 2 POLYSWITCH MVME 177 SCSI VME DS3 DS4 A1 B1 C1 60 59 MEZZANINE BOARD 2 1 P2 P5 2 1 1 A32 B32 C32 1 3 3 J10 J9 1817 9604 Figure 2-1.
Hardware Preparation and Installation Table 2-2.
Hardware Preparation Table 2-2.
Hardware Preparation and Installation Table 2-2. Configuring MVME177 Headers (Continued) 2 Header Number Header Description ConÞguration Receive RTXC4 J9 Drive RTXC4 Jumpers 2 -- 3 (Factory conÞguration) J10 Drive TRXC4 1 2 3 7 1 -- 2 Serial Port 4 clock conÞguration select headers Receive TRXC4 Notes 2 -- 3 (Factory conÞguration) 1 2 3 1 2 3 7 1 -- 2 1 2 3 MVME177 Header Notes: 1.
Hardware Preparation MVME177 Header Notes: (Continued) 3. Header J2 is used to select the power source used to back up the SRAM on the MVME177 when the backup battery is installed. ! Do not remove all jumpers from J2. This may disable the SRAM. Caution 4. If you remove the battery, you must install jumpers on J2 between pins 2 and 4, as shown for Backup Power Disabled. The MVME177 can be the VMEbus system controller.
Hardware Preparation and Installation 2 Setup Instructions Even though the MVME177Bug EPROMs are installed on the MVME177 module in the factory, follow this setup procedure for 177Bug to operate properly with the MVME177. ! Inserting or removing modules while power is applied could damage module components. Caution 1. Turn all equipment power OFF. 2. Refer to Table 2-2 in the Hardware Preparation section in this chapter and install/remove jumpers on headers as required for your particular application.
Hardware Preparation 2 Bit Bit #0 (GPI0) J1 Pins 1-2 Bit #1 (GPI1) 3-4 Bit #2 (GPI2) Bit #3 (GPI3) Bit #4 (GPI4) Bit #5 (GPI5) Bit #6 (GPI6) Bit #7 (GPI7) 5-6 7-8 9-10 11-12 13-14 15-16 Description When this bit is a one (high), it instructs the debugger to use local Static RAM for its work page (i.e., variables, stack, vector tables, etc.).
Hardware Preparation and Installation 2 MVME177 Module Installation Instructions When you have configured the MVME177Õs headers and installed the selected EPROMs in the sockets as described previously, install the MVME177 module in the system as follows: 1. Turn all equipment power OFF and disconnect the power cable from the AC power source. ! Inserting or removing modules while power is applied could result in damage to module components.
MVME177 Module Installation Instructions provided, making good contact with the transverse mounting rails to minimize RFI emissions. 5. Remove IACK and BG jumpers from the header on the chassis backplane for the card slot in which the MVME177 is installed. 6. Connect the P2 Adapter Board and specified cable(s) to the MVME177 at P2 on the backplane at the MVME177 slot, to mate with (optional) terminals or other peripherals at the EIA-232-D serial ports, parallel port, SCSI ports, and LAN Ethernet port.
Hardware Preparation and Installation Note 2 In order for high baud-rate serial communication between 177Bug and the terminal to work, the terminal must do some form of handshaking. If the terminal being used does not do hardware handshaking via the CTS line, then it must do XON/XOFF handshaking. If you get garbled messages and missing characters, then you should check the terminal to make sure XON/XOFF handshaking is enabled. 8.
MVME177 Module Installation Instructions Note that when the MVME177 comes up in a cold reset, 177Bug runs in System Mode. Using the Environment (ENV) or MENU commands can make 177Bug run in Board Mode. Refer to the Debugger Commands Table in Appendix B. If the confidence test fails, the test aborts when the first fault is encountered. If possible, an appropriate message displays, and control then returns to the menu. Refer to Appendix B for general information and operation of the Debugger. 13.
Hardware Preparation and Installation firmware. This may be changed, by software, to any other base address. Refer to the Single Board Computers Programmer's Reference Guide for details. 2 If the MVME177 attempts to access offboard resources in a nonexistent location, and is not system controller, and if the system does not have a global bus time-out, the MVME177 waits forever for the VMEbus cycle to complete. This causes the system to hang up.
MVME177 Module Installation Instructions the polyswitch. When using the MVME712M module, the yellow LED (DS1) on the MVME712M front panel lights when LAN power is available, indicating that the polyswitch is good. The MVME177 provides SCSI terminator power through a diode and a 1 amp polyswitch F1 located on the P2 Adapter Board. If the polyswitch is blown (i.e., open), the SCSI devices may not operate or may function erratically.
Hardware Preparation and Installation 2 2-18
3Operating Instructions 3 Introduction This chapter provides necessary information to use the MVME177 module in a system configuration.
Operating Instructions RESET Switch S2 The recessed front panel RESET switch resets all onboard devices, and drives SYSRESET* if the board is system controller. The RESET switch may be disabled by software. 3 The VMEchip2 includes both a global and a local reset driver. When the chip operates as the VMEbus system controller, the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET*.
Controls and Indicators Front Panel Indicators (DS1 - DS4) There are eight LEDs on the MVME177 front panel: FAIL, STAT, RUN, SCON, LAN, +12V (LAN power), SCSI, and VME. The purpose of each LED is as follows: ❏ The red FAIL LED (part of DS1) lights when the BRDFAIL signal line is active ❏ The MC68060 status lines are decoded, on the MVME177, to drive the yellow STAT (status) LED (part of DS1).
Operating Instructions Memory Maps There are two possible perspectives or points of view for memory maps: 3 ❏ The mapping of all resources as viewed by local bus masters (local bus memory map) ❏ The mapping of onboard resources as viewed by VMEbus Masters (VMEbus memory map) Local Bus Memory Map The local bus memory map is split into different address spaces by the transfer type (TT) signals. The local resources respond to the normal access and interrupt acknowledge codes.
Memory Maps Table 3-1.
Operating Instructions 2. This area is user-programmable. The suggested use is shown in the table. The DRAM decoder is programmed in the MCECC chip, and the local-to-VMEbus decoders are programmed in the VMEchip2. 3 3. Size is approximate. 4. Cache inhibit depends on devices in area mapped. 5. This area is not decoded. If these locations are accessed and the local bus timer is enabled, the cycle times out and is terminated by a TEA signal. 6. The SRAM has optional battery backup on the MVME177.
Memory Maps Table 3-2. Local I/O Devices Memory Map (Continued) Address Range $FFF77000 - $FFF77FFF $FFF78000 - $FFF7EFFF $FFF7F000 - $FFF7FFFF $FFF80000 - $FFF9FFFF $FFFA0000 - $FFFBFFFF $FFFC0000 - $FFFCFFFF Devices Accessed Reserved Reserved Reserved Reserved Reserved DS1643/MK48T08 (BBRAM, TOD Clock) $FFFD0000 - $FFFDFFFF Reserved $FFFE0000 - $FFFEFFFF Reserved Port Size -----D32-D8 Size 4KB 28KB 4KB 128KB 128KB 64KB --- 64KB 64KB Notes 2 6 2 6 5 1 5 2 Notes: 1.
Operating Instructions 8. Port commands to the 82596CA must be written as two 16-bit writes: upper word first and lower word second. 9. The CD2401 appears repeatedly from $FFF45200 to $FFF45FFF on the MVME177. If the local bus timer is enabled, the access times out and terminates by a TEA signal. 3 Software Initialization Most functions that have been enabled with switches or jumpers on other modules are enabled by setting control registers on the MVME177.
Software Initialization ❏ Pressing the front panel RESET switch (if the system controller function is disabled) ❏ Asserting a bit in the board control register in the GCSR ❏ SYSRESET* ❏ Power-up reset Note 3 The GCSR allows a VMEbus master to reset the local bus. This feature is very dangerous and should be used with caution. The local reset feature is a partial system reset, not a complete system reset such as power-up reset or SYSRESET*.
Operating Instructions 3 3-10
4Functional Description 4 Introduction This chapter provides a block diagram level description for the MVME177 module. The functional description provides an overview of the module, followed by a detailed description of several blocks of the module. The block diagram of the MVME177 is shown in Figure 4-1 on page 4-3. Descriptions of the other blocks of the MVME177, including programmable registers in the ASICs and peripheral chips, are given in the Single Board Computers Programmer's Reference Guide.
Functional Description local bus to communicate. The local bus is arbitrated by priority type arbiter and the priority of the local bus masters from highest to lowest is: 4 ❏ 82596CA LAN ❏ CD2401 serial (through the PCCchip2) ❏ 53C710 SCSI ❏ VMEbus ❏ MPU In the general case, any master can access any slave; however, not all combinations pass the common sense test.
EPROM 2 44-pin PLCC MC68060 MPU 50 or 60 MHZ VMEchip 2 VMEbus interface 128KB SRAM w/ battery option VMEbus A32/24:D64/32/16/08 Master/Slave 4MB FLASH i82596CA Ethernet Controller Ethernet Transceiver Data MUX Control PCC2 ASIC 1818 9604 Parallel I/O Port Centronics DS1643 or MK48T08 Battery Backed 8KB RAM/Clock CD2401 Quad Serial I/O Controller 4 Asynchronous or 3 Async/1 Sync 4 to 256MB ECC DRAM Address MUX 53C710 SCSI Coprocessor SCSI Peripherals MVME177 Functional Description 4 Fig
Functional Description MC68060 MPU The MC68060 microprocessor is the main processor for the MVME177. The superscalar MC68060 processor has: 4 ❏ Two MC68040-compatible CPU integer cores ❏ MC68040-compatible floating point core ❏ Independent 8KB instruction and operand data caches ❏ MC68040-compatible paged memory management unit ❏ A bus controller The processor is in a PGA socket. Its clock speed is 50 MHz (for the -00x models), and 60 MHz (for the -01x models).
MVME177 Functional Description Table 4-1.
Functional Description The MVME177 implements Flash write protection through clearing a control bit (GPIO1) in the GPIO register in the VMEchip2, to enable write by the software after download process/ programming is completed. EPROM 4 There are two 44-pin PLCC/CLCC EPROM sockets for SGSThompson M27C4002 (256K x 16) or AMD 27C4096 type EPROMs.
MVME177 Functional Description The EPROMs/Flashes are mapped to local bus address 0 following a local bus reset. This allows the MC68060 to access the reset vector and execution address following a reset. The EPROMs are controlled by the VMEchip2. The following items are all programmable: ❏ Map decoder ❏ Access time ❏ Time they appear at address 0 4 For more detail, refer to the VMEchip2 in the Single Board Computers Programmer's Reference Guide.
Functional Description provide an early warning to avoid data loss. Because the DS1210S may block the second access, the software should do at least two accesses before relying on the data. Optionally, the MVME177 provides jumpers that allow the power source of the DS1210S to connect to the VMEbus +5 V STDBY pin or the onboard battery. 4 The optional power source for the SRAM is a socketed Sanyo CR2430 battery. A small capacitor is provided to allow the battery to be quickly replaced without data loss.
MVME177 Functional Description ❏ Do not disassemble, deform, or apply excessive pressure ❏ Do not heat or incinerate ❏ Do not apply solder directly ❏ Do not use different models, or new and old batteries together ❏ Do not charge ❏ Always check proper polarity 4 To remove the battery from the module, carefully pull the battery from the socket. Onboard DRAM The MVME177 onboard DRAM is located on a mezzanine board.
Functional Description Two mezzanine boards may be stacked to provide 256MB of onboard RAM. The main board and a single mezzanine board together take one slot. The stacked configuration requires two VMEboard slots. The DRAM is four-way interleaved to efficiently support cache burst cycles. The DRAM map decoder can be programmed to accommodate different base address(es) and sizes of mezzanine boards. The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM can be accessed.
MVME177 Functional Description ❏ Minutes ❏ Hours ❏ Day ❏ Date ❏ Month ❏ Year 4 in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day months are automatically made. No interrupts are generated by the clock.
Functional Description 4 ❏ Parallel (printer) port ❏ Ethernet transceiver interface ❏ SCSI mass storage interface Serial Port Interface The CD2401 serial controller chip (SCC) is used to implement the four serial ports. The serial ports support the standard baud rates (110 to 38.4K baud). The four serial ports are different functionally because of the limited number of pins on the P2 I/O connector. Serial port 1 is a minimum function asynchronous port.
MVME177 Functional Description ❏ TXD ❏ RTS ❏ DTR It also interfaces to the synchronous clock signal lines. Refer to the Single Board Computers Programmer's Reference Guide for drawings of the serial port interface connections. All four serial ports use EIA-232-D drivers and receivers located on the main board, and all the signal lines are routed to the I/O connector. The configuration headers are located on the main board and the MVME712x transition board.
Functional Description Parallel Port Interface The PCCchip2 provides an 8-bit bidirectional parallel port. All eight bits of the port must be either inputs or outputs (no individual selection). In addition to the 8 bits of data, there are two control pins and five status pins.
MVME177 Functional Description Refer to the Single Board Computers Programmer's Reference Guide for drawings of the printer port interface connections. Ethernet Interface The 82596CA is used to implement the Ethernet transceiver interface. The 82596CA accesses local RAM using DMA operations to perform its normal functions. Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus.
Functional Description SCSI Interface The MVME177 provides for mass storage subsystems through the industry-standard SCSI bus. These subsystems may include: 4 ❏ Hard and floppy disk drives ❏ Streaming tape drives ❏ Other mass storage devices The SCSI interface is implemented using the NCR 53C710 SCSI I/O controller.
MVME177 Functional Description ❏ Note Local bus time-out The time basis for all local resources is set by Prescaler register(s). Refer to the Single Board Computers Programmer's Reference Guide for detailed programming information. 4 Programmable Tick Timers Four 32-bit programmable tick timers with 1 µs resolution are provided: ❏ Two in the VMEchip2 and ❏ Two in the PCCchip2 The tick timers can be programmed to generate periodic interrupts to the processor.
Functional Description Local Bus Time-out The MVME177 provides a time-out function for the local bus. When the timer is enabled and a local bus access times out, a Transfer Error Acknowledge (TEA) signal is sent to the local bus master. The time-out value is selectable by software for: 4 ❏ 8 µsec ❏ 64 µsec ❏ 256 µsec ❏ Infinite The local bus timer does not operate during VMEbus bound cycles. VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer.
MVME177 Functional Description onboard DRAM require 5 bus clock cycles with the bus error reported in the current cycle. Write accesses to onboard DRAM require 2 bus clock cycles. Burst read accesses require 8 (5-1-1-1) bus clock cycles with the bus error reported in the current cycle. Burst write cycles require 5 (2-1-1-1) bus clock cycles. ROM Cycle Times The ROM cycle time is programmable from 4 to 11 bus clock cycles. The data transfers are 32 bits wide.
Functional Description LAN DMA Transfers The MVME177 includes a LAN interface with DMA controller. The LAN DMA controller uses a FIFO buffer to interface the serial LAN bus to the 32-bit local bus. The FIFO buffer allows the LAN DMA controller to efficiently transfer data to the local bus. 4 The 82596CA does not execute MC68060 compatible burst cycles, therefore the LAN DMA controller does not use burst transfers.
AEIA-232-D Interconnections A Introduction The EIA-232-D standard is the most widely used terminal/computer and terminal/modem interface, and yet it is not fully understood. This may be because not all the lines are clearly defined, and many users do not see the need to follow the standard in their applications. Often designers think only of their own equipment, but the state of the art is computer-to-computer or computer-to-modem operation. A system should easily connect to any other system.
A EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Number Mnemonic Signal Name and Description 01 Not used. 02 TxD TRANSMIT DATA. Data to be transmitted; input to the modem from the terminal. 03 RxD RECEIVE DATA. Data which is demodulated from the receive line; output from the modem to the terminal. 04 RTS REQUEST TO SEND. Input to the modem from the terminal when required to transmit a message. With RTS off, the modem carrier remains off.
Levels of Implementation Table A-1. EIA-232-D Interconnections (Continued) Pin Signal Number Mnemonic Signal Name and Description 22 RI RING INDICATOR. Output from the modem to the terminal; indicates to the terminal that an incoming call is present. The terminal causes the modem to answer the phone by carrying DTR true while RI is active. 23 Not used. 24 TxC TRANSMIT CLOCK (DTE). Input to modem from terminal; same function as TxC on pin 15. 25 BSY BUSY. Input to modem from terminal.
A EIA-232-D Interconnections Signal Adaptations One set of handshaking signals frequently implemented are RTS and CTS. CTS is used in many systems to inhibit transmission until the signal is high. In the modem application, RTS is turned around and returned as CTS after 150 microseconds. RTS is programmable in some systems to work with the older type 202 modem (half duplex). CTS is used in some systems to provide flow control to avoid buffer overflow. This is not possible if modems are used.
Levels of Implementation 6850 RXD TXD 3 TXD RXD 2 39kΩ -12V RTS NC 1 CONNECTOR TO TERMINAL +12V LS08 470Ω CTS 470Ω 470Ω CTS 5 DSR OPTIONAL HARDWARE TRANSPARENT MODE DCD DCD SIG GND 6 8 7 TXC RXC LS08 +12V CHASSIS GND LOGIC GND SIG GND 470Ω 7 NC DTR 1 20 6850 TXD 2 TXD RXD 3 RXD -12V 39kΩ RTS RTS 4 470Ω CONNECTOR TO MODEM OR HOST SYSTEM +12V CTS CTS 39kΩ 5 470Ω -12V +12V DCD DCD TXC 6 39kΩ -12V RXC MODULE cb181 9210 Figure A-1.
EIA-232-D Interconnections Figure A-2 shows a way of wiring an EIA-232-D connector to enable a computer to connect to a basic terminal with only three lines. This is feasible because most terminals have a DTR signal that is ON, and which can be used to pull up the CTS, DCD, and DSR signals. Two of these connectors wired back-to-back can be used. In this implementation, however, diagnostic messages that might otherwise be generated do not occur because all the handshaking is bypassed.
Levels of Implementation Proper Grounding Another subject to consider is the use of ground pins. There are two pins labeled GND. Pin 7 is the SIGNAL GROUND and must be connected to the distant device to complete the circuit. Pin 1 is the CHASSIS GROUND, but it must be used with care. The chassis is connected to the power ground through the green wire in the power cord and must be connected to the chassis to be in compliance with the electrical code.
A EIA-232-D Interconnections A-8
BDebugger General Information B Overview of M68000 Firmware The firmware for the M68000-based (68K) series of board and system level products has a common genealogy, deriving from the debugger firmware currently used on all Motorola M68000-based CPU modules.
Debugger General Information ❏ B Various 177Bug routines that handle I/O, data conversion, and string functions available to user programs through the TRAP #15 system calls 177Bug consists of three parts: ❏ A command-driven user-interactive software debugger, described in this appendix, and hereafter referred to as Òthe debuggerÓ or Ò177BugÓ ❏ A command-driven diagnostic package for the MVME177 hardware, hereafter referred to as Òthe diagnosticsÓ ❏ A user interface which accepts commands from the s
Autoboot 177Bug Implementation B MVME177Bug is written largely in the ÒCÓ programming language, providing benefits of portability and maintainability. Where necessary, assembler has been used in the form of separately compiled modules containing only assembler code - no mixed language modules are used. Physically, 177Bug is contained in two 44-pin PLCC/CLCC EPROMs, providing 512KB (128K longwords) of storage.
Debugger General Information exhausted. If a valid bootable device is found, a boot from that device begins. The controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) detected to the highest LUN detected. B At power-up, Autoboot is enabled, and providing the drive and controller numbers encountered are valid, the following message displays on the system console: "Autoboot in progress...
ROMboot B At power-up, the tape controller positions the streaming tape to load point where the volume ID can correctly be read and used. If, however, the MVME177 loses power but the controller does not, and the tape happens to be at load point, the sequences of commands required (attach and rewind) cannot be given to the controller and autoboot will not be successful.
Debugger General Information B ❏ The ASCII string ÒBOOTÓ must be located within the specified memory range ❏ Your routine must pass a checksum test, which ensures that this routine was really intended to receive control at powerup For complete details on how to use ROMboot, refer to the Debugging Package for Motorola 68K CISC CPUs User's Manual.
Restarting the System Network Auto Boot is controlled by parameters contained in the NIOT and ENV commands. These parameters allow: ❏ Selection of specific boot devices ❏ Selection of systems ❏ Selection of files ❏ Programming of the Boot delay Refer to the ENV and NIOT commands in the Commands Table in this Appendix for more details. Also refer to the ENV parameters in Appendix D.
Debugger General Information B Reset Pressing and releasing the MVME177 front panel RESET switch initiates a system reset. COLD and WARM reset modes are available. By default, 177Bug is in COLD mode. During COLD reset, a total system initialization occurs, as if the MVME177 had just been powered up.
Restarting the System program that is being debugged. Abort should be used to regain control if the program gets caught in a loop, etc. The target PC and register contents assist you in locating the malfunction.
Debugger General Information B SYSFAIL* Assertion/Negation Upon a reset/power-up condition the debugger asserts the VMEbus SYSFAIL* line (refer to the VMEbus specification).
Memory Requirements Memory Requirements B The program portion of 177Bug is approximately 512KB of code, consisting of: ❏ Download ❏ Debugger ❏ Diagnostic packages and is contained entirely in EPROM. The EPROM sockets on the MVME177 are mapped starting at location $FF800000. 177Bug requires a minimum of 64KB of contiguous read/write memory to operate. The ENV command controls where this block of memory is located.
Debugger General Information B Terminal Input/Output Control When entering a command at the prompt, the following control codes may be entered for limited command line editing. Note ^X ^H ^D ^A The presence of the caret ( ^ ) before a character indicates that the Control (CTRL) key must be held down while striking the character key. (cancel line) The cursor is backspaced to the beginning of the line.
Disk I/O Support (default). These characters are initialized to ^S and ^Q respectively by 177Bug, but you may change them with the PF command. In the initialized (default) mode, operation is as follows: ^S ^Q (wait) (resume) Console output is halted. Console output is resumed. Disk I/O Support 177Bug can initiate disk input/output by communicating with intelligent disk controller modules over the VMEbus.
Debugger General Information The sector defines the unit of information for the media itself, as viewed by the controller. The sector size varies for different controllers, and the value for a specific device can be displayed and changed with the IOT command.
Disk I/O Support When a disk transfer is requested: B ❏ Start and size of the transfer is specified in blocks ❏ 177Bug translates this into an equivalent sector specification ❏ Passes the sector specification on to the controller to initiate the transfer If the conversion from blocks to sectors yields a fractional sector count, an error is returned and no data is transferred.
Debugger General Information The device probe mechanism utilizes the SCSI commands ÒInquiryÓ and ÒMode SenseÓ. If the specified controller is non-SCSI, the probe simply returns a status of Òdevice present and unknownÓ. The device probe makes an entry into the device descriptor table with the pertinent data. After an entry has been made, the next time a probe is done it simply returns with Òdevice presentÓ status (pointer to the device descriptor).
Disk I/O Support IOT (I/O Teach) B IOT allows you to change any configurable parameters and attributes of the device. In addition, it allows you to view the controllers available in the system. IOC (I/O Control) IOC allows you to send command packets as defined by the particular controller directly. IOC can also be used to examine the resultant device packet after using the IOP command.
Debugger General Information B .DSKCFIG Disk conÞgure. Use this system call to change the conÞguration of the speciÞed device. .DSKFMT Disk format. Use this system call to send a format command to the speciÞed device. .DSKCTRL Disk control. Use this system call to implement any special device control functions that cannot be accommodated easily with any of the other disk functions.
Disk I/O Support Default 177Bug Controller and Device Parameters B 177Bug initializes the parameter tables for a default configuration of controllers and devices (refer to Appendix C). If the system needs to be configured differently than this default configuration (for example, to use a 70MB Winchester drive where the default is a 40MB Winchester drive), then these tables must be changed. There are three ways to change parameter table contents: ❏ Using BO or BH.
Debugger General Information B ❏ The first phase: the diskless remote node discovers its network identify and the name of the file to be booted ❏ The second phase: the diskless remote node reads the boot file across the network into its memory The various modules (capabilities) and the dependencies of these modules that support the overall network boot function are described in the following paragraphs Intel 82596 LAN Coprocessor Ethernet Driver This driver manages/surrounds the Intel 82596 LAN Copro
Disk I/O Support RARP/ARP Protocol Modules B The Reverse Address Resolution Protocol (RARP) basically consists of: ❏ An identity-less node broadcasting a ÒwhoamiÓ packet onto the Ethernet ❏ The node awaiting an answer ❏ The RARP server filling an Ethernet reply packet with the target's Internet Address ❏ The RARP server sending it to the node The Address Resolution Protocol (ARP) basically provides a method of converting protocol addresses (e.g., IP addresses) to local area network addresses (e.
Debugger General Information B Network Boot Control Module The ÒcontrolÓ capability of the Network Boot Control Module is needed to tie together all the necessary modules (capabilities) and to sequence the booting process. The booting sequence consists of two phases: ❏ ÒAddress determination and bootfile selectionÓ phase ❏ ÒFile transferÓ phase The first phase utilizes the RARP/BOOTP capability and the second phase utilizes the TFTP capability.
Multiprocessor Support The status codes stored in the MPCR are of two types: ❏ Status returned (from the monitor) ❏ Status set (by the bus master) B The status codes that may be returned from the monitor are: HEX 0 ASCII R ASCII E (HEX 00) (HEX 52) (HEX 45) ---- Wait. Initialization not yet complete. Ready. The Þrmware monitor is watching for a change. Code pointed to by the MPAR address is executing.
Debugger General Information An ASCII G placed in the MPCR by a remote processor indicates that the Go Direct type of transfer is requested. An ASCII B in the MPCR indicates that breakpoints are to be armed before control is transferred (as with the GO command). B In either sequence, an E is placed in the MPCR to indicate that execution is underway just before control is passed to RAM. (Any remote processor could examine the MPCR contents).
Diagnostic Facilities and Status Registers (LCSR) of the MVME177. The execution address is formed by reading the GCSR general purpose registers in the following manner: GPCSR0 GPCSR1 used as the upper 16 bits of the address used as the lower 16 bits of the address The address appears as: GPCSR0 GPCSR1 Diagnostic Facilities The 177Bug hardware diagnostics are intended for testing and troubleshooting of the MVME177. In order to use the diagnostics, you must switch to the diagnostic directory.
Debugger General Information B Table B-1.
Using the 177Bug Debugger Using the 177Bug Debugger B Entering Debugger Command Lines 177Bug is command-driven and performs its various operations in response to user commands entered at the keyboard. When the debugger prompt (177-Bug>) appears on the terminal screen, then the debugger is ready to accept commands. As the command line is entered, it is stored in an internal buffer.
Debugger General Information The commands are shown using a modified Backus-Naur form syntax. The metasymbols used are: B boldface strings italic strings | [] {} A boldface string is a literal such as a command or a program name, and is to be typed just as it appears. An italic string is a Òsyntactic variableÓ and is to be replaced by one of a class of items it represents.
Using the 177Bug Debugger Expression as a Parameter B An expression can be one or more numeric values separated by the arithmetic operators: ❏ Plus (+) ❏ Minus (-) ❏ Multiplied by (*) ❏ Divided by (/) ❏ Logical AND (&) ❏ Shift left (<<) ❏ Shift right (>>) Numeric values may be expressed in either: ❏ Hexadecimal ❏ Decimal ❏ Octal ❏ Binary by immediately preceding them with the proper base identifier.
Debugger General Information A numeric value may also be expressed as a string literal of up to four characters. The string literal must begin and end with the single quote mark ('). The numeric value is interpreted as the concatenation of the ASCII values of the characters. This value is right-justified, as any other numeric value would be.
Using the 177Bug Debugger Address as a Parameter B Many commands use ADDR as a parameter. The syntax accepted by 177Bug is similar to the one accepted by the MC68060 one-line assembler. All control addressing modes are allowed. An Òaddress + offset registerÓ mode is also provided. Address Formats Table B-2 summarizes the address formats which are acceptable for address parameters in debugger command lines. Table B-2.
Debugger General Information An Xn d bd od n Rn B Note Ñ Ñ Ñ Ñ Ñ Ñ Ñ Address register n. Index register n (An or Dn). Displacement (any valid expression). Base displacement (any valid expression). Outer displacement (any valid expression). Register number (0 to 7). Offset register n.
Using the 177Bug Debugger Example: B A portion of the listing file of an assembled, relocatable module is shown below: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ****** ****** 0 0 0 0 0 0 0 0 00000000 00000004 00000006 00000008 0000000A 0000000C 00000010 00000014 48E78080 4280 1018 5340 12D8 51C8FFFC 4CDF0101 4E75 * * MOVE STRING SUBROUTINE * MOVESTR MOVEM.L D0/A0,—(A7) CLR.L D0 MOVE.B (A0)+,D0 SUBQ.W #1,D0 LOOP MOVE.B (A0)+,(A1)+ MOVS DBRA D0,LOOP MOVEM.
Debugger General Information B 177Bug>OF R0 R0 =00000000 00000000? 1327C. 177Bug>MD 0+R0;DI 00000+R0 48E78080 MOVEM.L 00004+R0 4280 CLR.L 00006+R0 1018 MOVE.B 00008+R0 5340 SUBQ.W 0000A+R0 12D8 MOVE.B 0000C+R0 51C8FFFC DBF 00010+R0 4CDF0101 MOVEM.L 00014+R0 4E75 RTS 177Bug> D0/A0,—(A7) D0 (A0)+,D0 #1,D0 (A0)+,(A1)+ D0,$A+R0 (A7)+,D0/A0 For additional information about the offset registers, refer to the Debugging Package for Motorola 68K CISC CPUs User's Manual.
Entering and Debugging Programs Entering and Debugging Programs B There are various ways to enter a user program into system memory for execution. One way is to create the program using the Memory Modify (MM) command with the assembler/disassembler option. You enter the program one source line at a time. After each source line is entered, it is assembled and the object code loads into memory.
Debugger General Information B Calling System Utilities from User Programs A convenient way of doing character input/output and many other useful operations has been provided so that you do not have to write these routines into the target code. You can access various 177Bug routines via one of the MC68060 TRAP instructions, using vector #15.
Preserving the Debugger Operating Environment ❏ Allocates space for the system stack ❏ Initializes the system stack pointer to the top of this area B With the exception of the first 1024-byte vector table area, you must be extremely careful not to use the above-mentioned memory areas for other purposes. You should refer to the Memory Requirements section in Chapter 3 to determine how to dictate the location of the reserved memory areas.
Debugger General Information B Table B-3. Exception Vectors Used by 177Bug Vector Offset $10 $24 $80-$B8 $BC $Note $Note $DC Exception 177Bug Facility Illegal instruction Breakpoints (used by GO, GN, GT) Trace Trace operations (such as T, TC, TT) TRAP #0 - #14 Used internally TRAP #15 System calls Level 7 interrupt ABORT push-button Level 7 interrupt AC Fail FP Unimplemented Data Software emulation and data type Type conversion of ßoating point data.
Preserving the Debugger Operating Environment Notice that the value of the target stack pointer register (A7) has not changed even though a trace exception has taken place. Your program may either use the exception vector table provided by 177Bug or it may create a separate exception vector table of its own. The two following sections detail these two methods. Using 177Bug Target Vector Table The 177Bug initializes and maintains a vector table area for target programs.
Debugger General Information B Creating a New Vector Table Your program may create a separate vector table in memory to contain its exception vectors. If this is done, the program must change the value of the VBR to point to the new vector table. In order to use the debugger facilities you can copy the proper vectors from the 177Bug vector table into the corresponding vector locations in your program vector table.
Preserving the Debugger Operating Environment It may happen that your program uses one or more of the exception vectors that are required for debugger operation. Debugger facilities may still be used, however, if your exception handler can determine when to handle the exception itself and when to pass the exception to the debugger. When an exception occurs which you want to pass on to the debugger; i.e.
Debugger General Information B 177Bug Generalized Exception Handler The 177Bug has a generalized exception handler which it uses to handle all of the exceptions not listed in Table B-3. For all these exceptions, the target stack pointer is left pointing to the top of the exception stack frame created. In this way, if an unexpected exception occurs during execution of your code, you are presented with the exception stack frame to help determine the cause of the exception.
Preserving the Debugger Operating Environment 177Bug>RD PC =000E0000 SR =2700=TR:OFF_S._7_..... VBR =00000000 SSP* =00010000 USP =00010000 SFC =1=UD DFC =1=UD CACR =00000000=D:....._B:..._I:...
Debugger General Information B Floating Point Support The floating point unit (FPU) of the MC68060 microprocessor chip is supported in 177Bug. For MVME177Bug, the commands: ❏ MD ❏ MM ❏ RM ❏ RS have been extended to allow display and modification of floating point data in registers and in memory. Floating point instructions can be assembled/disassembled with the DI option of the MD and MM commands.
Floating Point Support When entering data in: ❏ Single precision ❏ Double precision ❏ Extended precision ❏ Packed decimal format B the following rules must be observed: 1. The sign field is the first field and is a binary field. 2. The exponent field is the second field and is a hexadecimal field. 3. The mantissa field is the last field and is a hexadecimal field. 4.
Debugger General Information B Double Precision Real This format would appear in memory as: 1-bit sign Þeld (1 binary digit) 11-bit biased exponent Þeld (3 hex digits. Bias = $3FF) 52-bit fraction Þeld (13 hex digits) A double precision number requires 8 bytes in memory. Note The single and double precision formats have an implied integer bit (always 1). Extended Precision Real This format would appear in memory as: 1-bit sign Þeld (1 binary digit) 15-bit biased exponent Þeld (4 hex digits.
Additions to FLASH Commands Scientific Notation B This format provides a convenient way to enter and display a floating point decimal number. Internally, the number is assembled into a packed decimal number then converted into a number of the specified data type.
Debugger General Information B Flash Test Configuration Acceptable Entries Command Input: 177-Diag>cf flash FLASH Configuration Data: Flash Device Test Mask =00000001 ? 0 or 1 Flash Test Starting Block =00000000 ? 0 through F Flash Test Ending Block =0000000F ? 0 through F Save/Restore For PATS Test [Y?N] =Y ? Y or N Fill Data =000000FF ? any byte 00 through FF Test Data Increment/Decrement Step =00000001? 0, 1, 2, F (-1) etc.
Additions to FLASH Commands The Flash Fill test fills Flash memory according to the current test configuration parameters selecting: ❏ Starting and ending block ❏ The data to fill with ❏ An increment/decrement value Command Input: 177-Diag>flash fill Flash Patterns Test The Flash Patterns test writes and reads various data patterns in Flash memory according to the current test configuration parameters selecting starting and ending blocks, and saving / restoring of the Flash contents.
Debugger General Information B Default Flash Test Configuration Command Input: 177-Diag>cf flash FLASH Configuration Data: Flash Device Test Mask =00000001 ? Flash Test Starting Block =00000000 ? Flash Test Ending Block =0000000F ? Save/Restore For PATS Test [Y?N] =Y ? Fill Data =000000FF ? Test Data Increment/Decrement Step =00000001? Physical Address $FFBFFFFF $FFA00000 J8 Installed J8 Installed J8 Removed UPPER FLASH LOWER FLASH UPPER FLASH PROM LOWER FLASH PROM $FF800000 Flash Relative (off
Additions to FLASH Commands These addressing methods apply no matter which of the three mapping options is in effect when the PFLASH command is entered. B Two sets of information are reported to the user when the PFLASH command is executed: ❏ The user is asked to verify the arguments entered. ❏ The block number and physical address for each operation (erasing, programming, and verifying) is displayed.
Debugger General Information 177-Diag>sflash;l FLASH Memory Visible Now = Lower Half B 177-Diag>sflash;u FLASH Memory Visible Now = Upper Half 177-Diag>sflash FLASH Memory Visible Now = Lower Half The destination address DSAADR of the PFLASH command is always interpreted using the J8 removed mapping, all of Flash mapped in. See Figure B-1, Three Possible Mapping Options. This mapping is used whether or not J8 is installed and regardless of the most recent SFLASH command.
The 177Bug Debugger Command Set Additionally, both of these PFLASH commands do the same thing when J8 is removed as they do when J8 is installed, regardless of any SFLASH command that may have been executed. In the case where the bug is programming over itself the user will not regain the bug prompt. Successful programming is indicated by the FAIL LED blinking twice per second.
Debugger General Information Table B-4.
The 177Bug Debugger Command Set Table B-4.
Debugger General Information B Table B-4.
The 177Bug Debugger Command Set Table B-4.
Debugger General Information B B-58
CDisk/Tape Controller Data C Disk/Tape Controller Modules Supported The following VMEbus disk/tape controller modules are supported by 177Bug. The default address for each controller type is First Address. The controller can be addressed by First CLUN during: ❏ Command BH ❏ Command BO ❏ Command IOP ❏ TRAP #15 calls .DSKRD or .
Disk/Tape Controller Data Disk/Tape Controller Default Configurations C Note SCSI Common Command Set (CCS) devices are only the ones tested by Motorola Computer Group.
Disk/Tape Controller Default Configurations MVME323 -- Four Devices Controller LUN Address 8 $FFFFA000 9 $FFFFA200 Device LUN 0 1 2 3 Device Type C ESDI Winchester hard drive ESDI Winchester hard drive ESDI Winchester hard drive ESDI Winchester hard drive MVME327A --Nine Devices Controller LUN Address 2 $FFFFA600 3 $FFFFA700 Device LUN Device Type 00 10 20 30 40 50 60 SCSI Common Command Set (CCS), which may be any of these: - Fixed direct access - Removable ßexible direct access (TEAC s
Disk/Tape Controller Data MVME328 -- Fourteen Devices Controller LUN Address 6 $FFFF9000 7 $FFFF9800 16 $FFFF4800 C 17 $FFFF5800 18 $FFFF7000 19 $FFFF7800 Device LUN Device Type 00 08 10 18 20 28 30 SCSI Common Command Set (CCS), which may be any of these: - Removable ßexible direct access (TEAC style) - CD-ROM - Sequential access 40 48 50 58 60 68 70 Same as above, but these will only be available if the daughter card for the second SCSI channel is present.
IOT Command Parameters for Supported Floppy Types IOT Command Parameters for Supported Floppy Types The following table lists the proper IOT command parameters for floppies used with boards such as the: ❏ MVME328 ❏ MVME167 ❏ MVME177 ❏ MVME187 Floppy Types and Formats IOT Parameter DSDD5 PCXT8 Sector Size 0- 128 1- 256 2- 512 3-1024 4-2048 5-4096 1 2 2 2 Block Size: 0- 128 1- 256 2- 512 3-1024 4-2048 5-4096 1 1 1 Sectors/Track 10 8 Number of Heads 2 Number of Cylinders PCXT9 PCXT9_
Disk/Tape Controller Data Floppy Types and Formats (Continued) IOT Parameter C DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT Number of Physical Sectors 0A00 0280 02D0 05A0 Number of Logical Blocks (100 in size) 09F8 0500 05A0 0B40 Number of Bytes in Decimal 653312 327680 368460 737280 PS2 SHD 0960 0B40 1680 12C0 1680 2D00 Other Characteristics Media Size/Density Notes: C-6 1. 2. 1228800 1474560 2949120 5.25/DD 5.25/DD 5.25/DD 3.5/DD 5.25/D 3.5/HD 3.
DConfigure and Environment Commands D Configure Board Information Block CNFG [;[I][M]] This command is used to display and configure the board information block. This block resides within the Non-Volatile RAM (NVRAM). Refer to the Single Board Computer Programmer's Reference Guide for the actual location. The information block contains various elements detailing specific operation parameters of the hardware.
Configure and Environment Commands Note that the parameters that are quoted are left-justified character (ASCII) strings padded with space characters, and the quotes (") are displayed to indicate the size of the string. Parameters that are not quoted are considered data strings, and data strings are rightjustified. The data strings are padded with zeroes if the length is not met.
Set Environment to Bug/Operating System Set Environment to Bug/Operating System ENV [;[D]] The ENV command allows you to interactively view/configure all Bug operational parameters that are kept in Battery Backed Up RAM (BBRAM), also known as Non-Volatile RAM (NVRAM). The operational parameters are saved in NVRAM and used whenever power is lost. Any time the Bug uses a parameter from NVRAM, the NVRAM contents are first tested by checksum to insure the integrity of the NVRAM contents.
Configure and Environment Commands Auto Boot Enable [Y/N] = N? Auto Boot at power-up only [Y/N] = Y? Auto Boot Controller LUN = 00? Auto Boot Device LUN = 00? Auto Boot Abort Delay = 15? Auto Boot Default String [NULL for a empty string] = ? ROM Boot Enable [Y/N] = N? ROM Boot at power-up only [Y/N] = Y? ROM Boot Enable search of VMEbus [Y/N] = N? ROM Boot Abort Delay = 0? ROM Boot Direct Starting Address = FF800000? ROM Boot Direct Ending Address = FFBFFFFC? Network Auto Boot Enable [Y/N] = N? Network Aut
Set Environment to Bug/Operating System Master Starting Address #2 = 00000000? Master Ending Address #2 = 00000000? Master Control #2 = 00? Master Enable #3 [Y/N] = N? Master Starting Address #3 = 00000000? Master Ending Address #3 = 00000000? Master Control #3 = 00? Master Enable #4 [Y/N] = N? Master Starting Address #4 = 00000000? Master Ending Address #4 = 00000000? Master Address Translation Address #4 = 00000000? Master Address Translation Select #4 = 00000000? Master Control #4 = 00? Short I/O (VMEbu
Configure and Environment Commands Table D-1.
Set Environment to Bug/Operating System Table D-1. ENV Command Parameters (Continued) ENV Parameter and Options Auto Boot Default String [Y(NULL String)/(String)] Default Meaning of Default You may specify a string (Þlename) which is passed on to the code being booted. Maximum length is 16 characters. Default is the null string. ROM Boot Enable [Y/N] N ROMboot function is disabled. ROM Boot at power-up only [Y/N] Y ROMboot is attempted at power up only.
Configure and Environment Commands Table D-1. ENV Command Parameters (Continued) ENV Parameter and Options Network Autoboot ConÞguration Parameters Pointer (NVRAM) D Default Meaning of Default 00000000 This is the address where the network interface conÞguration parameters are to be saved/retained in NVRAM; these parameters are the necessary parameters to perform an unattended network boot.
Set Environment to Bug/Operating System Table D-1. ENV Command Parameters (Continued) ENV Parameter and Options Memory Search Starting Address Memory Search Ending Address Memory Search Increment Size Memory Search Delay Enable [Y/N] Default Meaning of Default 00000000 Where the Bug begins to search for a work page (a 64KB block of memory) to use for vector table, stack, and variables. This must be a multiple of the debugger work page, modulo $10000 (64KB).
Configure and Environment Commands Table D-1. ENV Command Parameters (Continued) ENV Parameter and Options Memory Search Delay Address D Memory Size Enable [Y/N] Memory Size Starting Address Memory Size Ending Address Base Address of Local Memory Size of Local Memory Board #0 Size of Local Memory Board #1 D-10 Default Meaning of Default FFFFCE0F Default address is $FFFFCE0F.
Set Environment to Bug/Operating System Table D-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Slave address decoders setup. The slave address decoders are use to allow another VMEbus master to access a local resource of the MVME177. There are two slave address decoders set. They are set up as follows: Slave Enable #1 [Y/N] Y Yes, set up and enable the Slave Address Decoder #1.
Configure and Environment Commands Table D-1. ENV Command Parameters (Continued) ENV Parameter and Options Slave Ending Address #2 D Default Meaning of Default FFE1FFFF Ending address of the local resource that is accessible by the VMEbus. Default is the end of static RAM, $FFE1FFFF. Slave Address Translation Address 00000000 Works the same as Slave Address #2 Translation Address #1. Default is 0. Slave Address Translation Select #2 00000000 Works the same as Slave Address Translation Select #1.
Set Environment to Bug/Operating System Table D-1.
Configure and Environment Commands Table D-1.
ENetwork Controller Data E Network Controller Modules Supported The VMEbus network controller modules in the following table are supported by 177Bug. The default address for each type and position is shown to indicate where the controller must reside to be supported by 177Bug. The controllers are accessed via the specified CLUN and DLUNs listed here.
Network Controller Data Controller Type E E-2 CLUN DLUN Address Interface Type MVME177 $00 $00 $FFF46000 Ethernet MVME376 $02 $00 $FFFF1200 Ethernet MVME376 $03 $00 $FFFF1400 Ethernet MVME376 $04 $00 $FFFF1600 Ethernet MVME376 $05 $00 $FFFF5400 Ethernet MVME376 $06 $00 $FFFF5600 Ethernet MVME376 $07 $00 $FFFFA400 Ethernet MVME374 $10 $00 $FF000000 Ethernet MVME374 $11 $00 $FF100000 Ethernet MVME374 $12 $00 $FF200000 Ethernet MVME374 $13 $00 $FF300
FTroubleshooting the MVME177: Solving Startup Problems F ❏ Try these simple troubleshooting steps before calling for help or sending your CPU board back for repair. ❏ Some of the procedures will return the board to the factory debugger environment. (The board was tested under these conditions before it left the factory.) ❏ Selftest may not run in all user-customized environments. Table F-1. Basic Troubleshooting Steps Condition ... Possible Problem ... Try This ... I.
Troubleshooting the MVME177: Solving Startup Problems Table F-1. Basic Troubleshooting Steps (Continued) Condition ... Possible Problem ... Try This ... II. There is a display on the terminal, but input from the keyboard and/or mouse has no effect. A. The keyboard or mouse may be connected incorrectly. Recheck the keyboard and/or mouse connections and power. B. Board jumpers may be conÞgured incorrectly. Check the board jumpers per this manual. C.
Table F-1. Basic Troubleshooting Steps (Continued) Condition ... Possible Problem ... Try This ... IV. Debug prompt A. The initial debugger environment parameters may be set wrong. 1. Start the onboard calendar clock and timer. Type set mmddyyhhmm where the characters indicate the month, day, year, hour, and minute. The date and time will be displayed. 177-Bug> appears at powerup, but the board does not auto boot. B. There may be some fault in the board hardware.
Troubleshooting the MVME177: Solving Startup Problems Table F-1. Basic Troubleshooting Steps (Continued) Condition ... Possible Problem ... Try This ... 6.You may need to use the cnfg command (see your board Debugger Manual) to change clock speed and/or Ethernet Address, and then later return to env and step 3. 7. Run selftest by typing in st The tests take as much as 10 minutes, depending on RAM size. They are complete when the prompt returns.
Index Numerics B 177Bug C-1 network controller data E-1 177Bug (see debug monitor and MVME177Bug) 1-8, 2-4, 3-1, 3-8, B-27 177Bug Generalized Exception Handler B-42 177Bug generalized exception handler B-42 177Bug implementation B-3 177Bug stack B-11 177Bug vector table and workspace B-36 5-1/4 DS/DD 96 TPI floppy drive C-2 53C710 (see SCSI Controller) 4-15 82596CA (see Ethernet and LAN) 4-15 Backus-Naur B-28 base and top addresses B-32 base identifier B-29 Battery Backed Up RAM (BBRAM) and Clock (see M
Index I N D E X CD2401 (see SCC and Serial Controller Chip) 4-12 CD2401 Serial Controller Chip (SCC) 2-14 CFM (cubic feet per minute) 1-3 chassis ground A-7 checksum D-3 CISC Single Board Computer(s) (SBC) C-1 Clear To Send (CTS) 2-14 CLUN (controller LUN) C-1, E-1 CNFG command D-1 command entry B-26 command identifier B-27 command line B-27 conductive chassis rails 1-5 configuration, default disk/tape controller C-2 Configure (CNFG) and Environment (ENV) commands D-1 configure BIB (Board Information Bloc
dynamic RAM (DRAM) 4-9 E EIA-232-D 4-13 EIA-232-D interconnections A-1, A-2 EIA-232-D port(s) 2-13, B-37 EIA-232-D standard A-1 entering and debugging programs B-35 entering debugger command lines B-27 ENV command D-3 parameters D-6 Environment (ENV) and Configure (CNFG) commands D-1 EPROM sockets 1-8 EPROM(s) 2-10, 2-11, 3-5, 3-8, 4-4 EPROM/Flash Configuration Jumper 2-7 equipment required 1-8 ESDI Winchester hard drive C-3 Ethernet E-1 Ethernet (see 82596 and LAN) E-2 Ethernet (see 82596CA and LAN) 2-16,
Index hardware interrupts software-programmable 4-17 hardware preparation 2-4 headers 2-10 hexadecimal character 1-12 host port B-34 host system B-35 I I/O interfaces 4-11 IACK (interrupt acknowledge) 2-13 installation instructions 2-10 Intel 82596 LAN Coprocessor Ethernet driver B-20 interrupt acknowledge (IACK) 2-13 Interrupt Stack Pointer (ISP) B-11 interrupts 4-17 introduction 1-1, 2-1, 3-1, 4-1, A-1 IOC (I/O Control) B-17 IOI (Input/Output Inquiry) B-16 IOP (Physical I/O to Disk) B-16 IOT (I/O Teach)
models, MVME177 iii modem(s) A-1 MPAR (Multiprocessor Address Register) B-23 MPCR (Multiprocessor Control Register) Method B-22 MPU clock speed calculation B-10 multi-MPU programming considerations 3-8 Multiprocessor Address Register (MPAR) B-23 Multiprocessor Control Register (MPCR) Method B-22 multiprocessor support B-22 MVME177 Features 1-2 MVME177 functional description 4-1 MVME177 model designations 1-1 MVME177 module installation 2-12 MVME177 Network Controller Modules Supported E-2 MVME177 specificat
Index port 1 or 01 B-34 port number(s) B-27, B-34 preserving the debugger operating environment B-36 printer interface 4-14 printer port 4-14 programmable hardware interrupts 4-17 programmable tick timers 4-17 proper grounding A-7 pseudo-registers B-32 Q QIC-02 streaming tape drive C-4 R range B-28 RARP/ARP Protocol Modules B-21 Readable Jumper J1 2-8 registers 3-8 default values 3-8 relative address+offset B-32 remote status and control J3 4-20 reset B-8 RESET switch S2 3-2, 3-9 restart mode B-26 restar
S-record format B-35 SRST (system reset) 3-2, 3-8 start-up procedure overview 2-2 static RAM (SRAM) 4-7 static variable space B-11 streaming tape drive (see QIC-2 streaming tape drive) C-4 string literal B-30 support information 1-11 syntactic variables B-28 SYSFAIL* assertion/negation B-10 SYSRESET* (see system reset) 3-2, 3-9 system considerations 2-15 system console 2-13 system console terminal 1-8 system controller function 3-9 System Controller Header 2-7 System Fail (SYSFAIL*) B-5 System Mode 2-15 sys
