user manual

Operating Instructions
3-6
3
2. This area is user-programmable. The suggested use is shown in
the table. The DRAM decoder is programmed in the MCECC chip,
and the local-to-VMEbus decoders are programmed in the
VMEchip2.
3. Size is approximate.
4. Cache inhibit depends on devices in area mapped.
5. This area is not decoded. If these locations are accessed and the
local bus timer is enabled, the cycle times out and is terminated by
a TEA signal.
6. The SRAM has optional battery backup on the MVME177.
The following table focuses on the Local I/O Devices portion of the
local bus Main Memory Map.
Table 3-2. Local I/O Devices Memory Map
Address Range Devices Accessed Port Size Size Notes
$FFF00000 - $FFF3FFFF Reserved -- 256KB 5
$FFF40000 - $FFF400FF VMEchip2 (LCSR) D32 256B 1,4
$FFF40100 - $FFF401FF VMEchip2 (GCSR) D32-D8 256B 1,4
$FFF40200 - $FFF40FFF Reserved -- 3.5KB 5,7
$FFF41000 - $FFF41FFF Reserved -- 4KB 5
$FFF42000 - $FFF42FFF PCCchip2 D32-D8 4KB 1
$FFF43000 - $FFF430FF MCECC #1 D8 256B 1
$FFF43100 - $FFF431FF MCECC #2 D8 256B 1
$FFF43200 - $FFF43FFF MCECCs (repeated) -- 3.5KB 1,7
$FFF44000 - $FFF44FFF Reserved -- 4KB 5
$FFF45000 - $FFF451FF CD2401 (Serial Comm. Cont.) D16-D8 512B 1,9
$FFF45200 - $FFF45DFF Reserved -- 3KB 7,9
$FFF45E00 - $FFF45FFF Reserved -- 512B 1,9
$FFF46000 - $FFF46FFF 82596CA (LAN) D32 4KB 1,8
$FFF47000 - $FFF47FFF 53C710 (SCSI) D32/D8 4KB 1
$FFF48000 - $FFF4FFFF Reserved -- 32KB 5
$FFF50000 - $FFF6FFFF Reserved -- 128KB 5
$FFF70000 - $FFF76FFF Reserved -- 28KB 6