user manual

MVME177 Functional Description

4-7

The EPROMs/Flashes are mapped to local bus address 0 following

a local bus reset. This allows the MC68060 to access the reset vector

and execution address following a reset. The EPROMs are

controlled by the VMEchip2. The following items are all

programmable:

❏ Map decoder

❏ Access time

❏ Time they appear at address 0

For more detail, refer to the VMEchip2 in the Single Board Computers

Programmer's Reference Guide.

SRAM

The boards include 128KB of 32-bit wide static RAM arrays that are

not parity protected and support:

❏ 8 bit

❏ 16 bit, and

❏ 32 bit wide accesses

The SRAM allows the debugger to operate and limited diagnostics

to be executed without the DRAM mezzanine. The SRAM will not

support burst cycles. The SRAM is controlled by the VMEchip2,

and the access time is programmable. Refer to the VMEchip2 in the

Single Board Computers Programmer's Reference Guide for more detail.

The boards are populated with 100 ns SRAMs.

SRAM battery backup is optionally available on the MVME177. The

battery backup function is provided by a Dallas DS1210S. Only one

backup power source is supported on the MVME177. The battery

supplies VCC to the SRAMs when main power is removed.

Each time the MVME177 is powered up, the DS1210S checks the

power source. If the voltage of the backup source is less than two

volts, the second memory cycle is blocked. This allows software to