MPU-1 INTRODUCTION The Motorola M6800 Microcomputer System of standard LSI (Large Scale Integration) devices permits the systems designer to configure and connect a total system with a minimum amount of time and effort. The MC6800 Microprocessing Unit (MPU) forms the nucleus of the system.
MPU-2 Microprocessing Unit (MC6800) The nucleus of the M6800 Microcomputer Family is the microprocessing unit (MPU). The MPU is enclosed in a 40 pin package as shown below: Features included in the MPU are: 1. Two accumulators (ACCA and ACCB) 2. One index register (X) 3. One program counter register (PC) 4.
MPU-3 5. One condition code register (CC) 6. 72 instructions 7. Five addressing modes 8. System clock range of 100 kilohertz to 1 megahertz 9. Program interrupt capability Accumulators The MPU contains 2 accumulators designated ACCA and ACCB. Each accumulator is 8 bits (one byte) long and is used to hold operands and data from the arithmetic logic unit.
MPU-4 INC – Increment LDA - Load accumulator LSR - Logical shift right NEA - Negate ORA - Inclusive OR PSH - Push data onto stack PUL - Pull data from stack ROL - Rotate left ROR - Rotate right RTI - Return from interrupt SBA - Subtract accumulators SBC - Subtract with carry STA - Store accumulator SUB - Subtract SWI - Software interrupt TAB - Transfer from accumulator A to accumulator B TAP - Transfer from accumulator A to processor condition codes register TBA - Transfe
MPU-5 CPX - Compare index register DEX - Decrement index register INX - Increment index register LDX - Load index register RTI - Return from interrupt STX - Store index register SWI - Software interrupt TSX - Transfer stack pointer to index register TXS - Transfer index register to stack pointer WAI - Wait for interrupt Program Counter The program counter (PC) is a 16 bit register that contains the address of the next byte to be fetched from memory.
MPU-6 Stack Pointer Address-5 : Contents of ACCB Stack Pointer Address-6 : Contents of CC After the status of each register is stored on the stack, the Stack Pointer will be decremented. When the stack is unloaded (status of registers restored), the status of the last register on the stack will be the first register that is restored. Condition Code Register (CC) The condition code register is an 8 bit register. Each individual bit may get set or get cleared from execution of an instruction.
MPU-7 Carry-Borrow: For addition, the carry-borrow condition code (C) in the zero bit position, represents a carry. This bit gets set (C=1) to indicate a carry, and is reset (C=0) if there is no carry. For subtraction, the C bit is set (C=1) to indicate a borrow and is reset (C=0) to indicate there was no borrow.
MPU-8 MPU Signal Descriptions 1. READ/WRITE (R/W): This output line is used to signal all devices external to the MPU that the MPU is in a read state (R/W = High) or a write state (R/W = Low). The normal standby state of this line when no external devices are being accessed is a high state. This line is three-state. When three-state goes high, this line enters the high impedance mode. 2.
MPU-9 Counter, Accumulators, and Condition Code Register are stored away on the stack. Next the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts may occur. At the end of the cycle, a 16-bit address will be loaded that points to a vectoring address which is located in memory locations n-6 and n-7 where n is the highest ROM address. An address loaded at these locations causes the MPU to branch to an interrupt routine in memory. 5.
MPU-10 Request signal, the processor will complete the current instruction that is being executed before it recognizes the NMI signal. The interrupt mask bit in the Condition Code Register has no effect on NMI. The Index Register, Program Counter, Accumulators, and Condition Code Register are stored away on the stack. At the end of the cycle, a 16-bit address will be loaded that points to a vectoring address which is located in memory locations n-2 and n-3.
MPU-11 available. This will occur if the GO/HALT line is in the Halt (low) mode or the 14PU is in a "Wait" state as the result of some instruction, such as the WAI instruction. 10. THREE-STATE CONTROL: (TSC) This input causes all of the address lines and the Read/Write line to go into the off or high impedance state. The Valid Memory address and Bus Available signals will be forced low. The data bus is not affected by TSC and has its own enable (Data Bus Enable).
MPU-12 Microprocessor Instruction Set -- Alphabetic Sequence ABA ADC ADD AND ASL ASR Add Accumulators Add with Carry Add Logical And Arithmetic Shift Left Arithmetic Shift Right INS INX Increment Stack Pointer Increment Index Register JMP JSR LDA LDS LDX LSR Jump Jump to Subroutine Load Accumulator Load Stack Pointer Load Index Register Logical Shift Right BCC BCS BEQ BGE BGT BHI BIT BLE BLS BLT BMI BNE BPL BRA BSR BVC BVS Branch if Carry Clear Branch if Carry Set Branch if Equal to Zero Branch if G
MPU-13 Hardware Interrupts What happens when the MPU gets a hardware interrupt? After it has been determined that the interrupt is not non-maskable, the MPU checks the status of the mask bit (bit 4 of the condition code register).
MPU-14
MPU-15 SUMMARY OF MPU OPERATION The MPU requires a two phase symmetrical, TTL compatible, nonoverlapping clock. During the first phase of the clock (Ø l high) an address will be placed on the address bus by the MPU. During the second phase of the clock (Ø2 high), the bidirectional data bus will be active. The first byte of an instruction enters the MPU and is transferred into an internal instruction register and decoded by the MPU.
MPU-16 RESET SEQUENCE 1. While HALT is high, RESET goes low for at least eight cycles of Øl, Ø2 during which all internal registers are cleared and interrupt bit (I) in CC is set. 2. Data at FFFE loads into PCH. 3. Data at FFFF loads into PCL. 4. PC contents go out on ADRS bus during Øl. 5. Contents of cell addressed enters instruction register during and is decoded as first instruction. 6. If two or more byte instruction, additional bytes enter MPU for execution. If not, go to next step. 7.
MPU-17 IRQ SEQUENCE 1. If bit "I" in condition code register is not set (I = 0) and IRQ goes low for at least one Ø 2 cycle, the IRQ sequence will be entered. 2. After completion of the current instruction, internal registers PC, X, A, B and CC will be stored in RAM at the address indicated by the stack pointer in descending locations (7 bytes in all). 3. The IRQ mask (bit I = 1) is set. 4. Data at FFF8 gets loaded into PCH. 5. Data at FFF9 gets loaded into PCL. 6.
MPU-18 NMI SEQUENCE 1. If NMI goes low for at least one Ø 2 cycle, the MPU will wait for completion of current instruction. 2. The internal registers PC, X, A, B and CC will then be stored in RAM at the address indicated by the stack pointer in descending locations (7 bytes in all). 3. The IRQ (bit I = 1) mask is set. 4. Data at FFFC is loaded into PCH. 5. Data at FFFD is loaded into PCL. 6. PC contents go out on ADRS bus during Ø1. 7.
MPU-19 SWI INSTRUCTION 1. Contents of the MPU registers PC, 1X, ACCA, ACCB and CC are stored in RAM at the address indicated by the stack pointer in descending location (7 bytes in all). 2. The IRQ mask (bit I = 1) is set. 3. Data at FFFA gets loaded into PCH. 4. Data at FFFB gets loaded into PCL. 5. PC contents go out on address bus during Ø 1. 6. Contents of cell addressed enters instruction register during Ø2 and is decoded as first instruction of SWI subroutine. 7.
MPU-20 Number Systems Everyone is quite familiar with the base 10 number system i.e. 0, 1, 2, 3, 4, 5, 6, 7, 8, & 9, since this is the system we all use day to day. Let us review a typical number, say 2743, and see what it really means. The least significant digit (LSD) is 3 and the most significant digit (MSD) is 2. Since we are talking about a base 10 number, the number 2743 really is = 3x10 0 + 4x101 + 7x102 + 2x10 3 = 3x1 + 4x10 + 7x100 + 2x1000 = 3 + 40 + 700 + 2000 = 2743.
MPU-21 101111 2 = = = = lx20 + 1x2 1 + lx22 + lx2 3 + 0x24 + 1x2 5 1x1 + 1x2 + 1x4 + 1x8 + 0x16 + 1x32 1 + 2 + 4 + 8 + 0 + 32 4710 In general, converting from a number in any base to a number in base 10 is accomplished as follows: (A0 B0 + A 1 B1 + A 2 B2 + A 3 B3 + A 4 B4 -- -- -- -- An Bn) where B is the base of the number system and A is the particular digit in the original number corresponding to its position to the left of the decimal point. On the example just completed, (101111).
MPU-22 First lets prove that 75 8 & 111101 2 are really equal to 61 10. 758 = = = = 111101 2 = = = = 5x80+ 7x81 5x1 + 7x8 5 + 56 6110 1x20 + 0x2 1 + 1x22 + 1x2 3 + 1x24 + 1x2 5 1x1 + 0x2 + 1x4 + 1x8 + 1x16 + 1x32 1 + 0 + 4 + 8 + 16 + 32 6110 Notice that if we take the base 8 number of 75 and convert each digit to base 2, we have the same number as when we converted the base 10 number to base 2. i.e.
MPU-23 Therefore 75 8 - 111101 which is the same pattern of 1's & 0's as we got from converting from base 10 to base 2. What this really says that it is easier to convert any base 10 number to base 8 by continuous division, and then convert each digit of the base 8 number to base 2. Let's look at another example. Convert 183 10 to base 8 & to base 2.
MPU-24 2 2 1 2 R=1 2 0 1 R=1 2 3 6 R=0 2 1 3 R=1 2 0 1 R=1 2 3 7 R=1 2 1 3 R=1 2 0 1 R=1 6 7 102 1102 1112 therefore 28 = 102, 68 = 110 2, & 7 8 = 1112, and 2678 = 101101112 Digital computers are designed to use binary numbers in their working registers. The working registers vary in number of bits depending on the manufacturer. The Motorola M6800 micro-processor utilizes, in general, 8 bit words (or registers).
MPU-25 1478 = = = = 7x8 0 + 4x81 + 1x8 2 7x1 + 4x8 + 1x64 7 + 32 + 64 103 10 6716 = = = = 7x160 + 6x161 7x1 + 6x16 7 + 96 103 10 As you probably have wondered by now, how do we represent these hex (base 16) numbers above 9? Here is the base 16 number compared with its equivalent base 10 number.
MPU-26 To convert any base 10 number to hex (base 16) you may convert it to base 8 first, then represent the base 8 number with its binary representation. By taking the binary representation of the number and grouping the bits from right to left in groups of four which are then represented in hex per the above table. Or one may convert any base 10 number to hex by our continuous division rule as before. Lets convert 825 10 to hex.
MPU-27 82510 to octal 8 103 825 R=1 8 12 103 R=7 8 1 12 R=4 8 0 1 R=1 2 412 825 R=1 2 206 412 R=0 2 103 206 R=0 2 51 103 R=1 2 255 51 R=1 2 12 25 R=1 2 6 12 R=0 2 3 6 R=0 2 1 3 R=1 2 0 1 R=1 1471 8 82510 to binary 82510 = = = = = 14718 1x80 + 7x8 1 + 4x82 + 1x8 3 1x1 + 7x8 + 4x64 + 1x512 1 + 56 + 256 + 512 82510 1100111001 2
MPU-28 82510 = = = = = 1100111001 2 1x20 +Ox21 +0x22 +lx23 +1x24 +1x25 +0x26 +0x27 +lx2 8 +1x29 lxl +0x2 +0x4 +lx8 +1x16 +lx32 +0x64 +0x128 +1x256 +1x512 1 + 0 + 0 + 8 + 16 + 32 + 0 + 0 + 256 + 512 82510 Or taking 147l 8 and representing each digit by its binary representation, we get 1=001, 4=100, 7=111 & 1 = 001 which when put together equal 001100111001. Notice this is the same bit pattern as when we converted from base 10 to base 2.
MPU-29 Conversion Chart Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Octal 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 50 Hexadecimal 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 lA 1B 1C 1D lE 1F 20 21 22 23 24 25 26 27 28 Binary 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 10
