User manual
Table Of Contents
- COVER
- TABLE OF CONTENTS
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
- LIST OF FIGURES
- LIST OF TABLES
- Table 2-1. Debugger Address Parameter Format
- Table 2-2. CPU32Bug Exception Vectors
- Table 3-1. Debug Monitor Commands
- Table 4-1. CPU32Bug Assembler Addressing Modes
- Table 5-1. CPU32Bug System Call Routines
- Table 6-1. MCU CPU Diagnostic Tests
- Table 6-2. Memory Diagnostic Tests
- Table B-1. Self-Test Error Messages
- Table C-1. CPU32Bug Customization Area
- Table C-2. MCU SCI Communication Formats
- Table C-3. Rev. A Chip Selection Summary
- Table C-4. Rev. B Chip Selection Summary
- Table C-5. BCC Rev. C Chip Selection Summary
- Table C-6. PFB Rev. C Compatibility
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- 3.1 INTRODUCTION
- 3.2 BLOCK OF MEMORY COMPARE
- 3.3 BLOCK OF MEMORY FILL
- 3.4 BLOCK OF MEMORY MOVE
- 3.5 BREAKPOINT INSERT/DELETE
- 3.6 BLOCK OF MEMORY SEARCH
- 3.7 BLOCK OF MEMORY VERIFY
- 3.8 DATA CONVERSION
- 3.9 DUMP S-RECORDS
- 3.10 GO DIRECT (IGNORE BREAKPOINTS)
- 3.11 GO TO NEXT INSTRUCTION
- 3.12 GO EXECUTE USER PROGRAM
- 3.13 GO TO TEMPORARY BREAKPOINT
- 3.14 HELP
- 3.15 LOAD S-RECORDS FROM HOST
- 3.16 MACRO DEFINE/DISPLAY/DELETE
- 3.17 MACRO EDIT
- 3.18 MACRO EXPANSION LISTING ENABLE/DISABLE
- 3.19 MEMORY DISPLAY
- 3.20 MEMORY MODIFY
- 3.21 MEMORY SET
- 3.22 OFFSET REGISTERS DISPLAY/MODIFY
- 3.23 PRINTER ATTACH/DETACH
- 3.24 PORT FORMAT
- 3.25 REGISTER DISPLAY
- 3.26 COLD/WARM RESET
- 3.27 REGISTER MODIFY
- 3.28 REGISTER SET
- 3.29 SWITCH DIRECTORIES
- 3.30 TRACE
- 3.31 TRACE ON CHANGE OF CONTROL FLOW
- 3.32 TRANSPARENT MODE
- 3.33 TRACE TO TEMPORARY BREAKPOINT
- 3.34 VERIFY S-RECORDS AGAINST MEMORY
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- 5.1 INTRODUCTION
- 5.2 SYSTEM CALL ROUTINES
- 5.2.1 Calculate BCD Equivalent Specified Binary Number
- 5.2.2 Parse Value, Assign to Variable
- 5.2.3 Check for Break
- 5.2.4 Timer Delay Function
- 5.2.5 Unsigned 32 x 32 Bit Divide
- 5.2.6 Erase Line
- 5.2.7 Input Character Routine
- 5.2.8 Input Line Routine
- 5.2.9 Input Serial Port Status
- 5.2.10 Unsigned 32 x 32 Bit Multiply
- 5.2.11 Output Character Routine
- 5.2.12 Output String Using Pointers
- 5.2.13 Print Carriage Return and Line Feed
- 5.2.14 Read Line to Fixed-Length Buffer
- 5.2.15 Read String Into Variable-Length Buffer
- 5.2.16 Return to CPU32Bug
- 5.2.17 Send Break
- 5.2.18 Compare Two Strings
- 5.2.19 Timer Initialization
- 5.2.20 Read Timer
- 5.2.21 Start Timer at T=0
- 5.2.22 Output String with Data
- 5.2.23 Output String Using Character Count
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- 6.1 INTRODUCTION
- 6.2 DIAGNOSTIC MONITOR
- 6.2.1 Monitor Start-Up
- 6.2.2 Command Entry and Directories
- 6.2.3 Help (HE)
- 6.2.4 Self Test (ST)
- 6.2.5 Switch Directories (SD)
- 6.2.6 Loop-On-Error Mode (LE)
- 6.2.7 Stop-On-Error Mode (SE)
- 6.2.8 Loop-Continue Mode (LC)
- 6.2.9 Non-Verbose Mode (NV)
- 6.2.10 Display Error Counters (DE)
- 6.2.11 Clear (Zero) Error Counters (ZE)
- 6.2.12 Display Pass Count (DP)
- 6.2.13 Zero Pass Count (ZP)
- 6.3 UTILITIES
- 6.4 CPU TESTS FOR THE MCU
- 6.5 MEMORY TESTS (MT)
- 6.6 BUS ERROR TEST
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
TABLE OF CONTENTS
M68CPU32BUG/D REV 1 iv
CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
6.1 Introduction......................................................................................................................... 6-1
6.2 Diagnostic Monitor............................................................................................................. 6-1
6.2.1 Monitor Start-Up...................................................................................................... 6-1
6.2.2 Command Entry and Directories.............................................................................. 6-1
6.2.3 Help (HE) ................................................................................................................. 6-2
6.2.4 Self Test (ST) ........................................................................................................... 6-2
6.2.5 Switch Directories (SD) ........................................................................................... 6-2
6.2.6 Loop-On-Error Mode (LE)....................................................................................... 6-2
6.2.7 Stop-On-Error Mode (SE)........................................................................................ 6-3
6.2.8 Loop-Continue Mode (LC)....................................................................................... 6-3
6.2.9 Non-Verbose Mode (NV)......................................................................................... 6-3
6.2.10 Display Error Counters (DE).................................................................................... 6-3
6.2.11 Clear (Zero) Error Counters (ZE)............................................................................. 6-3
6.2.12 Display Pass Count (DP).......................................................................................... 6-3
6.2.13 Zero Pass Count (ZP) ............................................................................................... 6-4
6.3 Utilities ............................................................................................................................... 6-4
6.3.1 Write Loop ............................................................................................................... 6-4
6.3.2 Read Loop ................................................................................................................ 6-5
6.3.3 Write/Read Loop...................................................................................................... 6-5
6.4 CPU Tests For The MCU (CPU)........................................................................................ 6-6
6.4.1 Register Test (CPU A) ............................................................................................. 6-7
6.4.2 Instruction Test (CPU B).......................................................................................... 6-8
6.4.3 Address Mode Test (CPU C).................................................................................... 6-9
6.4.4 Exception Processing Test (CPU D) ...................................................................... 6-10
6.5 Memory Tests (MT).......................................................................................................... 6-11
6.5.1 Set Function Code (MT A)..................................................................................... 6-13
6.5.2 Set Start Address (MT B)....................................................................................... 6-14
6.5.3 Set Stop Address (MT C)....................................................................................... 6-15
6.5.4 Set Bus Data Width (MT D)................................................................................... 6-16
6.5.5 March Address Test (MT E)................................................................................... 6-17
6.5.6 Walk a Bit Test (MT F).......................................................................................... 6-18
6.5.7 Refresh Test (MT G).............................................................................................. 6-19
6.5.8 Random Byte Test (MT H)..................................................................................... 6-20
6.5.9 Program Test (MT I) .............................................................................................. 6-21
6.5.10 Test and Set Test (MT J)........................................................................................ 6-22
6.6 Bus Error Test (BERR)..................................................................................................... 6-23
TABLE OF CONTENTS
M68CPU32BUG/D REV 1 v
APPENDIX A S-RECORD INFORMATION
A.1 Introduction.........................................................................................................................A-1
A.2 S-Record Content................................................................................................................A-1
A.3 S-Record Types...................................................................................................................A-2
A.4 S-Records Creation.............................................................................................................A-3
APPENDIX B SELF-TEST ERROR MESSAGES
B.1 Introduction.........................................................................................................................B-1
APPENDIX C USER CUSTOMIZATION
C.1 Introduction.........................................................................................................................C-1
C.2 CPU32BUG Customization................................................................................................C-2
C.3 Customization Table...........................................................................................................C-5
C.4 Communication Formats ..................................................................................................C-14
C.5 BCC REV. A Chip Selection Summary ...........................................................................C-15
C.6 BCC REV. B Chip Selection Summary............................................................................C-16
C.7 BCC REV. C Chip Selection Summary ...........................................................................C-17
C.8 Platform Board (PFB) REV. C Compatibility..................................................................C-18
C.9 CPU32BUG Questions and Answers ...............................................................................C-19
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Freescale Semiconductor, Inc.
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