Technical data

MOTOROLA MC68HC912B32
112 MC68HC912B32TS/D
Table 41 Multichannel Mode Result Register Assignment
S8CM CD CC CB CA Channel Signal
Result in ADRx
if MULT = 1
000
00 AN0 ADR0
0 1 AN1 ADR1
1 0 AN2 ADR2
1 1 AN3 ADR3
001
00 AN4 ADR0
0 1 AN5 ADR1
1 0 AN6 ADR2
1 1 AN7 ADR3
010
00 Reserved ADR0
0 1 Reserved ADR1
1 0 Reserved ADR2
1 1 Reserved ADR3
011
00V
RH
ADR0
0 1
V
RL
ADR1
1 0
(V
RH
+ V
RL
)/2 ADR2
1 1 TEST/Reserved ADR3
10
000 AN0 ADR0
0 0 1 AN1 ADR1
0 1 0 AN2 ADR2
0 1 1 AN3 ADR3
1 0 0 AN4 ADR4
1 0 1 AN5 ADR5
1 1 0 AN6 ADR6
1 1 1 AN7 ADR7
11
000 Reserved ADR0
0 0 1 Reserved ADR1
0 1 0 Reserved ADR2
0 1 1 Reserved ADR3
1
0 0V
RH
ADR4
1 0 1
V
RL
ADR5
1 1 0
(V
RH
+ V
RL
)/2 ADR6
1 1 1 TEST/Reserved ADR7
Shaded bits are “don’t care” if MULT = 1 and the entire block of four or eight
channels make up a conversion sequence. When MULT = 0, all four bits
(CD, CC, CB, and CA) must be specified and a conversion sequence con-
sists of four or eight consecutive conversions of the single specified chan-
nel.