AR Y The MC68328 DragonBall microprocessor is designed to save you time, power, cost, board space, pin count, and programming steps when designing your product. This functionality on a different microprocessor could require 20 separate components, each with 16-64 separate pins. Most of these components require interconnects, which may be duplicates.
Freescale Semiconductor, Inc. Introduction • System Integration Module Supports Glueless System Design 1 INTRODUCTION ❏ System Configuration and Programmable Address Mapping ❏ Memory Interface for SRAM, EPROM, and Flash Memory • Sixteen Programmable Peripheral Chip-Selects with Wait-State Generation Logic ❏ PCMCIA 1.
Freescale Semiconductor, Inc. Introduction ❏ External POCSAG Decoder (Slave) Support ❏ Digitizer For A/D Input or FLEX Pager (Master) Support INTRODUCTION • IEEE 1149.1 Boundary Scan Test Access Port (JTAG) • Operation From DC To 16.67MHz (Processor Clock) • Operating Voltage of 3.3V ± 0.3V Y AR IN IM PR EL Freescale Semiconductor, Inc... 1 • Compact 144-Lead Thin-Quad-Flat-Pack (TQFP) Packaging MOTOROLA MC68328 USER’S MANUAL 11/6/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. SECTION 2 SIGNALS IM IN MOTOROLA MC68328 USER’S MANUAL 11/6/97 For More Information On This Product, Go to: www.freescale.com SIGNAL DESCRIPTIONS 2 AR Y The DragonBall uses a standard M68000 bus for communication between both on-chip and external peripherals with optional address extension to A31. This single continuous bus exists both on the and off the chip.
Freescale Semiconductor, Inc. Signals 2.1 SIGNAL DESCRIPTIONS The DragonBall signals are grouped as shown in Table 2-1. Table 2-1.
Freescale Semiconductor, Inc. Signals 2.1.1 Power Pins The MC68328 processor has 20 power supply pins. Users should be careful to reduce noise, potential crosstalk, and RF radiation from the output drivers. Inputs may be +5 V or +3.3V when VDD = +3.3V or +5V respectively without damaging the device.
Freescale Semiconductor, Inc. Signals 2.1.3 System Control Pins 2.1.4 Address Bus Pins AR These are the address lines driven by the 68EC000 core or by the LCD controller for panel refresh DMA. The chip-select module can decode the entire 4 Gbyte address map. In many applications, only the lower portion of the address lines will be used, reserving any unused address pins for parallel I/O functions. IN A15—A0 These address output lines are not multiplexed with any other I/O signals.
Freescale Semiconductor, Inc. Signals PB7–PB0/D7–D0 This bus is the lower data byte or general-purpose I/O. In pure 8-bit systems, this bus can serve as a general-purpose I/O. The WDTH8 bit in the system control register ($FFF000) should be set to one (1) by software before the port can be used. In 16-bit or mixed 8-/16bit systems, these pins must function as the lower data byte. AS—ADDRESS STROBE This active-low output signal indicates that a valid address is present on the address bus.
Freescale Semiconductor, Inc. Signals 2.1.7 Interrupt Control Pins AR IN PM5-PM2/IRQ1, IRQ2, IRQ3, IRQ6 These pins can be programmed to either parallel I/O PM2-PM5 or interrupt input. When they function as interrupt inputs, they can be programmed to be edge or level triggered with either high or low polarity. IRQ6 generates a level 6 interrupt. IRQ3, IRQ2, and IRQ1 generate level 3, 2 and 1 interrupts respectively. 2.1.
Freescale Semiconductor, Inc. Signals PK7-PK6/CE1-CE2 These pins can be programmed as either parallel I/O port K7-6 or the PCMCIA 1.0 chipenable signals. When programmed as the PCMCIA chip-enables, CE1 and CE2 are activelow, card-enable signals driven by the MC68328 processor; CE1 enables even bytes; CE2 enables odd bytes. CE1 and CE2 are decoded for assertion by CSD3. PK0/SPMTXD—MASTER SPI TRANSMIT DATA, PORT K 0 This pin is the master SPI shift register output.
Freescale Semiconductor, Inc. Signals IN AR PM1/RTS—REQUEST TO SEND, PORT M 1 This pin serves two purposes. Normally, the receiver indicates that it is ready to receive data by asserting this pin (low). This pin would be connected to the far-end transmitter’s CTS pin. When the receiver detects a pending overrun, it negates this pin. For other applications, this pin can be a general-purpose output controlled by the bit in the receiver register. When it is programmed as parallel I/O, it becomes PM1.
Freescale Semiconductor, Inc. Signals PG3/TOUT2 —TIMER 2 OUTPUT, PORT G 3 This bidirectional signal can be programmed to toggle or generate a pulse of one system clock duration when timer/counter channel 2 reaches a reference value. By default after reset, this pin becomes general-purpose input, PG3. 2.1.15 Real-Time Clock Pins 2.1.16 LCD Controller Pins IN AR PG7/RTCO—REAL-TIME CLOCK OUTPUT/INPUT, PORT G 7 While PC0/MOCLK is high, this pin is a dedicated input that provides the 32.768 kHz or 38.
Freescale Semiconductor, Inc. Signals LCLK—SHIFT CLOCK This is the clock output to which the output data to the LCD panel is synchronized. LCLK can be programmed to be inverted. LACD—ALTERNATE CRYSTAL DIRECTION This output is toggled to alternate the crystal polarization on the panel and is used to protect the crystal from DC voltages. This signal can be programmed to toggle at a period from 1 to 16 frames.
Freescale Semiconductor, Inc. Signals 2.
Freescale Semiconductor, Inc. Signals 0.20 (0.008) H L– M N 0.20 (0.008) H L– M N 144 109 P L, M, N 108 1 CL G DETAIL "A" DETAIL "B" Y F 2 J B1 V1 DETAIL "A" BASE METAL 73 36 72 37 A1 S1 IN IM C θ2 PR EL H C2 S θ R2 R1 0.25 (0.010) GAGE PLANE K E C1 Y DETAIL "C" Z θ1 2. 3. 4. 5. 6. DETAIL "C" 7. ∩ 0.08 (0.003) T SEATING PLANE DETAIL "B" 0.05 (0.005) (ROTATED 90°) 144 PL 0.08(0.003) M T L – M 1. A S AA D AR SIGNAL DESCRIPTIONS Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. Y To improve total system throughput and reduce component count, board size, and cost of system implementation, the DragonBall combines a powerful MC68EC000 processor with intelligent peripheral modules and a typical system interface logic.
Freescale Semiconductor, Inc. Architecture PARALLEL I/O PORTS PULSE-WIDTH MODULATOR EC000 STATIC CORE Y BUS SIZING EXTENSION MC68EC000 INTERNAL BUS REAL-TIME CLOCK PCMCIA SUPPORT INTERRUPT CONTROLLER MASTER SERIAL PERIPHERAL INTERFACE SLAVE SERIAL PERIPHERAL INTERFACE UART WITH INFRA-RED SUPPORT PARALLEL I/O PORTS IM IN LCD CONTROLLER AR CLOCK SYNTHESIZER AND POWER CONTROL Figure 3-1.
Freescale Semiconductor, Inc. Architecture 3.1.1 Core Programming Model The core has 32-bit registers and a 32-bit program counter (see Figure 3-2). The first eight registers (D7–D0) are data registers that are used for byte (8-bit), word (16-bit), and long-word (32-bit) operations. When using the data registers to manipulate data, they affect the status register (SR). The next seven registers (A6–A0) and the user stack pointer (USP) can function as software stack pointers and base address registers.
Freescale Semiconductor, Inc. Architecture 3.1.2 Data and Address Mode Types ADDRESS MODE TYPES Bits Register direct Binary-coded decimal digits Register indirect Bytes Absolute Words Program counter relative Long words Immediate Y DATA TYPES AR Implied Table 3-1. Address Modes ADDRESS MODE IM Absolute data address Absolute short Absolute long SYNTAX Dn An IN Register direct address Data register direct Address register direct xxx.W xxx.
Freescale Semiconductor, Inc. Architecture 3.1.3 Instruction Set The EC000 core instruction set supports high-level languages that facilitate programming. Almost every instruction operates on bytes, words, and long-words, and most of them can use any of the 14 address modes. By combining instruction types, data types, and address modes, you can have access to over 1,000 instructions.
Freescale Semiconductor, Inc. Architecture Table 3-2.
Freescale Semiconductor, Inc. Architecture 3.3 PLL CLOCK SYNTHESIZER AND POWER CONTROL Y You can save power on the DragonBall by turning off peripherals that are not being used, reducing processor clock speed, or disabling the processor altogether. An interrupt at the interrupt controller logic that runs during low-power mode allows you to wake up from this mode. Programmable interrupt sources cause the system to wake up.
Freescale Semiconductor, Inc. Architecture 3.7 LCD CONTROLLER The LCD controller is used to display data on an LCD module. It fetches display data from memory and provides control signals, frame line pulse, clocks, and data to the LCD module. It supports monochrome STN LCD modules with a maximum of four grayscale levels with frame rate control. System RAM can be used as display memory and DMA frees the CPU from panel refresh responsibilities.
Freescale Semiconductor, Inc. Architecture 3.10 PROGRAMMER’S MEMORY MAP The memory map is a guide to all on-chip resources. Use the following table as a guide when configuring your chip. The base address used in the table is 0xFFFFF000 and 0xFFF000 from reset. If a double-mapped bit is cleared in the system control register, then the base address is 0xFFFFF000. Unpredictable results occur if you write to any 4K register space not documented in the table.
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Freescale Semiconductor, Inc. SECTION 4 SYSTEM CONTROL • Address space of the internal peripheral registers AR • Bus timeout control and status (bus-error generator) Y • Access permission from the internal peripheral registers 4.1 OPERATION IM IN The on-chip resources use a reserved 4,096-byte block of address space for their registers. This block is double-mapped to two locations—0xFFFFF000 (24-bit) and 0xFFF000 (32-bit) —at reset.
Freescale Semiconductor, Inc. System Control 4.1.1 System Control Register The 8-bit read/write system control register (SCR) resides at 0xFFF000 or 0xFFFFF000 after reset. The SCR cannot be accessed in user data space if the SO bit is set to 1. Writing a 1 to the status bits in this register clears them, but writing a 0 has no effect.
Freescale Semiconductor, Inc. System Control SO—Supervisor Only This control bit limits on-chip registers to supervisor accesses only. 0 = User and supervisor mode. 1 = Supervisor-only mode. DMAP—Double Map This control bit controls the double-mapping function. Y Bit 1—Reserved This bit is reserved and reads 0. AR WDTH8—8-Bit Width Select This control bit allows the D[7:0] pins to be used for port B input/output. EL IM IN 0 = Not an 8-bit system. 1 = 8-bit system.
Freescale Semiconductor, Inc. Y PR EL IM IN AR MODULE Freescale Semiconductor, Inc... System Control 4 SYSTEM CONTROL 4-4 MC68328 USER’S MANUAL 12/9/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. IN AR Y The DragonBall microprocessor contains 16 general-purpose, programmable, chip-select signals, which are arranged in four groups of four. Among them, there are two special-purpose chip-select signals—CSA0 and CSD3. The CSA0 signal is special in that it is also a boot device chip-select. From reset, all the addresses are mapped to CSA0 until group-base address A is programmed and the V bit is set.
Freescale Semiconductor, Inc. Chip-Select Logic GROUP BASE REGISTER COMPARE LOGIC COMPARE LOGIC CHIP-SELECT MASK REGISTER GROUP MASK REGISTER CSA CSB CSC CSD DTACK Y CSA0 CSA1 CSA2 CSA3 CSA0 CSA1 CSA2 CSA3 CSA3 AR MODULE IN DTACK GENERATION IM CSD3 COMPARE LOGIC CE1 CE2 OE WE PCMCIA V1.0 Figure 5-1. Chip-Select Operation 5.1 CHIP-SELECT OPERATION A chip-select output signal is asserted when an address is matched and after the AS signal goes low.
Freescale Semiconductor, Inc. Chip-Select Logic Y Each chip-select can be configured to address an 8- or 16-bit space. You can mix 16- and 8-bit contiguous address memory devices on a 16-bit data bus system. If the core performs a 16-bit data transfer in an 8-bit memory space, then two 8-bit cycles will occur. However, the address and data strobes remain asserted until the end of the second 8-bit cycle.
Freescale Semiconductor, Inc. Chip-Select Logic 5.2 PROGRAMMING MODEL The chip-select module of the DragonBall microprocessor contains registers that you can use to control external devices, such as memory. Chip-selects do not operate until the register in a particular group of devices is initialized and the V bit is set in the corresponding group-base address register. The only exception is the CSA0 signal, which is the boot device chip-select.
Freescale Semiconductor, Inc. Chip-Select Logic 5.2.2 Group Base Address Mask Registers The group base address mask registers (GRPMASKA–GRPMASKD) define the address comparison range for a group of devices. When the bits in this register are set to 1 the bits in the corresponding address lines (A[31:20]) compare true (“don’t care”).
Freescale Semiconductor, Inc. Chip-Select Logic 5.2.3 Chip-Select Option Registers There are four 32-bit chip-select option registers (CSA0–3 and CSB0–3) in each chip-select group, one for each chip-select signal. Chip-selects in group A and B decode address lines A[23:16] for a minimum 64K space. Chip-selects in group C and D decode address lines A[23:12] for a minimum 4K space. When a group address match and a chip-select option address match occurs, a chip-select is generated.
Freescale Semiconductor, Inc. Chip-Select Logic Bits 7–4—Reserved These bits are reserved and should be set to 0. RO—Read-Only This bit configures the memory space selected by this chip-select as read-only. Otherwise, read or write accesses are allowed. However, writes to read-only space cause a write-protection violation to occur, as described in Section 4.1.1 System Control Register.
Freescale Semiconductor, Inc. Chip-Select Logic BUSW—Bus Width This bit sets the bus width of the memory space selected by this chip-select. 0 = 8-bit. 1 = 16-bit. Y 0 = For a match to occur, the address line must match the corresponding bit in the CSCx or CSDx register. 1 = The corresponding address line compares true (“don’t care”). RO—Read-Only This bit configures the memory space selected by this chip-select as read-only. Otherwise, read or write accesses are allowed.
Freescale Semiconductor, Inc. Chip-Select Logic 5.3 PCMCIA 1.0 SUPPORT The Dragonball supports PCMCIA 1.0 memory card chip-selects and read/write signals. To meet the fanout requirement, use external buffers to interface to the memory card. The PCMCIA address range is decoded with CSD3. CE1 CE2 OE WE AR Y ADDRESS DATA CONTROL PCMCIA SIGNAL DECODE 5.3.1 PCMCIA Configuration IN Figure 5-2. PCMCIA Block Diagram EL CHIP-SELECT LOGIC IM The DragonBall can access PCMCIA 1.
Freescale Semiconductor, Inc. Y PR CHIP-SELECT LOGIC EL 5 IM IN AR MODULE Freescale Semiconductor, Inc... Chip-Select Logic 5-10 MC68328 USER’S MANUAL 12/9/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. Y The interrupt controller supports a variety of interrupts from internal and external sources. This block prioritizes and encodes pending interrupts and generates interrupt vector numbers during the interrupt acknowledge cycle. INTERRUPT CONTROLLER ................ AR INTERRUPTS INTERRUPT PENDING REGISTER IN ................ IM PRIORITY ENCODER IACK VECTOR DECODE IPL[0:2] EL VECTOR GENERATOR 6 INTERRUPT MASK REGISTER Figure 6-1.
Freescale Semiconductor, Inc. Interrupt Controller • Watchdog timer interrupt (level 4) • Real-time clock interrupt (level 4) • Keyboard interrupt (level 4) • PWM interrupt (level 4) • General-purpose interrupt INT[0:7] (level 4) • IRQ3 external interrupt (level 3) • IRQ2 external interrupt (level 2) AR 6.1 EXCEPTION VECTORS IM IN A vector number is an 8-bit number that can be multiplied by 4 to obtain the address of an exception vector.
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Freescale Semiconductor, Inc. Interrupt Controller 6.2 RESET Y AR IN Note: The DragonBall does not support the reset instruction. It will not cause a reset exception or an assertion of the RESET pin. IM RESET is an input-only pin on the DragonBall. For more information about core interrupts, see the Motorola application note called A Discussion of Interrupts for the MC68000 (part number AN1012). 6.
Freescale Semiconductor, Inc. Interrupt Controller handler. The interrupt service routine should end with the rte instruction, which restores the processing state prior to the interrupt. IM Table 6-2. Interrupt Vector Numbers VECTOR NUMBER Level 7 xxxxx111 Level 6 xxxxx110 EL INTERRUPT Level 5 xxxxx101 Level 4 xxxxx100 Level 3 xxxxx011 Level 2 xxxxx010 Level 1 xxxxx001 NOTE: xxxxx is replaced by the upper five bits of the interrupt vector register. 6.
Freescale Semiconductor, Inc. Interrupt Controller 6.5.1 Interrupt Vector Register IVR 7 6 5 4 R/W R/W 3 2 1 0 0 0 0 R R R AR VECTOR 0x00 ADDR 0x(FF)FFF300 IN RESET VECTOR— This field is the upper five bits of the interrupt vector number. IM 0 These lower three bits are always set to 0. EL 6.5.2 Interrupt Control Register The interrupt control register (ICR) controls the behavior of the external interrupt inputs.
Freescale Semiconductor, Inc. Interrupt Controller level low. Positive polarity means that an interrupt occurs when the signal goes from logic level low to logic level high. IM IN 0 = Negative polarity (default at reset). 1 = Positive polarity. EL POL6—Polarity 6 This bit controls interrupt polarity for IRQ6. In level-sensitive mode, negative polarity means that an interrupt occurs when the signal is at logic level low.
Freescale Semiconductor, Inc. Interrupt Controller this bit is low, IRQ1 is a level-sensitive interrupt. In this case, you must clear the external source of the interrupt. 0 = Level-sensitive interrupt (default at reset). 1 = Edge-sensitive interrupt. IN AR ET3—IRQ3 Edge Trigger Select When this bit is set, the IRQ3 signal is an edge-triggered interrupt. In edge-triggered mode, you must write a 1 to the IRQ3 bit in the interrupt status register to clear this interrupt.
Freescale Semiconductor, Inc. Interrupt Controller to the CPU, but its status can still be observed in the interrupt pending register. At reset, all the interrupts are masked and all the bits in this register are set to 1.
Freescale Semiconductor, Inc. Interrupt Controller MINT0—Mask External INT0 interrupt 0 = Enable INT0 interrupt. 1 = Mask INT0 interrupt (default at reset). IM IN MINT5—Mask External INT5 interrupt 0 = Enable INT5 interrupt. 1 = Mask INT5 interrupt (default at reset). AR MINT4—Mask External INT4 interrupt 0 = Enable INT4 interrupt. 1 = Mask INT4 interrupt (default at reset). EL MINT6—Mask External INT6 interrupt 0 = Enable INT6 interrupt. 1 = Mask INT6 interrupt (default at reset).
Freescale Semiconductor, Inc. Interrupt Controller MIRQ6—Mask IRQ6 Interrupt 0 = Enable IRQ6 interrupt. 1 = Mask IRQ6 interrupt (default value at reset). MSPIS—Mask Serial Peripheral Interface (SPI) Slave Interrupt 0 = Enable SPI slave interrupt. 1 = Mask SPI slave interrupt (default value at reset). IN IM 0 = Enable IRQ7 interrupt. 1 = Mask IRQ7 interrupt. 6.5.
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Freescale Semiconductor, Inc. Interrupt Controller INT0—Wake-up External INT0 0 = Disallow INT0 interrupt from waking up the processor. 1 = Enable INT0 interrupt to wake up the processor (default at reset). INT2—Wake-up External INT2 0 = Disallow INT2 interrupt from waking up the processor. 1 = Enable INT2 interrupt to wake up the processor (default at reset). AR Y INT3—Wake-up External INT3 0 = Disallow INT3 interrupt from waking up the processor.
Freescale Semiconductor, Inc. Interrupt Controller IRQ6—Wake-up IRQ6 Interrupt 0 = Disallow IRQ6 interrupt from waking up the processor. 1 = Enable IRQ6 interrupt to wake up the processor (default at reset). SPIS—Wake-up Serial Peripheral Interface (SPI) Slave Interrupt 0 = Disallow SPI slave interrupt from waking up the processor. 1 = Enable SPI slave interrupt to wake up the processor (default at reset). Y AR 6.5.
Freescale Semiconductor, Inc. Interrupt Controller TIMER2—Timer 2 Interrupt Request This bit indicates that a timer 2 event has occurred. This is a level 4 interrupt. See Section 8 Timers for more information about timer operation. 0 = No timer 2 event occurred. 1 = Timer 2 event has occurred. INTERRUPT CONTROLLER 0 = No watchdog timer interrupt 1 = A watchdog timer interrupt is pending AR WDT—Watchdog Timer Interrupt Request This bit indicates that a watchdog timer interrupt is pending.
Freescale Semiconductor, Inc. Interrupt Controller INT2—External INT2 Interrupt 0 = No INT2 interrupt. 1 = INT2 interrupt is pending. INT4—External INT4 Interrupt 0 = No INT4 interrupt. 1 = INT4 interrupt is pending. Y AR IM INT7— External INT7 Interrupt 0 = No INT7 interrupt. 1 = INT7 interrupt is pending. IN INT6— External INT6 Interrupt 0 = No INT6 interrupt. 1 = INT6 interrupt is pending.
Freescale Semiconductor, Inc. Interrupt Controller If IRQ3 signal is set to be an edge-triggered interrupt, you must clear the interrupt by writing a 1 to this bit (writing a 0 has no effect). 0 = No level 3 interrupt is pending. 1 = Level 3 interrupt is pending. 6.5.6 Interrupt Pending Register 31 30 29 28 27 26 25 24 IM BIT FIELD RESERVED R/W — EL RESET 23 6 IPR IN The read-only interrupt pending register (IPR) indicates which interrupts are pending.
Freescale Semiconductor, Inc. Interrupt Controller TIMER2—Timer 2 Interrupt Request This bit indicates that a timer 2 event has occurred. This is a level 4 interrupt. See Section 8 Timers for more information about timer operation. 0 = No timer 2 event occurred. 1 = Timer 2 event has occurred. AR 0 = No watchdog timer interrupt 1 = A watchdog timer interrupt is pending IN RTC—Real-Time Clock Interrupt Request This bit indicates that the real-time clock is requesting an interrupt.
Freescale Semiconductor, Inc. Interrupt Controller INT2—External INT2 Interrupt 0 = No INT2 interrupt. 1 = INT2 interrupt is pending. INT4—External INT4 Interrupt 0 = No INT4 interrupt. 1 = INT4 interrupt is pending. 6 IM INT7— External INT7 Interrupt 0 = No INT7 interrupt. 1 = INT7 interrupt is pending. IN INT6— External INT6 Interrupt 0 = No INT6 interrupt. 1 = INT6 interrupt is pending. INTERRUPT CONTROLLER AR Y INT5—External INT5 Interrupt 0 = No INT5 interrupt.
Freescale Semiconductor, Inc. Interrupt Controller If IRQ3 signal is set to be an edge-triggered interrupt, you must clear the interrupt by writing a 1 to this bit (writing a 0 has no effect). 0 = No level 3 interrupt is pending. 1 = Level 3 interrupt is pending. PR EL IM IN AR INTERRUPT CONTROLLER MODULE Y 0 = No level 6 interrupt pending. 1 = Level 6 interrupt is posted. 6 Freescale Semiconductor, Inc...
Y The DragonBall microprocessor supports up to 10 parallel ports, that can be configured either as general-purpose input/output ports or as a dedicated peripheral interface. There are three types of ports—basic, pull-up, and interrupt. This section describes these ports and how to configure their functions. AR 7.
Freescale Semiconductor, Inc. Parallel Ports 7 DATA FROM MODULE PAD BUFFER 0 MPU BUS OUTPUT ENABLE FROM MODULE PAD SEL 0 1 SEL IN DIRECTION 1 AR DATA Y DATA TO MODULE SELECT IM Figure 7-1. Basic Port Operation 7.1.
Freescale Semiconductor, Inc. Parallel Ports PULL-UP DATA TO MODULE IN DATA FROM MODULE 0 DATA IM MPU BUS OUTPUT ENABLE FROM MODULE AR Y 0 1 PAD SEL SEL EL DIRECTION 1 PAD BUFFER SELECT Figure 7-2. Pull-Up Port Operation MOTOROLA MC68328 USER’S MANUAL 12/9/97 For More Information On This Product, Go to: www.freescale.com 7-3 7 The pull-up ports (E, F, G, K, and M) operate just like the basic ports, except they have some additional pull-up resistors to be configured.
Freescale Semiconductor, Inc. Parallel Ports 7.3 INTERRUPT PORT 7 PARALLEL PORTS The interrupt port (port D) is a basic port and a pull-up port, except it has additional interrupt capabilities. Figure 7-3 illustrates the internal logic of the interrupt port. PULL-UP MPU BUS IRQ EDGE SEL0 1 EDGE DETECT Y POLARITY IRQ EN PAD BUFFER DATA DIRECTION AR BIT IRQ PAD IN Figure 7-3. Interrupt Port Operation IM Port D does not share its port pins with other peripheral modules.
Freescale Semiconductor, Inc. Parallel Ports At reset, or when the RESET signal is asserted, the DragonBall ports default to their reset configurations. You should examine the default value for each port carefully and, if necessary, reconfigure the port according to the requirements of your application. Table 7-1 contains the default port configurations.
Freescale Semiconductor, Inc. Parallel Ports Table 7-1.
Freescale Semiconductor, Inc. Parallel Ports Table 7-1.
Freescale Semiconductor, Inc. Parallel Ports AR Y SEL—Select 0–7 The select register allows you to individually select the function for each port pin. When you set a bit in this register, the corresponding port pin is configured as a general-purpose I/O. When a bit is clear, the corresponding port pin is configured as an address line A[16:23]. At reset, all bits in the select register are cleared. 7.5.2 Port B Registers BIT FIELD 15 14 13 12 IM IN Port B is multiplexed with data lines D7-D0.
Freescale Semiconductor, Inc. Parallel Ports SEL—Select 0–7 These bits select whether the data bus D0-D7 or general-purpose I/O signals are connected to the pins. When a bit is high, the corresponding port pin is configured as a general-purpose I/O and when they are low port B is a lower-byte data bus. 7 7.5.
Freescale Semiconductor, Inc. Parallel Ports AR Y SEL—Select 0–7 The select register allows you to individually select the function for each port pin. When you set a bit in this register, the corresponding port pin is configured as a general-purpose I/O. When a bit is clear, the corresponding port pin is configured as a bus control signal. At reset, all bits in the select register are cleared. 7.5.4 Port D Registers IM IN Port D has special features that allow it to be used as a keyboard input port.
Freescale Semiconductor, Inc. BIT 15 14 13 12 11 10 9 8 7 FIELD POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0 6 5 4 3 2 1 0 IQEN7 IQEN6 IQEN5 IQEN4 IQEN3 IQEN2 IQEN1 IQEN0 ADDR 0xFFFFF41C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD 0 0 0 0 0 0 0 0 IQEG7 IQEG6 IQEG5 IQEG4 IQEG3 IQEG2 IQEG1 IQEG0 0x0000 ADDR 0xFFFFF41E AR RESET Y BIT IN DIR—Direction 0–7 These bits control the direction of the corresponding port pin.
Freescale Semiconductor, Inc. Parallel Ports 7.5.5 Port E Registers Y Port E is multiplexed with seven chip-select signals that are described in the table below. BIT PORT FUNCTION 0 none 1 Bit 1 AR Table 7-3. Port E Bit Functions OTHER FUNCTION none IN CSA1 2 Bit 2 CSA2 Bit 3 CSA3 Bit 4 CSB0 5 Bit 5 CSB1 6 Bit 6 CSB2 7 Bit 7 CSB3 3 IM 4 EL Freescale Semiconductor, Inc... PARALLEL PORTS IQEG—Edge Enable 0–7 These bits, when high, enable edge-triggered interrupts.
Freescale Semiconductor, Inc. AR Y PU—Pull-Up 0–7 These bits enable the pull-up resistors on the port. When high, the pull-up resistors are enabled and when they are low they are disabled. The port E Bit 7 pull-up resistor is enabled after reset. IN SEL—Select 0–7 The select register allows you to individually select the function for each port pin. When you set a bit in this register, the corresponding port pin is configured as a general-purpose I/O.
Freescale Semiconductor, Inc. Parallel Ports AR Y SEL—Select 0–7 The select register allows you to individually select the function for each port pin. When you set a bit in this register, the corresponding port pin is configured as a general-purpose I/O. When a bit is cleared, the corresponding port pin is configured as an address line. 7.5.7 Port G Registers IM IN Port G is multiplexed with timer and serial communication signals.
Freescale Semiconductor, Inc. Parallel Ports BIT 14 13 12 11 10 9 ADDR 8 7 5 4 3 2 1 0 6 5 4 3 2 1 0 0xFFFFF430 BIT 15 14 13 12 11 10 9 FIELD PU7 PU6 PU5 PU4 PU3 PU2 PU1 8 7 PU0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 RESET 0xFFFF ADDR 0xFFFFF432 AR Y DIR—Direction 0–7 These bits control the direction of the corresponding port pin. When a bit is high, the corresponding port pin is an output pin and when it is low the corresponding port pin is an input pin.
Freescale Semiconductor, Inc. Parallel Ports 7.5.8 Port J Registers PORT FUNCTION OTHER FUNCTION 0 Bit 0 CSC0 1 Bit 1 CSC1 2 Bit 2 CSC2 3 Bit 3 CSC3 4 Bit 4 CSD0 5 Bit 5 CSD1 6 Bit 6 7 Bit 7 AR Y BIT CSD2 CSD3 As with other ports, each bit can be individually configured for use as general-purpose IO or chip-selects.
Freescale Semiconductor, Inc. Parallel Ports 7 the pin. Notice that the actual value on the pin is reported when a pin is read. At reset, all data bits default to 0. PARALLEL PORTS SEL—Select 0–7 The select register allows you to individually select the function for each port pin. When you set a bit in this register, the corresponding port pin is configured as a general-purpose I/O. When a bit is cleared, the corresponding port pin is configured as a chip-select. Table 7-6.
Freescale Semiconductor, Inc. Parallel Ports Y AR PU—Pull-Up 0–7 These bits enable the pull-up resistors on the port. When high, the pull-up resistors are enabled and when they are low they are disabled. IN SEL—Select 0–7 The select register allows you to individually select the function for each port pin. When you set a bit in this register, the corresponding port pin is configured as a general-purpose I/O. When a bit is clear, the corresponding port pin is configured as a peripheral interface.
Freescale Semiconductor, Inc. Parallel Ports 7 14 13 12 11 10 9 8 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 6 5 4 3 2 1 0 RESET 0x0000 ADDR 0xFFFFF448 BIT 15 14 13 12 11 10 9 FIELD PU7 PU6 PU5 PU4 PU3 PU2 PU1 8 7 PU0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 0xFF02 ADDR 0xFFFFF44A AR RESET IN DIR—Direction 0–7 These bits control the direction of the corresponding port pin.
Freescale Semiconductor, Inc. Parallel Ports 7 Y AR IN IM EL PR Freescale Semiconductor, Inc... PARALLEL PORTS 7-20 MC68328 USER’S MANUAL 12/9/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. Y The DragonBall liquid crystal display controller provides display data for an external LCD driver or LCD panel module.
Freescale Semiconductor, Inc. LCD Controller PIXCLK CLOCK (SLOW) DMA CLOCK (FAST) ADDRESS DATA LCD DRIVER LCD DRIVER LCDC BR BG SIM28 SCREEN DMA OE CURSOR LOGIC IN CS FRAME RATE CONTROL Y MPU INTERFACE REGISTERS AR 68EC000 CORE LINE BUFFER IM SYSTEM MEMORY Figure 8-1. LCD Controller Block Diagram EL 8.1.1 MPU Interface The MPU interface consists of control registers that enable you to operate different features of the LCD controller.
Freescale Semiconductor, Inc. LCD Controller 8.1.3 Line Buffer The line buffer collects display data from system memory during DMA cycles and outputs it to the cursor control logic. The input is synchronized with the fast DMA clock and the output is synchronized to the relatively slow LCD pixel clock (PIXCLK). Y When enabled, the cursor control logic generates a block-shaped cursor on the display screen. You can adjust the cursor height and width anywhere between 1 and 31 pixel counts.
Freescale Semiconductor, Inc. LCD Controller Y The LCD’s DMA controller is a fly-by 16-bit wide, fast-data transfer machine. The LCD screen has to be refreshed continuously at a rate of approximately 50-70Hz, which means the image data in memory is periodically read and transferred to the corresponding pixels on the screen. The refresh is divided into small bursts of 8- or 16-word reads. When the internal line buffer needs data, it asserts the BR signal to request the bus from the core.
Freescale Semiconductor, Inc. LCD Controller Y One clock cycle is added to the first data transfer of the DMA to allow for chip-select access time. For example, if the number of clock cycles selected for each DMA data word transfer is two, the first data word would transfer in three clocks. Subsequent data word transfers occur in two clock cycles to the end of the DMA burst.
Freescale Semiconductor, Inc. LCD Controller 8.2.2 Interfacing the LCD Controller with an LCD Panel With the following signals, you can interface the LCD controller to an LCD panel. AR Y The LCD data bus uses LD0 to display pixel 0, 0. Some LCD panel manufacturers specify their LCD panel data bus in which data bit 3 of the panel displays pixel 0,0.
Freescale Semiconductor, Inc. LCD Controller toggle on every frame. The LACD output signal is synchronized with the trailing or falling edge of the line pulse (LP) enclosed by FLM. NUMBER OF FRAMES 0000 1 0001 2 0010 3 0100 5 1000 9 . . . . . . AR 1111 Y LACDRC 16 8.2.3 LCD Panel Interface Timing IM IN The LCD controller continuously transfers pixel data into the LCD panel via the LCD data bus. The LCD bus is timed by the LSCLK, LLP, and LFLM signals.
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. LCD Controller 8.2.4 DISPLAY CONTROL AR Y 8.2.4.1 LCD SCREEN FORMAT. The LCD panel’s screen width and height can be programmed in the software. Figure 8-5 illustrates the relationship between part of a large graphics file displayed on screen versus the actual page in pixel counts.
Freescale Semiconductor, Inc. LCD Controller Y To define the position of the hardware cursor, the LCD controller maintains a vertical line counter (YCNT) to keep track of the pixel’s current vertical position. YCNT in conjunction with the horizontal pixel counter (XCNT) specifies the screen position of the current pixel data that is being processed.
Freescale Semiconductor, Inc. LCD Controller LCD DRIVERS (2,0) (X-1,0) AR Y LCD DRIVERS (1,0) (0,Y-1) (1,Y-1) (2,Y-1) (X-1,Y-1) 2-BIT PER PIXEL MODE 5 . . . . . . . . . . . . . . . . 4 3 . . . . . . . . . . . . . . . . . 2 1 . . . . . . . . . . . . . . . . . .0 (1,0) (2,0) (3,0) IN 7 .............................
Freescale Semiconductor, Inc. LCD Controller DPRAM_BASE = (IMMR & 0xFFFF0000) + 0x2000 0K ERAM = 01 BD / DATA /µCODE DPRAM_BASE = (IMMR & 0xFFFF0000) + 0x2200 ERAM = 10 BD / DATA / µCODE 1K BD / DATA / µCODE DPRAM_BASE = (IMMR & 0xFFFF0000) + 0x2800 BD / DATA 3K AR Y 2K DPRAM_BASE = (IMMR & 0xFFFF0000) + 0x2E00 IN BD / DATA / µCODE DPRAM_BASE = (IMMR & 0xFFFF0000) + 0x3000 EL 5K IM 4K LCD CONTROLLER PR 6K 8 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. LCD Controller Y The LCD controller is configured to only drive non-split monochrome LCD panels. It cannot handle color STN or TFT panels. However, grayscale generation can be selected by setting the GS bit in the LCD panel interface configuration (LPICF) register. In grayscale mode, the number of data words for displaying the gray levels increases as opposed to black and white mode. Also, the line buffer must be filled before the next line is displayed.
Freescale Semiconductor, Inc. LCD Controller Table 8-3. Gray Palette Selection DENSITY 000 0 001 1/4 010 5/16 1/2 100 11/16 101 3/4 110 1 8.2.9 Low-Power Mode AR 011 Y GRAY CODE 111 1 IM IN When the LCDON bit of the LCKCON register is set to 0, the LCD controller enters a low-power mode by stopping the pixel clock before the next line-buffer-fill DMA. In this mode, there can be no additional screen DMA and display refresh operations.
Freescale Semiconductor, Inc. LCD Controller 8.3 SYSTEM MEMORY CONTROL REGISTERS 8.3.
Freescale Semiconductor, Inc. LCD Controller 8.4 SCREEN FORMAT REGISTERS 8.4.1 LCD Screen Width Register Th LCD screen width register (LXMAX) specifies the width of the LCD panel in pixels. On a line, pixels are numbered 0 to LXMAX for a screen width of LXMAX +1 pixels. LXMAX+1 must be a multiple of 16.
Freescale Semiconductor, Inc. LCD Controller 8.5 CURSOR CONTROL REGISTERS 8.5.1 LCD Cursor X Position Register The LCD cursor X position (LCXP) register is used to configure the horizontal position of the cursor. 15 14 13 12 11 FIELD CC1 CC0 — R/W R/W R/W R/W 10 9 8 7 6 5 4 3 2 1 0 CXP9 CXP8 CXP7 CXP6 CXP5 CXP4 CXP3 CXP2 CXP1 CXP0 R/W R/W R/W 0x0000 ADDR 0x(FF)FFFA18 R/W R/W R/W R/W R/W R/W AR RESET R/W Y BIT IN CC—Cursor Control 00 = Transparent.
Freescale Semiconductor, Inc. LCD Controller 8.5.3 LCD Cursor Width and Height Register The LCD cursor width and height (LCWCH) register is used to configure the width and height of the cursor.
Freescale Semiconductor, Inc. LCD Controller BD—Blink Divisor 0–6 These bits indicate when the cursor will toggle once per specified number of internal frame pulses plus one. The half-period can be as long as two seconds. 8.6 LCD PANEL INTERFACE REGISTERS 8.6.1 LCD Panel Interface Configuration Register 7 6 5 FIELD — R/W RW/ 4 3 2 1 0 PBSIZ1 PBSIZ0 GS R/W R/W R/W AR BIT Y LPICF 0x00 ADDR 0x(FF)FFFA20 IN RESET 1-bit. 2-bit. 4-bit. Unused.
Freescale Semiconductor, Inc. LCD Controller 8.6.2 LCD Polarity Configuration Register The LCD polarity configuration (LPOLCF) register is used to configure the polarity of the panel interface signals and the data bus. LPOLCF 7 6 5 4 3 2 1 0 — LCKPOL FLMPOL LPPOL PIXPOL R/W R/W R/W R/W R/W R/W RESET 0x00 ADDR 0x(FF)FFFA21 IN FLMPOL—First Line Marker Polarity This bit indicates the first-line marker polarity. AR 0 = Active negative edge of LCLK. 1 = Active positive edge of LCLK.
Freescale Semiconductor, Inc. LCD Controller programmed plus one. The default value will toggle the LACD signal on each new frame, which is required by many LCD panel manufacturers. LACD is also referred to as the M signal by some LCD panel manufacturers. LACDRC 7 6 5 FIELD — R/W R/W 4 3 2 1 0 ACD3 ACD2 ACD1 ACD0 R/W R/W R/W R/W 0x00 ADDR 0x(FF)FFFA23 Y RESET AR ACD—Alternate Crystal Direction Control 0–3 This bit represents the LACD toggle rate control code. 8.
Freescale Semiconductor, Inc. LCD Controller 8.7.2 LCD Clocking Control Register The LCD clocking control (LCKCON) register is used to configure the length of a DMA burst, the number of clock cycles per DMA word access, the size of the external bus interface, and the pixel clock divider source. You can also use it to turn on the LCD controller.
Freescale Semiconductor, Inc. LCD Controller DWIDTH—Data Width This bit displays memory data width that indicates the size of the external bus interface. 0 = 16-bit memory. 1 = 8-bit memory. Y Note: The PCDS bit requires an LCD controller off/on sequence before any changes will occur. AR 8.7.3 LCD Last Buffer Address Register The LCD last buffer address (LLBAR) register is used to configure the number of memory words required to fill one line on the LCD panel.
Freescale Semiconductor, Inc. LCD Controller 8.7.4 LCD Octet Terminal Count Register The LCD octet terminal count register (LOTCR) is used to confure the time interval from the end of the current line to the beginning of the next line on the LCD display.
Freescale Semiconductor, Inc. LCD Controller POS—Pixel Offset Code 0–2 These bits specify which of the eight pixels in the first or second (GS = 0, BOS = 1 only) octet retrieved from the line buffer is the first to be displayed on the screen. 000 implies that pixel 7, the first shifted out, will be the first to be displayed on every horizontal line in the current frame. 8.
Freescale Semiconductor, Inc. LCD Controller 2-BIT GRAYSCALE VALUE IN MEMORY LEVEL LOG GRAY LEVEL LINEAR GRAY LEVEL (11) 3 111 (1) 111 (1) (10) 2 011 (3/4) 100 (11/16) (01) 1 001 (1/4) 010 (5/16) (00) 0 000 (0) 000 (0) Y 8.9 CALCULATING BANDWIDTH 8.9.1 Bus Overhead Considerations AR The LCD’s DMA controller consumes bus bandwidth by periodically accessing memory. This is an important consideration for the high-performance handheld system designer.
Freescale Semiconductor, Inc. LCD Controller Thus, the percentage of host bus time taken up by the LCDC DMA is PDMA, EL IM IN AR Y (EQ 3) 8 LCD CONTROLLER PR Freescale Semiconductor, Inc... 4.8`µs P DMA = ------------------69.4`µs = 6.92% MOTOROLA MC68328 USER’S MANUAL 12/9/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. Y AR IN IM EL LCD CONTROLLER PR 8 Freescale Semiconductor, Inc... LCD Controller 8-28 MC68328 USER’S MANUAL 12/9/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. SECTION 9 REAL-TIME CLOCK AR The following list summarizes the features of the real-time clock: Y 9.1 FEATURES • Full clock features—seconds, minutes, and hours • Minute countdown timer with interrupt • Programmable alarm with interrupt • 32.768kHz or 38.4kHz operation IN • Once-per-second, once-per-minute, and once-per-day interrupts 1 PPS RTC_CLKO RTC_IRQB INTERRUPT CONTROL 1 PPH 1 PPM MINUTE SECOND HOUR 9 PRESCALER EL 32.768KHZ 38.
Freescale Semiconductor, Inc. Real-Time Clock 9.2 OPERATION 9.2.1 Prescaler and Counter Y 9.2.2 Alarm IN 9.2.3 Minute Stopwatch AR You can set an alarm interrupt by setting the HOURS, MINUTES, and SECONDS fields in the RTC alarm (RTCALRM) register. An interrupt is enabled when the ALMEN bit in the RTC interrupt enable register (RTCIENR) is set. An interrupt is posted when the current time matches the time in the RTCALRM register. 9.
Freescale Semiconductor, Inc. Real-Time Clock The real-time clock may be in the process of updating the hours, minutes, or seconds data, so the data value may be incorrect if a read and an update occur at the same time. When reading this register, you should make two reads and compare the results. If the reads do not compare, make another read and use the new value. The following code fragment illustrates the preferred method. Hours, minutes, and seconds values are returned in the CPU’s D0 register.
Freescale Semiconductor, Inc. Real-Time Clock 9.3.2 RTC Alarm Register The real-time clock alarm (ALARM) register specifies the exact time that the real-time clock will generate an alarm interrupt to the processor. The HOURS, MINUTES, and SECONDS fields of this register can be read or written at any time. After a write, the alarm timer assumes the new values. Unused bits read 0.
Freescale Semiconductor, Inc. Real-Time Clock 9.3.3 RTC Control Register The real-time clock control (CTL) register has two configurable bits that enable or disable real-time clock operation and select the frequency for the reference crystal clock. CTL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 FIELD — ENABLE — 38.4 RESERVED R/W R/W R/W R/W R/W R/W 0x0000 ADDR 0x(FF)FFFB0C 0 Y RESET AR ENABLE—RTC Enable 1 = Enable real-time clock. 0 = Disable the real-time clock interrupts.
Freescale Semiconductor, Inc. Real-Time Clock 1Hz FLAG—1Hz Flag When the 1Hz interrupt is enabled, this bit is set every second and an interrupt is generated to the processor. 1 = A 1Hz interrupt occurs. 0 = No 1Hz interrupt occurs. Y 1 = A 24-hour rollover interrupt occurs. 0 = No 24-hour rollover interrupt occurs. IN 1 = An alarm interrupt occurs. 0 = No alarm interrupt occurs.
Freescale Semiconductor, Inc. Real-Time Clock 9.3.5 RTC Interrupt Enable Register The real-time clock interrupt enable register (IENR) allows you to individually enable different real-time clock interrupts. The real-time clock provides five interrupts—a 1 second interrupt, 1 minute interrupt, 1 day (at midnight) interrupt, alarm interrupt, and a stopwatch interrupt. At reset, all RTC interrupts are disabled.
Freescale Semiconductor, Inc. Real-Time Clock SWEN—Stopwatch Interrupt Enable This bit enables the stopwatch interrupt. 1 = A stopwatch interrupt is enabled. 0 = A stopwatch interrupt is disabled. Y 9.3.6 RTC STOPWATCH REGISTER STPWCH 15 14 13 12 11 FIELD — R/W R/W 10 8 7 6 5 4 3 2 1 0 STOPWATCH COUNT R/W 0x0000 ADDR 0x(FF)FFFB12 EL STOPWATCH COUNT This field contains the stopwatch countdown value, which can be a maximum of 62 minutes.
Freescale Semiconductor, Inc. SECTION 10 TIMERS Y CLOCK GENERATOR PRESCALAR REGISTER IN EVENT REGISTER COMPARE REGISTER IM COUNTER REGISTER TIMERS DIV 16 MPU BUS TOUT 10 PRESCALER CONTROL REGISTER CAPTURE REGISTER SYSTEM CLOCK 32K HZ CLOCK TIN INTERRUPT AR TIMER CLOCK CAPTURE DETECT EL Figure 10-1. General-Purpose Timer Block Diagram 10.
Freescale Semiconductor, Inc. Timers WATCHDOG TIMER COMPARE REGISTER INTERRUPT RESET COMPARATOR 16-BIT COUNTER 4KHZ CLOCK PRESCALER 32KHZ CLOCK TIMERS Y 10 AR Figure 10-2. Software Watchdog Timer Block Diagram 10.2 GENERAL-PURPOSE TIMER OPERATION IM IN The clock input to the prescaler can be selected from the system clock (divided by 1 or 16), the corresponding timer input (TIN1 or TIN2) pin, or the 32kHz (or 38kHz) reference clock.
Freescale Semiconductor, Inc. Timers 10.3 SOFTWARE WATCHDOG TIMER OPERATION IN 10 AR The software watchdog timer uses the 32kHz clock as the input to its prescaler module. The prescaler circuitry divides the clock input by a fixed value of eight. The output of this prescaler circuitry is connected to the input of a 16-bit counter. The reference/compare register is a 16-bit programmable register that can be programmed with a maximum value of 65535 (or 0xFFFF in hex).
Freescale Semiconductor, Inc. Timers 10.5 PROGRAMMING THE GENERAL-PURPOSE TIMERS 10.5.1 Timer Unit 1 and 2 Control Registers You can use the timer unit 1 and 2 control registers (TCTL1 and TCTL2) to configure the overall operation of the timers.
Freescale Semiconductor, Inc. Timers CLKSOURCE—Clock Source This field controls the clock source to the timer. The stop-count mode freezes the timer without causing the value in the counter to be reset to 0x0000. Stop count (clock disabled). System clock to timer. System clock divided by 16. TIN pin is the clock source. 32kHz or 38kHz clock. Y TEN—Timer Enable This bit enables the timer module. AR 0 = Timer disabled. 1 = Timer enabled.
Freescale Semiconductor, Inc. Timers 10.5.3 Timer Unit 1 and 2 Compare Registers The timer unit 1 and 2 compare (TCMP1 and TCMP2) registers are used as a reference value, so that when the timer counter matches its value with these registers, a compare event occurs. These registers are set to all ones at system reset.
Freescale Semiconductor, Inc. Timers 10.5.5 Timer Unit 1 and 2 Counter Registers The timer unit 1 and 2 counter (TCN1 and TCN2) registers are 16-bit read-only registers. You can read them anytime without disturbing the current count. TCN1 AND TCN2 13 12 11 10 9 8 7 FIELD COUNT R/W R 6 5 4 0x0000 ADDR 0x(FF)FFF608 OR (TIMER 1) AND 0x(FF)FFF614 (TIMER 2) 2 1 0 Y RESET 3 AR COUNT This field represents the current count value. 10.5.
Freescale Semiconductor, Inc. Timers 10.6 PROGRAMMING THE SOFTWARE WATCHDOG TIMER The software watchdog timer has a watchdog compare register, a watchdog counter register, and a watchdog control and status register. 10.6.1 Watchdog Compare Register The 16-bit watchdog compare register (WRR) contains the reference value so that when there is a match between this value and the value in the watchdog counter, the watchdog timer times out. This value resets to 0xFFFF.
Freescale Semiconductor, Inc. Timers 10.6.3 Watchdog Control and Status Register The watchdog control and status register (WCSR) consists of three control or status bits. At power-up or reset, the watchdog timer is enabled. WCSR BIT 15 14 13 12 11 10 FIELD 9 8 7 6 5 4 — ADDR 0x(FF)FFF618 1 0 WRST FI WDEN R/W R/W R/W Y RESET 0x0001 2 TIMERS IM IN FI—Forced Interrupt This bit selects whether an interrupt or a software reset will occur when the watchdog timer times out.
Freescale Semiconductor, Inc. PR EL IM IN AR TIMERS Y 10 Freescale Semiconductor, Inc... Timers 10-10 MC68328 USER’S MANUAL 12/9/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 11.1 FEATURES UART AR Y The universal asynchronous receiver/transmitter (UART) allows serial communication with external devices, such as modems and other computers. Data is transported in character blocks at data rates ranging from 300bps to over 500Kbps using a standard “start-stop” format.
Freescale Semiconductor, Inc. RECEIVER TRANSMITTER SERIAL INTERFACE TX FIFO RXD TXD GPIO CTS RTS AR UART Y BAUD GEN BA 11 Figure 11-1. UART Block Diagram 11.2 SERIAL INTERFACE SIGNALS IN There are five UART signals that you can access. If you need any or all of the UART signals, the appropriate port bits can be programmed to assume their UART function. Refer to Section 7 Parallel Ports for information about programming the ports.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter • RTS—The request-to-send pin is an output that serves two purposes. Normally, the receiver indicates that it is ready to receive data by asserting this pin (low). This pin would be connected to the far-end transmitter’s CTS pin. When the receiver detects a pending overrun, it negates this pin. For other applications, this pin can serve as a general-purpose output controlled by the RTS bit in the UART receiver register.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter AR 11.3.1 Transmitter IM IN The transmitter accepts a character (a byte) from the MPU bus and transmits it serially. While the FIFO is empty, the transmitter outputs continuous idle (1 in NRZ mode and 0 in infra-red mode). When a character is available for transmission, the START, STOP, and PARITY (if enabled) bits are added to the character and it is serially shifted at the selected bit rate.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter 11.3.2 Receiver IM IN EL When the infra-red mode is enabled, the receiver expects narrow pulses for each 0 bit received; otherwise, normal NRZ is expected. An infra-red transceiver, external to the DragonBall microprocessor, transforms the infra-red signal into an electrical signal. MOTOROLA MC68328 USER’S MANUAL 12/9/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter 11.3.3 Baud Rate Generator The baud generator provides the bit clocks to the transmitter and receiver blocks. It consists of a prescaler and a 2n divider. The baud rate generator master clock source can either be the system clock (SYSCLK) or it can be provided by the GPIO pin (input mode). By setting the BAUD SOURCE bit in the UART baud control register to 1, an external clock can directly drive the baud rate generator.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter 11.3.4 MPU Interface The MPU interface includes all status and control registers and all miscellaneous logic. This block directly connects to the internal 68000 bus and provides address decode for three address lines and a full 16-bit read/write port. The interrupt line is the logical-OR of the eight interrupt sources.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter TX EN—Transmitter Enable This bit enables the transmitter block. When this bit is low, the transmitter is disabled and the transmit FIFO is flushed. This bit resets to 0. AR 0 = 16x clock mode. 1 = 1x clock mode. PAR EN—Parity Enable This bit controls the parity generator in the transmitter and parity checker in the receiver. When this bit is high, they are enabled and when it is low, they are disabled. IN 0 = Parity disabled.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter GPIO DELTA EN—General-Purpose I/O Delta Enable This bit enables an interrupt when the GPIO pin (while configured as an input) changes state. The current state of the GPIO pin is read in the UART baud control register. 0 = GPIO interrupt disabled. 1 = GPIO interrupt enabled. 11 IN 0 = RX full interrupt disabled. 1 = RX full interrupt enabled.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter TX HALF EN—Transmitter Half Enable When this bit is high, it enables an interrupt when the transmit FIFO is less than half full. When it is low, the TX half interrupt is disabled. This bit resets to 0. 0 = TX half interrupt disabled. 1 = TX half interrupt enabled. 0 = TX avail interrupt disabled. 1 = TX avail interrupt enabled. PR EL IM IN AR UART Y 11 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter 11.4.2 UART Baud Control Register The UART baud control (UBAUD) register controls the operation of the baud-rate generator and the GPIO pin. It resets to 0x003F.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter GPIO—GPIO Status/Control If GPIO is configured as an input, this bit indicates the current state of the GPIO pin. If GPIO is configured as an output, this bit controls the state of the pin. 0 = GPIO pin is low. 1 = GPIO pin is high. AR GPIO SRC—GPIO Source This bit controls the source of the GPIO pin. When high, the source is the 1x clock from the baud rate generator. When low, the source is the GPIO bit.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter 11.4.3 UART Receiver Register The UART receiver (URX) register contains the status of the receiver. The high byte of this register resets to 0x00. This register contains random data until the first character is received. The CHARACTER STATUS field is updated and valid with each data character. Status and data must be read as a 16-bit word.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter FRAME ERROR—Frame Error When high, this read-only bit indicates that the current character had a framing error (missing STOP bit), which indicates the possibility of corrupted data. This bit is updated for each character read from the FIFO. Y BREAK—Break When high, this read-only bit indicates that the current character was detected as a break. The DATA bits are all 0 and the STOP bit was also 0.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter FIFO HALF—FIFO Half This read-only bit indicates that the transmit FIFO is less than half full. 0 = Transmitter FIFO more than half full. 1 = Transmitter FIFO less than half full. TX AVAIL—Transmit FIFO Available This bit indicates that the transmit FIFO has at least one slot available for data.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter TX DATA—Transmit Data This field is the parallel transmit data inputs. While in 7-bit mode, D7 is ignored. While in 8-bit mode, all bits are used. Data is transmitted LSB first. A new character is transmitted when these bits are written. These bits are read as 0. 11.4.
Freescale Semiconductor, Inc. Universal Asynchronous Receiver/Transmitter RTS CONT—RTS Control This bit selects the function of the RTS pin. 0 = RTS pin is controlled by the RTS bit. 1 = RTS pin is controlled by the receiver FIFO. When the FIFO is full (one slot remaining) RTS is negated. 0 = Normal NRZ operation. 1 = Infra-red operation. IN LOOP IR—Loopback Mode for Infra-Red This bit controls a loopback from transmitter to receiver in the infrared interface. This bit is provided for system testing.
Freescale Semiconductor, Inc. PR EL IM IN AR UART Y 11 Freescale Semiconductor, Inc... Universal Asynchronous Receiver/Transmitter 11-18 MC68328 USER’S MANUAL 12/9/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. AR Y The serial peripheral interface (SPI) is a high-speed synchronous serial port for communicating to external devices such as A/D converters and nonvolatile RAMs. The interface is a 3- or 4-wire system, depending on unidirectional or bidirectional communication mode. The SPIM provides the clock for data transfer and can only function as a master device. It is upward-compatible with SPIs that are popular on Motorola’s 6805 microcomputer chips.
Freescale Semiconductor, Inc. (POL=1, PHA=1) SPMCLK (POL=1, PHA=0) SPMCLK (POL=0, PHA=1) SPMCLK (POL=0, PHA=0) SPMCLK Bn Bn-1 Bn-2 Bn-3 ... ... B1 B0 SPMRXD Bn Bn-1 Bn-2 Bn-3 ... ... B1 B0 AR Y SPMTXD Figure 12-2. Master SPI Operation 12.1 OPERATION 12.1.
Freescale Semiconductor, Inc. Serial Peripheral Interface—Master 12.1.2 Phase/Polarity Configurations The SPIM transfers data in and out of the shift register with the SPICLK. Data is clocked using any one of the variations of clock phase and clock polarity. The clocked transfer may be programmed in phase and in polarity (Figure 12-2). In phase 0 operation, output data changes on falling clock edges, while input data is shifted on rising edges.
Freescale Semiconductor, Inc. Serial Peripheral Interface—Master Y 000 = Divide by 4 001 = Divide by 8 010 = Divide by 16 011 = Divide by 32 100 = Divide by 64 101 = Divide by 128 110 = Divide by 256 111 = Divide by 512 AR SPIMEN—SPI Master Enable This bit enables the SPIM. The enable should be asserted before initiating an exchange and should be negated after the exchange is complete. This bit must be set before data can be written into the SPIM data register.
Freescale Semiconductor, Inc. Serial Peripheral Interface—Master IRQEN—Interrupt Request Enable This bit will enable the SPIM interrupt. This bit is cleared to 0 on reset and must be enabled by software. 0 = Interrupts disabled 1 = Interrupts enabled Y 0 = Normal phase 1 = Shift advance to opposite phase AR POL—Polarity This bit controls the SPMCLK polarity.
Freescale Semiconductor, Inc. Y The slave serial peripheral interface (SPI) operates as an externally clocked slave, allowing the MC68328 processor to interface with external master devices (for example, FLEX™ paging decoder). The interface is a 3-wire system consisting of the clock, enable, and data input pins. It is compatible with SPIs that are popular on Motorola’s 68HC05 microcomputer chips. IN AR The SPI transfers data to the MC68328 processor from a peripheral device over a serial link.
Freescale Semiconductor, Inc. Serial Peripheral Interface—Slave 13.1 OPERATION Y The clock input performs shifts depending on phase and polarity. In phase 0 mode(PHA=0), serial data are strobed on the leading edges of SPSCLK. In phase 1 mode(PHA=1), data are strobed in on trailing edges. The polarity (POL) specifies the inactive state value of SPSCLK. While POL=1, the idle state of the SPSCLK is high. While POL = 0, the idle state of the SPSCLK is low.
Freescale Semiconductor, Inc. Serial Peripheral Interface—Slave 13.3.1 SPI Slave Register This register controls the SPI operation and reports its status. The lower byte is the input data received from an external source. 15 14 13 12 11 10 9 8 SPIS IRQ IRQ EN EN POL DATA RDY OV WR PHA POL SPIS EN 7 6 5 4 3 1 0 DATA ADDRESS: $(FF)FFF700: RESET VALUE: $0000 AR Y SPISIRQ—Slave SPI Interrupt Request This interrupt-flag bit is asserted at the end of an 8-bit transfer.
Freescale Semiconductor, Inc. Serial Peripheral Interface—Slave PHA—Phase This bit sets the phase relationship between SPSCLK and SPSRxD. Refer to Figure 9-2. 0 = Phase 0 (normal); data is captured on the leading edge of SPSCLK 1 = Phase 1; data is captured on the trailing edge of SPSCLK POL—Polarity This bit controls the polarity of the SPSCLK. AR 1 = SPIS module enabled 0 = SPIS module disabled (default) Y SPISEN—Slave SPI Enable This status bit enables the slave SPI module.
Freescale Semiconductor, Inc. SYSCLK IN WIDTH COMPARE AR Y The pulse-width modulator (PWM) provides high-quality sound generation and accurate motor control. This section describes the PWM block. The PWM is a simple free-running counter with two “compare” registers that each perform a particular task when they match the count value. The period comparator sets the output signal and the free-running counter resets when its value matches the period value.
Freescale Semiconductor, Inc. Pulse-Width Modulator The width and period registers are double-buffered so that a new value can be loaded for the next cycle without disturbing the current cycle. At the beginning of each period, the contents of the buffer registers are loaded into the comparator for the next cycle. Sampled audio can be recreated by feeding a new sample value into the width register on each interrupt.
Freescale Semiconductor, Inc. Pulse-Width Modulator IRQEN—Interrupt Request Enable This bit controls the PWM interrupt. While this bit is low, the interrupt is disabled. 0 = PWM interrupt disabled 1 = PWM interrupt enabled Y PIN—Pin This bit indicates the current status of the PWM output pin and can change immediately after it is read, depending on the current state of the pin.
Freescale Semiconductor, Inc. Pulse-Width Modulator When this bit is set high, the PWM is enabled and begins a new period. The following actions occur: • The output pin changes state to start a new period. • The clock prescaler is released and begins counting. • The counter begins counting. • The comparators are enabled.
Freescale Semiconductor, Inc. Pulse-Width Modulator 14.1.4 Counter This read-only register is the current count value and can be read at any time without disturbing the counter. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COUNT RESET VALUE: 0000 PULSE-WIDTH MODULATOR IM IN AR Y COUNT—Count This is the current count value. MOTOROLA MC68328 USER’S MANUAL 11/10/97 For More Information On This Product, Go to: www.freescale.com 11 PR EL Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Y The phase-locked-loop (PLL) block generates all clocks for the MC68328 processor. It includes a crystal oscillator for use with low-frequency (32.768 kHz) crystals. The PLL generates a high-frequency master clock phase-locked to the crystal reference. IN AR The PLL is a flexible clock source for the MC68328. It provides a crystal-controlled master clock at frequencies from 13 MHz to the maximum operational frequency in 32 KHz steps.
Freescale Semiconductor, Inc. Phase-Locked Loop and Power Control 15.1.1 PLL Control Register This register (illustrated in Figure 3-2) controls the overall PLL operation. Several bits are provided for control of the dynamic performance of the PLL. Refer to Section 3.4.3 for operation details.
Freescale Semiconductor, Inc. Phase-Locked Loop and Power Control 15.1.2 Frequency Select Register This register (illustrated in Figure 3-3) controls the two dividers of the dual-modulus counter. One additional bit assists the software to protect the PLL from accidental writes that change the frequency. Another bit prepares for the VCO frequency change. While this register can be accessed as bytes, it should always be written as a 16-bit word.
Freescale Semiconductor, Inc. Phase-Locked Loop and Power Control 15.2.2 Divider Y Divisor = 14 (P + 1) + Q + 1 Where: 1 <= Q <= 14 P >= Q + 1 AR Below the value of 225, some divisors are not allowed as the P and Q relationships cannot be met. 15.2.3 Normal Startup To change the VCO frequency, use the sequence below. This fragment assumes all peripherals have been disabled and the CPU is operating at the highest possible frequency (SYSCLK SEL = 100).
Freescale Semiconductor, Inc. Phase-Locked Loop and Power Control ;interrupt service for Timer 2 occurs here move.w (SP)+,IMR ;restore the Interrupt Mask Register rts ;PLL is now at the new frequency ;The PLL has reacquired lock and SYSCLK is stable The master frequency should only be changed during an early phase of the boot-up sequence.
Freescale Semiconductor, Inc. Phase-Locked Loop and Power Control Y MPU BUS CPU BUS GRAN CLOCK CONTROL CLK68K DMA BUS GRANT Figure 15-2. Power Control Module PR EL PHASE-LOCKED LOOP AND POWER CONTROL DMA BUS REQUEST IM IN BURST WIDTH CONTROL WAKEUP SYSCLK AR MPU INTERFACE 3 Freescale Semiconductor, Inc... CPU BUS REQUE the screen refreshed. The following sections describe the use and operation of the power control block. 15.3.
Freescale Semiconductor, Inc. Phase-Locked Loop and Power Control controller always has priority, so if a DMA access is in progress, the CPU will wait until the DMA controller has completed its access before interrupt processing begins. Y 1 MSEC CPU ACTIVE WAKEUP EVENT CPU DOZE CPU ACTIVE IN CPU DOZE CPU ACTIVE CPU DOZE CPU ACTIVE CPUCLK AR SYSCLK One register is associated with the power control block. Figure 3-6 illustrates the bits in the power control register (PCTLR).
Freescale Semiconductor, Inc. Phase-Locked Loop and Power Control STOP This bit immediately enters the power-save mode without waiting for the power controller to cycle through a complete burst period. This bit disables the CPU clock after the bus cycle that follows the next CLK32 rising edge. When the system is to enter the doze mode, this bit is set. On the next burst period, or interrupt, the clock will restart for its allotted period. This bit is reset to zero and is cleared on wake-up events.
Freescale Semiconductor, Inc. Phase-Locked Loop and Power Control The CLKO pin is an external reference of the internal MC68EC000 clock. If the external system does not require CLKO, it can be disabled by clearing the CLKEN bit in the PLL control register further reducing the normal operation power consumption. AR Y Users can program the duty-cycle register (WIDTH bits) for burst-duty cycles of any value between 0/31 and 31/31.
Freescale Semiconductor, Inc. • 512K boot EPROM x 1 (8-bit interface) AR • M68328 16.58MHz (using 32.768kHz crystal) APPLICATIONS AND DESIGN EXAMPLES Y This section discusses the details of a simple M68328 processor base system, which will illustrate the simplicity of the system hardware design and glueless interface to various memory and peripheral devices when using the M68328 processor. The ability of a mixed 8-bit and 16-bit memory is also demonstrated.
Freescale Semiconductor, Inc. Applications and Design Examples A low boot bus width-select (BBUSW) at reset means that the system will boot up with an 8bit ROM. A low mode-clock (MOCLK) signal at reset means that the M68328 processor uses the 32.768kHz crystal and enables its internal PLL to supply the clock for the entire chip. The suggested circuit for PLL is shown in Figure 14-2.
Freescale Semiconductor, Inc. Applications and Design Examples IM IN 16.1.2.1 EPROM INTERFACE The M68328 processor supports both 8-bit and 16-bit devices. Any chip-select can be individually programmed for 8 or 16 bits; however, CSA0 can be programmed only by the externally supplied BBUSW signal. Figure 14-3 shows the connection of M68328 processor to EPROM. The OE signal controls the EPROM output-enable.
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Freescale Semiconductor, Inc. Applications and Design Examples 16.2 SYSTEM INITIALIZATION EXAMPLES 16.2.
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Freescale Semiconductor, Inc. Applications and Design Examples ;********************************************************************** #$00410000,LSSA #$14,LVPW #319,LXMAX #199,LYMAX #$14,LLBAR #$1b,LOTCR #2,LPXCD #$04,LPICF #$e0,LCKCON ;frame starting address ;virtual width ;xmax = 16 ;ymax = 16 ;LBAR ;RPTC ;pixel clock = 1/3 sysclk ;4 bit LCD data no grey ;enable lcdc, 16 words per DMA move.b clr.l clr.l clr.l clr.l clr.l clr.l clr.l clr.l move.l move.l move.l move.l move.w move.
Freescale Semiconductor, Inc. Applications and Design Examples jmp _main ; jmp to main program 16.2.2 Chip-Select Access Time Calculation The time path that is critical in the M68328 processor application using the CS signals is shown in Figure 14-5. The chip-select access time is from CS asserted to when data must be valid to the processor. S0 S1 S2 S3 S4 S5 S6 S7 Y ADDR 14 t1 DATA AR CSxx APPLICATIONS AND DESIGN EXAMPLES taccess IN t2 IM Figure 16-5.
Freescale Semiconductor, Inc. Applications and Design Examples where t2 = DATA setup requirement = 20 ns CLKO ADDR AR DATA t2 Figure 16-6. LCD Chip-Select Access Timing where WS = wait states IM tacess = (1 + WS) T – (t1 + t2) IN An equation for the access time, tacess, can be developed from Figure 14-6. This equation applies to EC000 core accesses. where T = system clock period where t1 = CSxx delay = 30ns where t2 = DATA setup requirement = 20ns 16.2.
Freescale Semiconductor, Inc. Applications and Design Examples interrupt status register (ISR) and the interrupt pending register (IPR). Among interrupt levels, their priority is shown in Figure 14-5, with Level 7 being the highest. Note: Keyboard down is the OR (negative logic) of all inputs on the keyboard port. 16.2.4.
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Freescale Semiconductor, Inc. Applications and Design Examples should poll the IRQ bit for an indication of a completed transfer. Do not poll the exchange bit for exchange completion.
Freescale Semiconductor, Inc. Applications and Design Examples 16.3 POWER-SAVING TIPS You can save power on the MC68328 by following these tips: • Keep the core shut down as much as possible by putting it in doze mode. Set the STOP bit in the power control register during any peiod of inactivity. • Shut down the PLL to enter sleep mode. Set the DISPLL bit in the PLL control register to conserve power when the processor is inactive for an extended period of time.
Freescale Semiconductor, Inc. Applications and Design Examples 16.3.1 LCD Refresh Frequency The following sequence of steps can be used to determine the values required for the PIXCLK divider (LCDC PXCD), last buffer address register (LBAR), and octet terminal count register (OTCR). These registers all affect the refresh rate of the LCD panel. The following example assumes a screes size of 240 × 160. 1. Calculate the pixel clock divider for grayscale.
SECTION 17 ELECTRICAL CHARACTERISTICS RATING AR Y 17.1 MAXIMUM RATINGS SYMBOL VALUE UNIT VCC –0.3 to 7.0 V Input Voltage Vin –0.3 to 7.0 V Maximum Operating Temperature Range TA TL to TH –0 to 70 °C Tstg –55 to 150 °C IM Storage Temperature IN Supply Voltage 17.2 POWER CONSUMPTION CHARACTERISTIC PR EL Freescale Semiconductor, Inc... This section provides information on the maximum ratings for the MC68328 processor. 3.
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Freescale Semiconductor, Inc. Electrical Characteristics S1 S2 S3 S4 S5 S6 S7 S1 S0 ELECTRICAL CHARACTERISTICS S0 CLKO 1 2 13 A31-A0 3 10 5 Y AS 16 R/W 12 4 13 CSxx 13 7 IM UDS/LDS IN 6 14 DTACK AR 11 PR EL Freescale Semiconductor, Inc... 9 8 18 19 20 D15-D0 23 15 OE UWE/LWE 24 25 21 22 Figure 17-1. Chip-Select Write Cycle Timing (when CPU is Bus Master) MOTOROLA MC68328 USER’S MANUAL 11/10/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. Electrical Characteristics Table 17-2.
Freescale Semiconductor, Inc. Electrical Characteristics S1 S2 S3 S4 S5 S6 S7 S1 S0 ELECTRICAL CHARACTERISTICS S0 CLKO 1 2 13 A31-A0 3 AS 16 10 Y 5 R/W 12 13 4 CSxx 13 IN 6 14 8 IM UDS/LDS DTACK AR 11 PR EL Freescale Semiconductor, Inc... 9 19 20 18 21 D15-D0 15 22 OE Figure 17-2. Chip-Select Read Cycle Timing (when the CPU is the Bus Master) MOTOROLA MC68328 USER’S MANUAL 11/10/97 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. Electrical Characteristics Table 17-3.
Freescale Semiconductor, Inc. Dn+15 Y Dn+14 Dn... AR Dn+1 3 4 IN An... 9 8 6 7 5 DMAn 1 An 2 Dn 3 IM An+1 1 13 12 An+15 An+14 DMAn... DMAn+14 DMAn+15 DMAn+1 DMAn PR EL OE D15-D0 CSxx R/W AS A31-A0 CLKO S7 Freescale Semiconductor, Inc... 10 13 S0 11 S1 S2 ELECTRICAL CHARACTERISTICS Electrical Characteristics Figure 17-3.
Freescale Semiconductor, Inc. Electrical Characteristics Table 17-4. AC Electrical Specifications—PCMCIA Write Cycle Timing Write Cycle Time Addr Setup Time to CE1, CE2 Asserted Addr Valid to WE Asserted WE Negated to Address Invalid Data Setup to WE Negated WE Negated to Data Invalid (Hold Time) CE1 , CE2 IN 3 D15-D0 IM WE MAX 150 40 0 90 0 30 — — 30 — 30 — ns ns ns ns ns ns AR A31-A0 2 MIN Y 1 UNIT ELECTRICAL CHARACTERISTICS 3.3 V 4 5 PR EL Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Electrical Characteristics ELECTRICAL CHARACTERISTICS 1 A31-A0 2 4 3 Y OE 5 AR D15-D0 6 IN Figure 17-5. PCMCIA Read Cycle Timing IM 17.5 DC ELECTRICAL SPECIFICATIONS CHARACTERISTIC SYMBOL MIN MAX UNIT VIH 2.0 VDD V VIL GND – 0.3 0.8 V VIHC 0.7 VDD VDD+ 0.3 V Input leakage current @3.3V (all input-only pins) IIN — -1.0 uA Three-state (off state) input current @2.4V/0.4V ITSI — -5.0 uA Output high voltage (IOH = 1.5mA) VOH 0.
Freescale Semiconductor, Inc. Y AR IN IM PR EL Freescale Semiconductor, Inc... 13 ELECTRICAL CHARACTERISTICS Electrical Characteristics MOTOROLA MC68328 USER’S MANUAL 11/10/97 For More Information On This Product, Go to: www.freescale.
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Mechanical SpecificationsFreescale Semiconductor, Inc. CASE 918-02 144 TQFP 0.20 (0.008) H L– M N 0.20 (0.008) H L– M N 144 109 P L, M, N 108 1 CL G DETAIL "A" 18 Freescale Semiconductor, Inc... B V DETAIL "B" MECHANICAL CHARACTERIISTICS F AA J B1 V1 DETAIL "A" BASE METAL (ROTATED 90°) 144 PL 0.08(0.003) M T L – M 73 36 D M N 72 37 A1 S1 A S C θ2 DETAIL "C" H ∩ 0.08 (0.003) T SEATING PLANE DETAIL "B" C2 0.05 (0.005) S θ R2 R1 0.25 (0.
18 MECHANICAL CHARACTERISTICS Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.Mechanical Specifications MOTOROLA MC68328 USER’S MANUAL 1/29/98 For More Information On This Product, Go to: www.freescale.
Mechanical SpecificationsFreescale Semiconductor, Inc. MECHANICAL CHARACTERIISTICS Freescale Semiconductor, Inc... 18 18-4 MC68328 USER’S MANUAL 1/29/98 For More Information On This Product, Go to: www.freescale.
